diff options
Diffstat (limited to 'arch/powerpc/sysdev/fsl_pci.h')
| -rw-r--r-- | arch/powerpc/sysdev/fsl_pci.h | 65 |
1 files changed, 56 insertions, 9 deletions
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h index 72b5625..c95738b 100644 --- a/arch/powerpc/sysdev/fsl_pci.h +++ b/arch/powerpc/sysdev/fsl_pci.h @@ -16,6 +16,10 @@ struct platform_device; +/* FSL PCI controller BRR1 register */ +#define PCI_FSL_BRR1 0xbf8 +#define PCI_FSL_BRR1_VER 0xffff + #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ #define PCIE_LTSSM_L0 0x16 /* L0 state */ #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */ @@ -47,6 +51,45 @@ struct pci_inbound_window_regs { u8 res2[12]; }; +/* PCI Error Management Registers */ +struct pci_err_regs { + /* 0x.e00 - PCI Error Detect Register */ + __be32 pedr; + /* 0x.e04 - PCI Error Capture Disable Register */ + __be32 pecdr; + /* 0x.e08 - PCI Error Interrupt Enable Register */ + __be32 peer; + /* 0x.e0c - PCI Error Attributes Capture Register */ + __be32 peattrcr; + /* 0x.e10 - PCI Error Address Capture Register */ + __be32 peaddrcr; + /* 0x.e14 - PCI Error Extended Address Capture Register */ + __be32 peextaddrcr; + /* 0x.e18 - PCI Error Data Low Capture Register */ + __be32 pedlcr; + /* 0x.e1c - PCI Error Data High Capture Register */ + __be32 pedhcr; + /* 0x.e20 - PCI Gasket Timer Register */ + __be32 gas_timr; + u8 res21[4]; +}; + +/* PCI Express Error Management Registers */ +struct pcie_err_regs { + /* 0x.e00 - PCI/PCIE error detect register */ + __be32 pex_err_dr; + u8 res21[4]; + /* 0x.e08 - PCI/PCIE error interrupt enable register */ + __be32 pex_err_en; + u8 res22[4]; + /* 0x.e10 - PCI/PCIE error disable register */ + __be32 pex_err_disr; + u8 res23[12]; + /* 0x.e20 - PCI/PCIE error capture status register */ + __be32 pex_err_cap_stat; + u8 res24[4]; +}; + /* PCI/PCI Express IO block registers for 85xx/86xx */ struct ccsr_pci { __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */ @@ -79,15 +122,11 @@ struct ccsr_pci { * define an inbound window base extended address register. */ struct pci_inbound_window_regs piw[4]; - - __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */ - u8 res21[4]; - __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */ - u8 res22[4]; - __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */ - u8 res23[12]; - __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */ - u8 res24[4]; +/* PCI/PCI Express Error Management Registers */ + union { + struct pci_err_regs pcier; + struct pcie_err_regs pexer; + }; __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */ __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */ __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */ @@ -111,6 +150,8 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose); extern struct device_node *fsl_pci_primary; +extern unsigned int qemu_e500_pci; + #ifdef CONFIG_PCI void fsl_pci_assign_primary(void); #else @@ -126,5 +167,11 @@ static inline int mpc85xx_pci_err_probe(struct platform_device *op) } #endif +#ifdef CONFIG_FSL_PCI +extern int fsl_pci_mcheck_exception(struct pt_regs *); +#else +static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; } +#endif + #endif /* __POWERPC_FSL_PCI_H */ #endif /* __KERNEL__ */ |