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-rw-r--r--arch/sh/mm/cache-sh4.c5
-rw-r--r--arch/sh/mm/fault.c5
2 files changed, 8 insertions, 2 deletions
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index c036c2b..2203bd6 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -269,6 +269,11 @@ static inline void flush_icache_all(void)
ccr |= CCR_CACHE_ICI;
ctrl_outl(ccr, CCR);
+ /*
+ * back_to_P1() will take care of the barrier for us, don't add
+ * another one!
+ */
+
back_to_P1();
local_irq_restore(flags);
}
diff --git a/arch/sh/mm/fault.c b/arch/sh/mm/fault.c
index 775f86c..364181f 100644
--- a/arch/sh/mm/fault.c
+++ b/arch/sh/mm/fault.c
@@ -369,12 +369,13 @@ void flush_tlb_all(void)
* Flush all the TLB.
*
* Write to the MMU control register's bit:
- * TF-bit for SH-3, TI-bit for SH-4.
+ * TF-bit for SH-3, TI-bit for SH-4.
* It's same position, bit #2.
*/
local_irq_save(flags);
status = ctrl_inl(MMUCR);
- status |= 0x04;
+ status |= 0x04;
ctrl_outl(status, MMUCR);
+ ctrl_barrier();
local_irq_restore(flags);
}