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-rwxr-xr-xarch/arm/boot/dts/ls1021a-twr.dts79
-rw-r--r--arch/arm/boot/dts/ls1021a.dtsi2
-rw-r--r--arch/arm/mach-imx/mach-ls1021a.c23
-rw-r--r--arch/arm/mach-imx/pm-ls1.c56
4 files changed, 111 insertions, 49 deletions
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index 6486178..611433c 100755
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -1,5 +1,5 @@
/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -112,6 +112,10 @@
status = "okay";
};
+&ftm0 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
};
@@ -157,52 +161,69 @@
device-width = <1>;
partition@0 {
- /* 128KB for rcw */
- reg = <0x00000000 0x0020000>;
+ /* 128KB for bank0 RCW */
+ reg = <0x00000000 0x00020000>;
label = "NOR bank0 RCW Image";
};
- partition@20000 {
- /* 1MB for DTB */
- reg = <0x00020000 0x00100000>;
- label = "NOR DTB Image";
+ partition@100000 {
+ /* 1MB for bank0 u-boot Image */
+ reg = <0x00100000 0x00100000>;
+ label = "NOR bank0 u-boot Image";
};
- partition@120000 {
- /* 8 MB for Linux Kernel Image */
- reg = <0x00120000 0x00800000>;
- label = "NOR Linux Kernel Image";
+ partition@200000 {
+ /* 1MB for bank0 DTB */
+ reg = <0x00200000 0x00100000>;
+ label = "NOR bank0 DTB Image";
};
- partition@920000 {
- /* 56MB for Ramdisk Root File System */
- reg = <0x00920000 0x03600000>;
- label = "NOR Ramdisk Root File System Image";
+ partition@300000 {
+ /* 7MB for bank0 Linux Kernel */
+ reg = <0x00300000 0x00700000>;
+ label = "NOR bank0 Linux Kernel Image";
};
- partition@3f80000 {
- /* 512KB for bank4 u-boot Image */
- reg = <0x03f80000 0x80000>;
- label = "NOR bank4 u-boot Image";
+ partition@a00000 {
+ /* 54MB for bank0 Ramdisk Root File System */
+ reg = <0x00a00000 0x03600000>;
+ label = "NOR bank0 Ramdisk Root File System Image";
};
partition@4000000 {
- /* 128KB for bank4 RCW Image */
- reg = <0x04000000 0x20000>;
+ /* 128KB for bank4 RCW */
+ reg = <0x04000000 0x00020000>;
label = "NOR bank4 RCW Image";
};
- partition@4020000 {
- /* 63MB JFFS2 ROOT File System Image */
- reg = <0x04020000 0x3f00000>;
- label = "NOR JFFS2 ROOT File System Image";
+ partition@4100000 {
+ /* 1MB for bank4 u-boot Image */
+ reg = <0x04100000 0x00100000>;
+ label = "NOR bank4 u-boot Image";
};
- partition@7f80000 {
- /* 512KB for bank0 u-boot Image */
- reg = <0x07f80000 0x80000>;
- label = "NOR bank0 u-boot Image";
+ partition@4200000 {
+ /* 1MB for bank4 DTB */
+ reg = <0x04200000 0x00100000>;
+ label = "NOR bank4 DTB Image";
};
+
+ partition@4300000 {
+ /* 7MB for bank4 Linux Kernel */
+ reg = <0x04300000 0x00700000>;
+ label = "NOR bank4 Linux Kernel Image";
+ };
+
+ partition@4a00000 {
+ /* 54MB for bank4 Ramdisk Root File System */
+ reg = <0x04a00000 0x03600000>;
+ label = "NOR bank4 Ramdisk Root File System Image";
+ };
+ };
+
+ cpld@2,0 {
+ compatible = "fsl,ls1021atwr-cpld";
+ reg = <0x2 0x0 0x100>;
};
};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c98b794..c3a31b8 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -555,7 +555,6 @@
dma-names = "tx", "rx";
dmas = <&edma0 1 47>,
<&edma0 1 46>;
- big-endian-regs;
status = "disabled";
};
@@ -568,7 +567,6 @@
dma-names = "tx", "rx";
dmas = <&edma0 1 45>,
<&edma0 1 44>;
- big-endian-regs;
status = "disabled";
};
diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
index 3692dd0..dbb0256 100644
--- a/arch/arm/mach-imx/mach-ls1021a.c
+++ b/arch/arm/mach-imx/mach-ls1021a.c
@@ -10,13 +10,36 @@
#include <linux/clk-provider.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
+#include <linux/dma-mapping.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "common.h"
+static int ls1021a_platform_notifier(struct notifier_block *nb,
+ unsigned long event, void *__dev)
+{
+ struct device *dev = __dev;
+
+ if (event != BUS_NOTIFY_ADD_DEVICE)
+ return NOTIFY_DONE;
+
+ if (of_device_is_compatible(dev->of_node, "fsl,etsec2"))
+ set_dma_ops(dev, &arm_coherent_dma_ops);
+ else if (of_property_read_bool(dev->of_node, "dma-coherent"))
+ set_dma_ops(dev, &arm_coherent_dma_ops);
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block ls1021a_platform_nb = {
+ .notifier_call = ls1021a_platform_notifier,
+};
+
static void __init ls1021a_init_machine(void)
{
+ bus_register_notifier(&platform_bus_type, &ls1021a_platform_nb);
+
mxc_arch_reset_init_dt();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
diff --git a/arch/arm/mach-imx/pm-ls1.c b/arch/arm/mach-imx/pm-ls1.c
index b8bfdb5..50b0758 100644
--- a/arch/arm/mach-imx/pm-ls1.c
+++ b/arch/arm/mach-imx/pm-ls1.c
@@ -101,7 +101,7 @@ static struct ls1_pm_baseaddr ls1_pm_base;
static unsigned int sleep_modes;
static suspend_state_t ls1_pm_state;
-static void ls1_pm_iomap(void)
+static int ls1_pm_iomap(void)
{
struct device_node *np;
void *base;
@@ -130,13 +130,24 @@ static void ls1_pm_iomap(void)
ls1_pm_base.dcfg = base;
np = of_find_compatible_node(NULL, NULL, "fsl,ls1021aqds-fpga");
- base = of_iomap(np, 0);
- BUG_ON(!base);
- ls1_pm_base.fpga = base;
+ if (np) {
+ base = of_iomap(np, 0);
+ BUG_ON(!base);
+ ls1_pm_base.fpga = base;
+ } else {
+ np = of_find_compatible_node(NULL, NULL,
+ "fsl,ls1021atwr-cpld");
+ if (!np) {
+ pr_err("%s: Can not find cpld/fpga node.\n", __func__);
+ return -ENODEV;
+ }
+ }
base = ioremap(SRAM_CODE_BASE_PHY, PAGE_SIZE);
BUG_ON(!base);
ls1_pm_base.sram = base;
+
+ return 0;
}
static void ls1_pm_uniomap(void)
@@ -146,7 +157,10 @@ static void ls1_pm_uniomap(void)
iounmap(ls1_pm_base.dcsr_rcpm2);
iounmap(ls1_pm_base.scfg);
iounmap(ls1_pm_base.dcfg);
- iounmap(ls1_pm_base.fpga);
+
+ if (ls1_pm_base.fpga)
+ iounmap(ls1_pm_base.fpga);
+
iounmap(ls1_pm_base.sram);
}
@@ -299,15 +313,18 @@ static void ls1_enter_deepsleep(void)
/* setup the registers of the EPU FSM for deep sleep */
ls1_fsm_setup();
- /* connect the EVENT button to IRQ in FPGA */
- tmp = ioread8(ls1_pm_base.fpga + QIXIS_CTL_SYS);
- tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
- tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
- iowrite8(tmp, ls1_pm_base.fpga + QIXIS_CTL_SYS);
-
- /* enable deep sleep signals in FPGA */
- tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
- iowrite8(tmp | QIXIS_PWR_CTL2_PCTL, ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ if (ls1_pm_base.fpga) {
+ /* connect the EVENT button to IRQ in FPGA */
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_CTL_SYS);
+ tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
+ tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
+ iowrite8(tmp, ls1_pm_base.fpga + QIXIS_CTL_SYS);
+
+ /* enable deep sleep signals in FPGA */
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ iowrite8(tmp | QIXIS_PWR_CTL2_PCTL,
+ ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ }
/* enable Warm Device Reset */
ls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,
@@ -329,9 +346,12 @@ static void ls1_enter_deepsleep(void)
ls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,
CCSR_SCFG_DPSLPCR_VAL, 0);
- /* disable deep sleep signals in FPGA */
- tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
- iowrite8(tmp & ~QIXIS_PWR_CTL2_PCTL, ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ if (ls1_pm_base.fpga) {
+ /* disable deep sleep signals in FPGA */
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ iowrite8(tmp & ~QIXIS_PWR_CTL2_PCTL,
+ ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ }
}
static void ls1_set_power_except(struct device *dev, int on)
@@ -414,7 +434,7 @@ static int ls1_suspend_begin(suspend_state_t state)
dpm_for_each_dev(NULL, ls1_set_wakeup_device);
if (ls1_pm_state == PM_SUSPEND_MEM)
- ls1_pm_iomap();
+ return ls1_pm_iomap();
return 0;
}
generated by cgit v0.10.2 at 2024-06-08 17:27:32 (GMT)