summaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/ls1021a-qds.dts8
-rwxr-xr-xarch/arm/boot/dts/ls1021a-twr.dts122
-rw-r--r--arch/arm/boot/dts/ls1021a.dtsi102
-rw-r--r--arch/arm/configs/ls1021a_defconfig1
-rw-r--r--arch/arm/mach-imx/mach-ls1021a.c23
-rw-r--r--arch/arm/mach-imx/pm-ls1.c118
-rw-r--r--arch/arm/mach-imx/sleep-ls1.S23
7 files changed, 290 insertions, 107 deletions
diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
index 93cda05..c029e65 100644
--- a/arch/arm/boot/dts/ls1021a-qds.dts
+++ b/arch/arm/boot/dts/ls1021a-qds.dts
@@ -436,6 +436,14 @@
status = "okay";
};
+&can2 {
+ status = "disabled";
+};
+
+&can3 {
+ status = "disabled";
+};
+
&sai2 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
index 6486178..db1c6b6 100755
--- a/arch/arm/boot/dts/ls1021a-twr.dts
+++ b/arch/arm/boot/dts/ls1021a-twr.dts
@@ -1,5 +1,5 @@
/*
- * Copyright 2013-2014 Freescale Semiconductor, Inc.
+ * Copyright 2013-2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -58,6 +58,22 @@
};
};
+&can0 {
+ status = "okay";
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "disabled";
+};
+
+&can3 {
+ status = "disabled";
+};
+
&dcu0 {
display = <&display>;
status = "okay";
@@ -112,8 +128,24 @@
status = "okay";
};
+&ftm0 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
+
+ ina220@40 {
+ compatible = "ti,ina220";
+ reg = <0x40>;
+ shunt-resistor = <1000>;
+ };
+
+ ina220@41 {
+ compatible = "ti,ina220";
+ reg = <0x41>;
+ shunt-resistor = <1000>;
+ };
};
&i2c1 {
@@ -157,52 +189,69 @@
device-width = <1>;
partition@0 {
- /* 128KB for rcw */
- reg = <0x00000000 0x0020000>;
+ /* 128KB for bank0 RCW */
+ reg = <0x00000000 0x00020000>;
label = "NOR bank0 RCW Image";
};
- partition@20000 {
- /* 1MB for DTB */
- reg = <0x00020000 0x00100000>;
- label = "NOR DTB Image";
+ partition@100000 {
+ /* 1MB for bank0 u-boot Image */
+ reg = <0x00100000 0x00100000>;
+ label = "NOR bank0 u-boot Image";
};
- partition@120000 {
- /* 8 MB for Linux Kernel Image */
- reg = <0x00120000 0x00800000>;
- label = "NOR Linux Kernel Image";
+ partition@200000 {
+ /* 1MB for bank0 DTB */
+ reg = <0x00200000 0x00100000>;
+ label = "NOR bank0 DTB Image";
};
- partition@920000 {
- /* 56MB for Ramdisk Root File System */
- reg = <0x00920000 0x03600000>;
- label = "NOR Ramdisk Root File System Image";
+ partition@300000 {
+ /* 7MB for bank0 Linux Kernel */
+ reg = <0x00300000 0x00700000>;
+ label = "NOR bank0 Linux Kernel Image";
};
- partition@3f80000 {
- /* 512KB for bank4 u-boot Image */
- reg = <0x03f80000 0x80000>;
- label = "NOR bank4 u-boot Image";
+ partition@a00000 {
+ /* 54MB for bank0 Ramdisk Root File System */
+ reg = <0x00a00000 0x03600000>;
+ label = "NOR bank0 Ramdisk Root File System Image";
};
partition@4000000 {
- /* 128KB for bank4 RCW Image */
- reg = <0x04000000 0x20000>;
+ /* 128KB for bank4 RCW */
+ reg = <0x04000000 0x00020000>;
label = "NOR bank4 RCW Image";
};
- partition@4020000 {
- /* 63MB JFFS2 ROOT File System Image */
- reg = <0x04020000 0x3f00000>;
- label = "NOR JFFS2 ROOT File System Image";
+ partition@4100000 {
+ /* 1MB for bank4 u-boot Image */
+ reg = <0x04100000 0x00100000>;
+ label = "NOR bank4 u-boot Image";
};
- partition@7f80000 {
- /* 512KB for bank0 u-boot Image */
- reg = <0x07f80000 0x80000>;
- label = "NOR bank0 u-boot Image";
+ partition@4200000 {
+ /* 1MB for bank4 DTB */
+ reg = <0x04200000 0x00100000>;
+ label = "NOR bank4 DTB Image";
+ };
+
+ partition@4300000 {
+ /* 7MB for bank4 Linux Kernel */
+ reg = <0x04300000 0x00700000>;
+ label = "NOR bank4 Linux Kernel Image";
};
+
+ partition@4a00000 {
+ /* 54MB for bank4 Ramdisk Root File System */
+ reg = <0x04a00000 0x03600000>;
+ label = "NOR bank4 Ramdisk Root File System Image";
+ };
+ };
+
+ cpld@2,0 {
+ compatible = "fsl,ls1021atwr-cpld";
+ reg = <0x2 0x0 0x100>;
};
};
@@ -271,6 +320,21 @@
};
};
+&dspi1 {
+ bus-num = <0>;
+ status = "okay";
+
+ dspiflash: compatible@0 {
+ compatible = "st,m25p80";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <3000000>;
+ spi-cpol;
+ spi-cpha;
+ reg = <0>;
+ };
+};
+
&sai1 {
status = "okay";
};
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index c98b794..eddd576 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -257,6 +257,7 @@
clocks = <&platform_clk 1>;
spi-num-chipselects = <5>;
big-endian;
+ tcfq-mode;
status = "disabled";
};
@@ -555,7 +556,6 @@
dma-names = "tx", "rx";
dmas = <&edma0 1 47>,
<&edma0 1 46>;
- big-endian-regs;
status = "disabled";
};
@@ -568,7 +568,6 @@
dma-names = "tx", "rx";
dmas = <&edma0 1 45>,
<&edma0 1 44>;
- big-endian-regs;
status = "disabled";
};
@@ -618,22 +617,28 @@
fsl,magic-packet;
fsl,wake-on-filer;
sleep = <&rcpm 0x80000000 0x0>;
- fsl,num_rx_queues = <0x1>;
- fsl,num_tx_queues = <0x1>;
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
ranges;
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0 0x2d10000 0x0 0x8000>;
- fsl,rx-bit-map = <0xff>;
- fsl,tx-bit-map = <0xff>;
+ queue-group@2d10000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d10000 0x0 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
};
+ queue-group@2d14000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d14000 0x0 0x1000>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
enet1: ethernet@2d50000 {
@@ -644,22 +649,28 @@
interrupt-parent = <&gic>;
model = "eTSEC";
fsl,dma-endian-le;
- fsl,num_rx_queues = <0x1>;
- fsl,num_tx_queues = <0x1>;
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
ranges;
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0 0x2d50000 0x0 0x8000>;
- fsl,rx-bit-map = <0xff>;
- fsl,tx-bit-map = <0xff>;
+ queue-group@2d50000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d50000 0x0 0x1000>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
};
+ queue-group@2d54000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d54000 0x0 0x1000>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
enet2: ethernet@2d90000 {
@@ -670,65 +681,64 @@
interrupt-parent = <&gic>;
model = "eTSEC";
fsl,dma-endian-le;
- fsl,num_rx_queues = <0x1>;
- fsl,num_tx_queues = <0x1>;
+ fsl,num_rx_queues = <0x8>;
+ fsl,num_tx_queues = <0x8>;
local-mac-address = [ 00 00 00 00 00 00 ];
ranges;
- queue-group@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0 0x2d90000 0x0 0x8000>;
- fsl,rx-bit-map = <0xff>;
- fsl,tx-bit-map = <0xff>;
+ queue-group@2d90000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d90000 0x0 0x1000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ queue-group@2d94000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x2d94000 0x0 0x1000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
can0: can@2a70000 {
- compatible = "fsl,ls1021a-flexcan";
+ compatible = "fsl,ls1021ar2-flexcan";
reg = <0x0 0x2a70000 0x0 0x1000>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
- clock-frequency = <150000000>;
- clock-names = "per";
+ clocks = <&platform_clk 1>, <&platform_clk 1>;
+ clock-names = "ipg", "per";
little-endian;
- status = "disabled";
};
can1: can@2a80000 {
- compatible = "fsl,ls1021a-flexcan";
+ compatible = "fsl,ls1021ar2-flexcan";
reg = <0x0 0x2a80000 0x0 0x1000>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
- clock-frequency = <150000000>;
- clock-names = "per";
+ clocks = <&platform_clk 1>, <&platform_clk 1>;
+ clock-names = "ipg", "per";
little-endian;
- status = "disabled";
};
can2: can@2a90000 {
- compatible = "fsl,ls1021a-flexcan";
+ compatible = "fsl,ls1021ar2-flexcan";
reg = <0x0 0x2a90000 0x0 0x1000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
- clock-frequency = <150000000>;
- clock-names = "per";
+ clocks = <&platform_clk 1>, <&platform_clk 1>;
+ clock-names = "ipg", "per";
little-endian;
- status = "disabled";
};
can3: can@2aa0000 {
- compatible = "fsl,ls1021a-flexcan";
+ compatible = "fsl,ls1021ar2-flexcan";
reg = <0x0 0x2aa0000 0x0 0x1000>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&platform_clk 1>;
- clock-frequency = <150000000>;
- clock-names = "per";
+ clocks = <&platform_clk 1>, <&platform_clk 1>;
+ clock-names = "ipg", "per";
little-endian;
- status = "disabled";
};
usb@8600000 {
diff --git a/arch/arm/configs/ls1021a_defconfig b/arch/arm/configs/ls1021a_defconfig
index 12f5f84..8721e23 100644
--- a/arch/arm/configs/ls1021a_defconfig
+++ b/arch/arm/configs/ls1021a_defconfig
@@ -104,6 +104,7 @@ CONFIG_SATA_SIL24=y
CONFIG_NETDEVICES=y
CONFIG_GIANFAR=y
CONFIG_E1000E=y
+CONFIG_AT803X_PHY=y
CONFIG_VITESSE_PHY=y
CONFIG_BROADCOM_PHY=y
CONFIG_REALTEK_PHY=y
diff --git a/arch/arm/mach-imx/mach-ls1021a.c b/arch/arm/mach-imx/mach-ls1021a.c
index 3692dd0..dbb0256 100644
--- a/arch/arm/mach-imx/mach-ls1021a.c
+++ b/arch/arm/mach-imx/mach-ls1021a.c
@@ -10,13 +10,36 @@
#include <linux/clk-provider.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
+#include <linux/dma-mapping.h>
#include <linux/of_platform.h>
#include <asm/mach/arch.h>
#include "common.h"
+static int ls1021a_platform_notifier(struct notifier_block *nb,
+ unsigned long event, void *__dev)
+{
+ struct device *dev = __dev;
+
+ if (event != BUS_NOTIFY_ADD_DEVICE)
+ return NOTIFY_DONE;
+
+ if (of_device_is_compatible(dev->of_node, "fsl,etsec2"))
+ set_dma_ops(dev, &arm_coherent_dma_ops);
+ else if (of_property_read_bool(dev->of_node, "dma-coherent"))
+ set_dma_ops(dev, &arm_coherent_dma_ops);
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block ls1021a_platform_nb = {
+ .notifier_call = ls1021a_platform_notifier,
+};
+
static void __init ls1021a_init_machine(void)
{
+ bus_register_notifier(&platform_bus_type, &ls1021a_platform_nb);
+
mxc_arch_reset_init_dt();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
diff --git a/arch/arm/mach-imx/pm-ls1.c b/arch/arm/mach-imx/pm-ls1.c
index b8bfdb5..d1af079 100644
--- a/arch/arm/mach-imx/pm-ls1.c
+++ b/arch/arm/mach-imx/pm-ls1.c
@@ -48,6 +48,8 @@
#define CCSR_SCFG_PMCINTSR 0x168
#define CCSR_SCFG_SPARECR2 0x504
#define CCSR_SCFG_SPARECR3 0x508
+#define CCSR_SCFG_CLUSTERPMCR 0x904
+#define CCSR_SCFG_CLUSTERPMCR_WFIL2EN 0x80000000
#define CCSR_DCFG_CRSTSR 0x400
#define CCSR_DCFG_CRSTSR_VAL 0x00000008
@@ -65,6 +67,9 @@
#define CCSR_RCPM_IPPDEXPCR1_LPUART 0x40000000
#define CCSR_RCPM_IPPDEXPCR1_FLEXTIMER 0x20000000
#define CCSR_RCPM_IPPDEXPCR1_OCRAM1 0x10000000
+#define CCSR_RCPM_NFIQOUTR 0x15c
+#define CCSR_RCPM_NIRQOUTR 0x16c
+#define CCSR_RCPM_DSIMSKR 0x18c
#define QIXIS_CTL_SYS 0x5
#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c
@@ -101,11 +106,19 @@ static struct ls1_pm_baseaddr ls1_pm_base;
static unsigned int sleep_modes;
static suspend_state_t ls1_pm_state;
-static void ls1_pm_iomap(void)
+static int ls1_pm_iomap(int deepsleep)
{
struct device_node *np;
void *base;
+ np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-scfg");
+ base = of_iomap(np, 0);
+ BUG_ON(!base);
+ ls1_pm_base.scfg = base;
+
+ if (!deepsleep)
+ return 0;
+
np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcsr-epu");
base = of_iomap(np, 0);
BUG_ON(!base);
@@ -119,41 +132,59 @@ static void ls1_pm_iomap(void)
BUG_ON(!base);
ls1_pm_base.dcsr_rcpm2 = base;
- np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-scfg");
- base = of_iomap(np, 0);
- BUG_ON(!base);
- ls1_pm_base.scfg = base;
-
np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
base = of_iomap(np, 0);
BUG_ON(!base);
ls1_pm_base.dcfg = base;
np = of_find_compatible_node(NULL, NULL, "fsl,ls1021aqds-fpga");
- base = of_iomap(np, 0);
- BUG_ON(!base);
- ls1_pm_base.fpga = base;
+ if (np) {
+ base = of_iomap(np, 0);
+ BUG_ON(!base);
+ ls1_pm_base.fpga = base;
+ } else {
+ np = of_find_compatible_node(NULL, NULL,
+ "fsl,ls1021atwr-cpld");
+ if (!np) {
+ pr_err("%s: Can not find cpld/fpga node.\n", __func__);
+ return -ENODEV;
+ }
+ }
base = ioremap(SRAM_CODE_BASE_PHY, PAGE_SIZE);
BUG_ON(!base);
ls1_pm_base.sram = base;
+
+ return 0;
}
-static void ls1_pm_uniomap(void)
+static void ls1_pm_uniomap(int deepsleep)
{
+ iounmap(ls1_pm_base.scfg);
+ if (!deepsleep)
+ return;
+
iounmap(ls1_pm_base.epu);
iounmap(ls1_pm_base.dcsr_rcpm1);
iounmap(ls1_pm_base.dcsr_rcpm2);
- iounmap(ls1_pm_base.scfg);
iounmap(ls1_pm_base.dcfg);
- iounmap(ls1_pm_base.fpga);
+
+ if (ls1_pm_base.fpga)
+ iounmap(ls1_pm_base.fpga);
+
iounmap(ls1_pm_base.sram);
}
-static void ls1_setup_pmc_int(void)
+static void ls1_deepsleep_irq(void)
{
u32 pmcintecr;
+ /* mask interrupts from GIC */
+ iowrite32be(0x0ffffffff, ls1_pm_base.rcpm + CCSR_RCPM_NFIQOUTR);
+ iowrite32be(0x0ffffffff, ls1_pm_base.rcpm + CCSR_RCPM_NIRQOUTR);
+ /* mask deep sleep wake-up interrupts during deep sleep entry */
+ iowrite32be(0x0ffffffff, ls1_pm_base.rcpm + CCSR_RCPM_DSIMSKR);
+
pmcintecr = 0;
if (ippdexpcr0 & CCSR_RCPM_IPPDEXPCR0_ETSEC)
pmcintecr |= CCSR_SCFG_PMCINTECR_ETSECRXG0 |
@@ -173,11 +204,12 @@ static void ls1_setup_pmc_int(void)
/* always set external IRQ pins as wakeup source */
pmcintecr |= CCSR_SCFG_PMCINTECR_IRQ0 | CCSR_SCFG_PMCINTECR_IRQ1;
- /* enable wakeup interrupt during deep sleep */
- iowrite32be(pmcintecr, ls1_pm_base.scfg + CCSR_SCFG_PMCINTECR);
iowrite32be(0, ls1_pm_base.scfg + CCSR_SCFG_PMCINTLECR);
/* clear PMC interrupt status */
iowrite32be(0xffffffff, ls1_pm_base.scfg + CCSR_SCFG_PMCINTSR);
+ /* enable wakeup interrupt during deep sleep */
+ iowrite32be(pmcintecr, ls1_pm_base.scfg + CCSR_SCFG_PMCINTECR);
+
}
static void ls1_clear_pmc_int(void)
@@ -299,15 +331,18 @@ static void ls1_enter_deepsleep(void)
/* setup the registers of the EPU FSM for deep sleep */
ls1_fsm_setup();
- /* connect the EVENT button to IRQ in FPGA */
- tmp = ioread8(ls1_pm_base.fpga + QIXIS_CTL_SYS);
- tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
- tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
- iowrite8(tmp, ls1_pm_base.fpga + QIXIS_CTL_SYS);
-
- /* enable deep sleep signals in FPGA */
- tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
- iowrite8(tmp | QIXIS_PWR_CTL2_PCTL, ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ if (ls1_pm_base.fpga) {
+ /* connect the EVENT button to IRQ in FPGA */
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_CTL_SYS);
+ tmp &= ~QIXIS_CTL_SYS_EVTSW_MASK;
+ tmp |= QIXIS_CTL_SYS_EVTSW_IRQ;
+ iowrite8(tmp, ls1_pm_base.fpga + QIXIS_CTL_SYS);
+
+ /* enable deep sleep signals in FPGA */
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ iowrite8(tmp | QIXIS_PWR_CTL2_PCTL,
+ ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ }
/* enable Warm Device Reset */
ls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,
@@ -319,7 +354,7 @@ static void ls1_enter_deepsleep(void)
/* copy the last stage code to sram */
ls1_copy_sram_code();
- ls1_setup_pmc_int();
+ ls1_deepsleep_irq();
cpu_suspend(SRAM_CODE_BASE_PHY, ls1_start_deepsleep);
@@ -329,9 +364,12 @@ static void ls1_enter_deepsleep(void)
ls1_clrsetbits_be32(ls1_pm_base.scfg + CCSR_SCFG_DPSLPCR,
CCSR_SCFG_DPSLPCR_VAL, 0);
- /* disable deep sleep signals in FPGA */
- tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
- iowrite8(tmp & ~QIXIS_PWR_CTL2_PCTL, ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ if (ls1_pm_base.fpga) {
+ /* disable deep sleep signals in FPGA */
+ tmp = ioread8(ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ iowrite8(tmp & ~QIXIS_PWR_CTL2_PCTL,
+ ls1_pm_base.fpga + QIXIS_PWR_CTL2);
+ }
}
static void ls1_set_power_except(struct device *dev, int on)
@@ -367,11 +405,26 @@ static void ls1_set_wakeup_device(struct device *dev, void *enable)
ls1_set_power_except(dev, *((int *)enable));
}
+/* enable cluster to enter the PCL10 state */
+void ls1_set_clusterpm(int enable)
+{
+ u32 val;
+
+ if (enable)
+ val = CCSR_SCFG_CLUSTERPMCR_WFIL2EN;
+ else
+ val = 0;
+
+ BUG_ON(!ls1_pm_base.scfg);
+ iowrite32be(val, ls1_pm_base.scfg + CCSR_SCFG_CLUSTERPMCR);
+}
+
static int ls1_suspend_enter(suspend_state_t state)
{
int ret = 0;
ls1_set_powerdown();
+ ls1_set_clusterpm(1);
switch (state) {
case PM_SUSPEND_STANDBY:
@@ -391,6 +444,7 @@ static int ls1_suspend_enter(suspend_state_t state)
ret = -EINVAL;
}
+ ls1_set_clusterpm(0);
return ret;
}
@@ -414,7 +468,9 @@ static int ls1_suspend_begin(suspend_state_t state)
dpm_for_each_dev(NULL, ls1_set_wakeup_device);
if (ls1_pm_state == PM_SUSPEND_MEM)
- ls1_pm_iomap();
+ return ls1_pm_iomap(1);
+ else if (ls1_pm_state == PM_SUSPEND_STANDBY)
+ return ls1_pm_iomap(0);
return 0;
}
@@ -422,7 +478,9 @@ static int ls1_suspend_begin(suspend_state_t state)
static void ls1_suspend_end(void)
{
if (ls1_pm_state == PM_SUSPEND_MEM)
- ls1_pm_uniomap();
+ ls1_pm_uniomap(1);
+ else if (ls1_pm_state == PM_SUSPEND_STANDBY)
+ ls1_pm_uniomap(0);
}
static const struct platform_suspend_ops ls1_suspend_ops = {
diff --git a/arch/arm/mach-imx/sleep-ls1.S b/arch/arm/mach-imx/sleep-ls1.S
index b8d7f1a..f8fd8a4 100644
--- a/arch/arm/mach-imx/sleep-ls1.S
+++ b/arch/arm/mach-imx/sleep-ls1.S
@@ -25,6 +25,10 @@
#define DCSR_EPU_EPECR0 0x300
#define DCSR_EPU_EPECR15 0x33c
+#define CCSR_GIC_BASE 0x1400000
+#define CCSR_GICD_CTLR 0x1000
+#define CCSR_GICC_CTLR 0x2000
+
/* for big endian registers */
.macro ls1_set_bits, addr, value
ldr r4, \addr
@@ -85,6 +89,13 @@ ENTRY(ls1_start_fsm)
ls1_delay #2000
+ mov r7, #0
+ ldr r8, ls1_ccsr_gicd_ctlr
+ str r7, [r8]
+ ldr r9, ls1_ccsr_gicc_ctlr
+ str r7, [r9]
+ dsb
+
/* Enable all EPU Counters */
ls1_set_bits ls1_dcsr_epu_epgcr_addr, ls1_dcsr_epu_epgcr_val
@@ -92,8 +103,10 @@ ENTRY(ls1_start_fsm)
ls1_set_bits ls1_dcsr_epu_epecr15, ls1_dcsr_epu_epecr15_val
/* Enter WFI mode, and EPU FSM will start */
-20: wfi
- b 20b
+ isb
+ wfi
+ nop
+20: b 20b
ls1_ccsr_scfg_hrstcr_addr:
.word CCSR_SCFG_BASE + CCSR_SCFG_HRSTCR
@@ -120,6 +133,12 @@ ls1_dcsr_epu_epecr15:
ls1_dcsr_epu_epecr15_val:
.word 0x90000004
+ls1_ccsr_gicd_ctlr:
+ .word CCSR_GIC_BASE + CCSR_GICD_CTLR
+
+ls1_ccsr_gicc_ctlr:
+ .word CCSR_GIC_BASE + CCSR_GICC_CTLR
+
ENTRY(ls1_sram_code_size)
.word . - ls1_start_fsm
generated by cgit v0.10.2 at 2024-06-01 19:05:07 (GMT)