diff options
Diffstat (limited to 'drivers/cpufreq/exynos4x12-cpufreq.c')
-rw-r--r-- | drivers/cpufreq/exynos4x12-cpufreq.c | 70 |
1 files changed, 62 insertions, 8 deletions
diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c index efad5e6..08b7477 100644 --- a/drivers/cpufreq/exynos4x12-cpufreq.c +++ b/drivers/cpufreq/exynos4x12-cpufreq.c @@ -128,9 +128,9 @@ static void exynos4x12_set_clkdiv(unsigned int div_index) static void exynos4x12_set_apll(unsigned int index) { - unsigned int tmp, freq = apll_freq_4x12[index].freq; + unsigned int tmp, pdiv; - /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ + /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */ clk_set_parent(moutcore, mout_mpll); do { @@ -140,9 +140,24 @@ static void exynos4x12_set_apll(unsigned int index) tmp &= 0x7; } while (tmp != 0x2); - clk_set_rate(mout_apll, freq * 1000); + /* 2. Set APLL Lock time */ + pdiv = ((apll_freq_4x12[index].mps >> 8) & 0x3f); - /* MUX_CORE_SEL = APLL */ + __raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK); + + /* 3. Change PLL PMS values */ + tmp = __raw_readl(EXYNOS4_APLL_CON0); + tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); + tmp |= apll_freq_4x12[index].mps; + __raw_writel(tmp, EXYNOS4_APLL_CON0); + + /* 4. wait_lock_time */ + do { + cpu_relax(); + tmp = __raw_readl(EXYNOS4_APLL_CON0); + } while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT))); + + /* 5. MUX_CORE_SEL = APLL */ clk_set_parent(moutcore, mout_apll); do { @@ -152,15 +167,52 @@ static void exynos4x12_set_apll(unsigned int index) } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)); } +static bool exynos4x12_pms_change(unsigned int old_index, unsigned int new_index) +{ + unsigned int old_pm = apll_freq_4x12[old_index].mps >> 8; + unsigned int new_pm = apll_freq_4x12[new_index].mps >> 8; + + return (old_pm == new_pm) ? 0 : 1; +} + static void exynos4x12_set_frequency(unsigned int old_index, unsigned int new_index) { + unsigned int tmp; + if (old_index > new_index) { - exynos4x12_set_clkdiv(new_index); - exynos4x12_set_apll(new_index); + if (!exynos4x12_pms_change(old_index, new_index)) { + /* 1. Change the system clock divider values */ + exynos4x12_set_clkdiv(new_index); + /* 2. Change just s value in apll m,p,s value */ + tmp = __raw_readl(EXYNOS4_APLL_CON0); + tmp &= ~(0x7 << 0); + tmp |= apll_freq_4x12[new_index].mps & 0x7; + __raw_writel(tmp, EXYNOS4_APLL_CON0); + + } else { + /* Clock Configuration Procedure */ + /* 1. Change the system clock divider values */ + exynos4x12_set_clkdiv(new_index); + /* 2. Change the apll m,p,s value */ + exynos4x12_set_apll(new_index); + } } else if (old_index < new_index) { - exynos4x12_set_apll(new_index); - exynos4x12_set_clkdiv(new_index); + if (!exynos4x12_pms_change(old_index, new_index)) { + /* 1. Change just s value in apll m,p,s value */ + tmp = __raw_readl(EXYNOS4_APLL_CON0); + tmp &= ~(0x7 << 0); + tmp |= apll_freq_4x12[new_index].mps & 0x7; + __raw_writel(tmp, EXYNOS4_APLL_CON0); + /* 2. Change the system clock divider values */ + exynos4x12_set_clkdiv(new_index); + } else { + /* Clock Configuration Procedure */ + /* 1. Change the apll m,p,s value */ + exynos4x12_set_apll(new_index); + /* 2. Change the system clock divider values */ + exynos4x12_set_clkdiv(new_index); + } } } @@ -198,6 +250,7 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info) info->volt_table = exynos4x12_volt_table; info->freq_table = exynos4x12_freq_table; info->set_freq = exynos4x12_set_frequency; + info->need_apll_change = exynos4x12_pms_change; return 0; @@ -211,3 +264,4 @@ err_moutcore: pr_debug("%s: failed initialization\n", __func__); return -EINVAL; } +EXPORT_SYMBOL(exynos4x12_cpufreq_init); |