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Diffstat (limited to 'drivers/staging/cxt1e1')
-rw-r--r--drivers/staging/cxt1e1/comet.c819
-rw-r--r--drivers/staging/cxt1e1/functions.c10
-rw-r--r--drivers/staging/cxt1e1/hwprobe.c6
-rw-r--r--drivers/staging/cxt1e1/linux.c64
-rw-r--r--drivers/staging/cxt1e1/musycc.c42
-rw-r--r--drivers/staging/cxt1e1/pmcc4.h10
-rw-r--r--drivers/staging/cxt1e1/pmcc4_drv.c52
-rw-r--r--drivers/staging/cxt1e1/sbecom_inline_linux.h6
-rw-r--r--drivers/staging/cxt1e1/sbeid.c6
-rw-r--r--drivers/staging/cxt1e1/sbeproc.h4
10 files changed, 520 insertions, 499 deletions
diff --git a/drivers/staging/cxt1e1/comet.c b/drivers/staging/cxt1e1/comet.c
index 52224cd..fabfd77 100644
--- a/drivers/staging/cxt1e1/comet.c
+++ b/drivers/staging/cxt1e1/comet.c
@@ -13,7 +13,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
-#include <asm/io.h>
+#include <linux/io.h>
#include <linux/hdlc.h>
#include "pmcc4_sysdep.h"
#include "sbecom_inline_linux.h"
@@ -35,235 +35,253 @@ extern int cxt1e1_log_level;
#define COMET_NUM_UNITS 5 /* Number of points per entry in table */
/* forward references */
-STATIC void SetPwrLevel (comet_t * comet);
-STATIC void WrtRcvEqualizerTbl (ci_t * ci, comet_t * comet, u_int32_t *table);
-STATIC void WrtXmtWaveformTbl (ci_t * ci, comet_t * comet, u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]);
+STATIC void SetPwrLevel(comet_t *comet);
+STATIC void WrtRcvEqualizerTbl(ci_t *ci, comet_t *comet, u_int32_t *table);
+STATIC void WrtXmtWaveformTbl(ci_t *ci, comet_t *comet, u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]);
void *TWV_table[12] = {
- TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB,
- TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3, TWVShortHaul4,
- TWVShortHaul5,
- TWV_E1_75Ohm, /** PORT POINT - 75 Ohm not supported **/
- TWV_E1_120Ohm
+ TWVLongHaul0DB, TWVLongHaul7_5DB, TWVLongHaul15DB, TWVLongHaul22_5DB,
+ TWVShortHaul0, TWVShortHaul1, TWVShortHaul2, TWVShortHaul3,
+ TWVShortHaul4, TWVShortHaul5,
+ /** PORT POINT - 75 Ohm not supported **/
+ TWV_E1_75Ohm,
+ TWV_E1_120Ohm
};
static int
-lbo_tbl_lkup (int t1, int lbo)
-{
- if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) /* error switches to
- * default */
- {
- if (t1)
- lbo = CFG_LBO_LH0; /* default T1 waveform table */
- else
- lbo = CFG_LBO_E120; /* default E1 waveform table */
- }
- return (lbo - 1); /* make index ZERO relative */
+lbo_tbl_lkup(int t1, int lbo) {
+ /* error switches to default */
+ if ((lbo < CFG_LBO_LH0) || (lbo > CFG_LBO_E120)) {
+ if (t1)
+ /* default T1 waveform table */
+ lbo = CFG_LBO_LH0;
+ else
+ /* default E1 waveform table */
+ lbo = CFG_LBO_E120;
+ }
+ /* make index ZERO relative */
+ return lbo - 1;
}
-
-void
-init_comet (void *ci, comet_t * comet, u_int32_t port_mode, int clockmaster,
- u_int8_t moreParams)
+void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
+ u_int8_t moreParams)
{
- u_int8_t isT1mode;
- u_int8_t tix = CFG_LBO_LH0; /* T1 default */
-
- isT1mode = IS_FRAME_ANY_T1 (port_mode);
- /* T1 or E1 */
- if (isT1mode)
- {
- pci_write_32 ((u_int32_t *) &comet->gbl_cfg, 0xa0); /* Select T1 Mode & PIO
- * output enabled */
- tix = lbo_tbl_lkup (isT1mode, CFG_LBO_LH0); /* default T1 waveform
- * table */
- } else
- {
- pci_write_32 ((u_int32_t *) &comet->gbl_cfg, 0x81); /* Select E1 Mode & PIO
- * output enabled */
- tix = lbo_tbl_lkup (isT1mode, CFG_LBO_E120); /* default E1 waveform
- * table */
- }
-
- if (moreParams & CFG_LBO_MASK)
- tix = lbo_tbl_lkup (isT1mode, moreParams & CFG_LBO_MASK); /* dial-in requested
- * waveform table */
-
- /* Tx line Intfc cfg ** Set for analog & no special patterns */
- pci_write_32 ((u_int32_t *) &comet->tx_line_cfg, 0x00); /* Transmit Line
- * Interface Config. */
-
- /* master test ** Ignore Test settings for now */
- pci_write_32 ((u_int32_t *) &comet->mtest, 0x00); /* making sure it's
- * Default value */
-
- /* Turn on Center (CENT) and everything else off */
- pci_write_32 ((u_int32_t *) &comet->rjat_cfg, 0x10); /* RJAT cfg */
- /* Set Jitter Attenuation to recommend T1 values */
- if (isT1mode)
- {
- pci_write_32 ((u_int32_t *) &comet->rjat_n1clk, 0x2F); /* RJAT Divider N1
- * Control */
- pci_write_32 ((u_int32_t *) &comet->rjat_n2clk, 0x2F); /* RJAT Divider N2
- * Control */
- } else
- {
- pci_write_32 ((u_int32_t *) &comet->rjat_n1clk, 0xFF); /* RJAT Divider N1
- * Control */
- pci_write_32 ((u_int32_t *) &comet->rjat_n2clk, 0xFF); /* RJAT Divider N2
- * Control */
- }
-
- /* Turn on Center (CENT) and everything else off */
- pci_write_32 ((u_int32_t *) &comet->tjat_cfg, 0x10); /* TJAT Config. */
-
- /* Do not bypass jitter attenuation and bypass elastic store */
- pci_write_32 ((u_int32_t *) &comet->rx_opt, 0x00); /* rx opts */
-
- /* TJAT ctrl & TJAT divider ctrl */
- /* Set Jitter Attenuation to recommended T1 values */
- if (isT1mode)
- {
- pci_write_32 ((u_int32_t *) &comet->tjat_n1clk, 0x2F); /* TJAT Divider N1
- * Control */
- pci_write_32 ((u_int32_t *) &comet->tjat_n2clk, 0x2F); /* TJAT Divider N2
- * Control */
- } else
- {
- pci_write_32 ((u_int32_t *) &comet->tjat_n1clk, 0xFF); /* TJAT Divider N1
- * Control */
- pci_write_32 ((u_int32_t *) &comet->tjat_n2clk, 0xFF); /* TJAT Divider N2
- * Control */
- }
-
- /* 1c: rx ELST cfg 20: tx ELST cfg 28&38: rx&tx data link ctrl */
- if (isT1mode)
- { /* Select 193-bit frame format */
- pci_write_32 ((u_int32_t *) &comet->rx_elst_cfg, 0x00);
- pci_write_32 ((u_int32_t *) &comet->tx_elst_cfg, 0x00);
- } else
- { /* Select 256-bit frame format */
- pci_write_32 ((u_int32_t *) &comet->rx_elst_cfg, 0x03);
- pci_write_32 ((u_int32_t *) &comet->tx_elst_cfg, 0x03);
- pci_write_32 ((u_int32_t *) &comet->rxce1_ctl, 0x00); /* disable T1 data link
- * receive */
- pci_write_32 ((u_int32_t *) &comet->txci1_ctl, 0x00); /* disable T1 data link
- * transmit */
- }
+ u_int8_t isT1mode;
+ /* T1 default */
+ u_int8_t tix = CFG_LBO_LH0;
+ isT1mode = IS_FRAME_ANY_T1(port_mode);
+ /* T1 or E1 */
+ if (isT1mode) {
+ /* Select T1 Mode & PIO output enabled */
+ pci_write_32((u_int32_t *) &comet->gbl_cfg, 0xa0);
+ /* default T1 waveform table */
+ tix = lbo_tbl_lkup(isT1mode, CFG_LBO_LH0);
+ } else {
+ /* Select E1 Mode & PIO output enabled */
+ pci_write_32((u_int32_t *) &comet->gbl_cfg, 0x81);
+ /* default E1 waveform table */
+ tix = lbo_tbl_lkup(isT1mode, CFG_LBO_E120);
+ }
+
+ if (moreParams & CFG_LBO_MASK)
+ /* dial-in requested waveform table */
+ tix = lbo_tbl_lkup(isT1mode, moreParams & CFG_LBO_MASK);
+ /* Tx line Intfc cfg Set for analog & no special patterns */
+ /* Transmit Line Interface Config. */
+ pci_write_32((u_int32_t *) &comet->tx_line_cfg, 0x00);
+ /* master test Ignore Test settings for now */
+ /* making sure it's Default value */
+ pci_write_32((u_int32_t *) &comet->mtest, 0x00);
+ /* Turn on Center (CENT) and everything else off */
+ /* RJAT cfg */
+ pci_write_32((u_int32_t *) &comet->rjat_cfg, 0x10);
+ /* Set Jitter Attenuation to recommend T1 values */
+ if (isT1mode) {
+ /* RJAT Divider N1 Control */
+ pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0x2F);
+ /* RJAT Divider N2 Control */
+ pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0x2F);
+ } else {
+ /* RJAT Divider N1 Control */
+ pci_write_32((u_int32_t *) &comet->rjat_n1clk, 0xFF);
+ /* RJAT Divider N2 Control */
+ pci_write_32((u_int32_t *) &comet->rjat_n2clk, 0xFF);
+ }
+
+ /* Turn on Center (CENT) and everything else off */
+ /* TJAT Config. */
+ pci_write_32((u_int32_t *) &comet->tjat_cfg, 0x10);
+
+ /* Do not bypass jitter attenuation and bypass elastic store */
+ /* rx opts */
+ pci_write_32((u_int32_t *) &comet->rx_opt, 0x00);
+
+ /* TJAT ctrl & TJAT divider ctrl */
+ /* Set Jitter Attenuation to recommended T1 values */
+ if (isT1mode) {
+ /* TJAT Divider N1 Control */
+ pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0x2F);
+ /* TJAT Divider N2 Control */
+ pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0x2F);
+ } else {
+ /* TJAT Divider N1 Control */
+ pci_write_32((u_int32_t *) &comet->tjat_n1clk, 0xFF);
+ /* TJAT Divider N2 Control */
+ pci_write_32((u_int32_t *) &comet->tjat_n2clk, 0xFF);
+ }
+
+ /* 1c: rx ELST cfg 20: tx ELST cfg 28&38: rx&tx data link ctrl */
+
+ /* Select 193-bit frame format */
+ if (isT1mode) {
+ pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x00);
+ pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x00);
+ } else {
+ /* Select 256-bit frame format */
+ pci_write_32((u_int32_t *) &comet->rx_elst_cfg, 0x03);
+ pci_write_32((u_int32_t *) &comet->tx_elst_cfg, 0x03);
+ /* disable T1 data link receive */
+ pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x00);
+ /* disable T1 data link transmit */
+ pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x00);
+ }
/* the following is a default value */
/* Enable 8 out of 10 validation */
- pci_write_32 ((u_int32_t *) &comet->t1_rboc_ena, 0x00); /* t1RBOC
- * enable(BOC:BitOriented
- * Code) */
- if (isT1mode)
- {
-
- /* IBCD cfg: aka Inband Code Detection ** loopback code length set to */
- pci_write_32 ((u_int32_t *) &comet->ibcd_cfg, 0x04); /* 6 bit down, 5 bit up
- * (assert) */
- pci_write_32 ((u_int32_t *) &comet->ibcd_act, 0x08); /* line loopback
- * activate pattern */
- pci_write_32 ((u_int32_t *) &comet->ibcd_deact, 0x24); /* deactivate code
- * pattern (i.e.001) */
- }
+ /* t1RBOC enable(BOC:BitOriented Code) */
+ pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
+ if (isT1mode)
+ {
+
+ /* IBCD cfg: aka Inband Code Detection ** loopback code length set to */
+ /* 6 bit down, 5 bit up (assert) */
+ pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04);
+ /* line loopback activate pattern */
+ pci_write_32((u_int32_t *) &comet->ibcd_act, 0x08);
+ /* deactivate code pattern (i.e.001) */
+ pci_write_32((u_int32_t *) &comet->ibcd_deact, 0x24);
+ }
/* 10: CDRC cfg 28&38: rx&tx data link 1 ctrl 48: t1 frmr cfg */
/* 50: SIGX cfg, COSS (change of signaling state) 54: XBAS cfg */
/* 60: t1 ALMI cfg */
/* Configure Line Coding */
- switch (port_mode)
- {
- case CFG_FRAME_SF: /* 1 - T1 B8ZS */
- pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->t1_frmr_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->t1_xbas_cfg, 0x20); /* 5:B8ZS */
- pci_write_32 ((u_int32_t *) &comet->t1_almi_cfg, 0);
- break;
- case CFG_FRAME_ESF: /* 2 - T1 B8ZS */
- pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->rxce1_ctl, 0x20); /* Bit 5: T1 DataLink
- * Enable */
- pci_write_32 ((u_int32_t *) &comet->txci1_ctl, 0x20); /* 5: T1 DataLink Enable */
- pci_write_32 ((u_int32_t *) &comet->t1_frmr_cfg, 0x30); /* 4:ESF 5:ESFFA */
- pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0x04); /* 2:ESF */
- pci_write_32 ((u_int32_t *) &comet->t1_xbas_cfg, 0x30); /* 4:ESF 5:B8ZS */
- pci_write_32 ((u_int32_t *) &comet->t1_almi_cfg, 0x10); /* 4:ESF */
- break;
- case CFG_FRAME_E1PLAIN: /* 3 - HDB3 */
- pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
- break;
- case CFG_FRAME_E1CAS: /* 4 - HDB3 */
- pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0x60);
- pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0);
- break;
- case CFG_FRAME_E1CRC: /* 5 - HDB3 */
- pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0x10);
- pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
- break;
- case CFG_FRAME_E1CRC_CAS: /* 6 - HDB3 */
- pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0x70);
- pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
- break;
- case CFG_FRAME_SF_AMI: /* 7 - T1 AMI */
- pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line
- * Decoding */
- pci_write_32 ((u_int32_t *) &comet->t1_frmr_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->t1_xbas_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->t1_almi_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
- break;
- case CFG_FRAME_ESF_AMI: /* 8 - T1 AMI */
- pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line
- * Decoding */
- pci_write_32 ((u_int32_t *) &comet->rxce1_ctl, 0x20); /* 5: T1 DataLink Enable */
- pci_write_32 ((u_int32_t *) &comet->txci1_ctl, 0x20); /* 5: T1 DataLink Enable */
- pci_write_32 ((u_int32_t *) &comet->t1_frmr_cfg, 0x30); /* Bit 4:ESF 5:ESFFA */
- pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0x04); /* 2:ESF */
- pci_write_32 ((u_int32_t *) &comet->t1_xbas_cfg, 0x10); /* 4:ESF */
- pci_write_32 ((u_int32_t *) &comet->t1_almi_cfg, 0x10); /* 4:ESF */
- break;
- case CFG_FRAME_E1PLAIN_AMI: /* 9 - AMI */
- pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line
- * Decoding */
- pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0x80);
- pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
- break;
- case CFG_FRAME_E1CAS_AMI: /* 10 - AMI */
- pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line
- * Decoding */
- pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0xe0);
- pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0);
- break;
- case CFG_FRAME_E1CRC_AMI: /* 11 - AMI */
- pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line
- * Decoding */
- pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0x90);
- pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
- break;
- case CFG_FRAME_E1CRC_CAS_AMI: /* 12 - AMI */
- pci_write_32 ((u_int32_t *) &comet->cdrc_cfg, 0x80); /* Enable AMI Line
- * Decoding */
- pci_write_32 ((u_int32_t *) &comet->sigx_cfg, 0);
- pci_write_32 ((u_int32_t *) &comet->e1_tran_cfg, 0xf0);
- pci_write_32 ((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
- break;
- } /* end switch */
+ switch (port_mode)
+ {
+ /* 1 - T1 B8ZS */
+ case CFG_FRAME_SF:
+ pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
+ /* 5:B8ZS */
+ pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x20);
+ pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
+ break;
+ /* 2 - T1 B8ZS */
+ case CFG_FRAME_ESF:
+ pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
+ /* Bit 5: T1 DataLink Enable */
+ pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
+ /* 5: T1 DataLink Enable */
+ pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
+ /* 4:ESF 5:ESFFA */
+ pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
+ /* 2:ESF */
+ pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
+ /* 4:ESF 5:B8ZS */
+ pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x30);
+ /* 4:ESF */
+ pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
+ break;
+ /* 3 - HDB3 */
+ case CFG_FRAME_E1PLAIN:
+ pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
+ break;
+ /* 4 - HDB3 */
+ case CFG_FRAME_E1CAS:
+ pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x60);
+ pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
+ break;
+ /* 5 - HDB3 */
+ case CFG_FRAME_E1CRC:
+ pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x10);
+ pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
+ break;
+ /* 6 - HDB3 */
+ case CFG_FRAME_E1CRC_CAS:
+ pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x70);
+ pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
+ break;
+ /* 7 - T1 AMI */
+ case CFG_FRAME_SF_AMI:
+ /* Enable AMI Line Decoding */
+ pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
+ pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
+ break;
+ /* 8 - T1 AMI */
+ case CFG_FRAME_ESF_AMI:
+ /* Enable AMI Line Decoding */
+ pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
+ /* 5: T1 DataLink Enable */
+ pci_write_32((u_int32_t *) &comet->rxce1_ctl, 0x20);
+ /* 5: T1 DataLink Enable */
+ pci_write_32((u_int32_t *) &comet->txci1_ctl, 0x20);
+ /* Bit 4:ESF 5:ESFFA */
+ pci_write_32((u_int32_t *) &comet->t1_frmr_cfg, 0x30);
+ /* 2:ESF */
+ pci_write_32((u_int32_t *) &comet->sigx_cfg, 0x04);
+ /* 4:ESF */
+ pci_write_32((u_int32_t *) &comet->t1_xbas_cfg, 0x10);
+ /* 4:ESF */
+ pci_write_32((u_int32_t *) &comet->t1_almi_cfg, 0x10);
+ break;
+ /* 9 - AMI */
+ case CFG_FRAME_E1PLAIN_AMI:
+ /* Enable AMI Line Decoding */
+ pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
+ pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x80);
+ pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x40);
+ break;
+ /* 10 - AMI */
+ case CFG_FRAME_E1CAS_AMI:
+ /* Enable AMI Line Decoding */
+ pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
+ pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xe0);
+ pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0);
+ break;
+ /* 11 - AMI */
+ case CFG_FRAME_E1CRC_AMI:
+ /* Enable AMI Line Decoding */
+ pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
+ pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0x90);
+ pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0xc2);
+ break;
+ /* 12 - AMI */
+ case CFG_FRAME_E1CRC_CAS_AMI:
+ /* Enable AMI Line Decoding */
+ pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0x80);
+ pci_write_32((u_int32_t *) &comet->sigx_cfg, 0);
+ pci_write_32((u_int32_t *) &comet->e1_tran_cfg, 0xf0);
+ pci_write_32((u_int32_t *) &comet->e1_frmr_aopts, 0x82);
+ break;
+ } /* end switch */
/***
* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0)
@@ -277,101 +295,109 @@ init_comet (void *ci, comet_t * comet, u_int32_t port_mode, int clockmaster,
/* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
/* note "rate bits can only be set once after reset" */
- if (clockmaster)
- { /* CMODE == clockMode, 0=clock master (so
- * all 3 others should be slave) */
- if (isT1mode) /* rate = 1.544 Mb/s */
- pci_write_32 ((u_int32_t *) &comet->brif_cfg, 0x00); /* Comet 0 Master
- * Mode(CMODE=0) */
- else /* rate = 2.048 Mb/s */
- pci_write_32 ((u_int32_t *) &comet->brif_cfg, 0x01); /* Comet 0 Master
- * Mode(CMODE=0) */
-
- /* 31: BRIF frame pulse cfg 06: tx timing options */
- pci_write_32 ((u_int32_t *) &comet->brif_fpcfg, 0x00); /* Master Mode
- * i.e.FPMODE=0 (@0x20) */
- if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL)
- {
- if (cxt1e1_log_level >= LOG_SBEBUG12)
- pr_info(">> %s: clockmaster internal clock\n", __func__);
- pci_write_32 ((u_int32_t *) &comet->tx_time, 0x0d); /* internal oscillator */
- } else /* external clock source */
- {
- if (cxt1e1_log_level >= LOG_SBEBUG12)
- pr_info(">> %s: clockmaster external clock\n", __func__);
- pci_write_32 ((u_int32_t *) &comet->tx_time, 0x09); /* loop timing
- * (external) */
- }
-
- } else /* slave */
- {
- if (isT1mode)
- pci_write_32 ((u_int32_t *) &comet->brif_cfg, 0x20); /* Slave Mode(CMODE=1,
- * see above) */
- else
- pci_write_32 ((u_int32_t *) &comet->brif_cfg, 0x21); /* Slave Mode (CMODE=1) */
- pci_write_32 ((u_int32_t *) &comet->brif_fpcfg, 0x20); /* Slave Mode i.e.
- * FPMODE=1 (@0x20) */
- if (cxt1e1_log_level >= LOG_SBEBUG12)
- pr_info(">> %s: clockslave internal clock\n", __func__);
- pci_write_32 ((u_int32_t *) &comet->tx_time, 0x0d); /* oscillator timing */
- }
-
- /* 32: BRIF parity F-bit cfg */
- /* Totem-pole operation */
- pci_write_32 ((u_int32_t *) &comet->brif_pfcfg, 0x01); /* Receive Backplane
- * Parity/F-bit */
+ if (clockmaster)
+ {
+ /* CMODE == clockMode, 0=clock master (so all 3 others should be slave) */
+ /* rate = 1.544 Mb/s */
+ if (isT1mode)
+ /* Comet 0 Master Mode(CMODE=0) */
+ pci_write_32((u_int32_t *) &comet->brif_cfg, 0x00);
+ /* rate = 2.048 Mb/s */
+ else
+ /* Comet 0 Master Mode(CMODE=0) */
+ pci_write_32((u_int32_t *) &comet->brif_cfg, 0x01);
+
+ /* 31: BRIF frame pulse cfg 06: tx timing options */
+
+ /* Master Mode i.e.FPMODE=0 (@0x20) */
+ pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
+ if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL)
+ {
+ if (cxt1e1_log_level >= LOG_SBEBUG12)
+ pr_info(">> %s: clockmaster internal clock\n", __func__);
+ /* internal oscillator */
+ pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
+ } else {
+ /* external clock source */
+ if (cxt1e1_log_level >= LOG_SBEBUG12)
+ pr_info(">> %s: clockmaster external clock\n", __func__);
+ /* loop timing(external) */
+ pci_write_32((u_int32_t *) &comet->tx_time, 0x09);
+ }
+
+ } else {
+ /* slave */
+ if (isT1mode)
+ /* Slave Mode(CMODE=1, see above) */
+ pci_write_32((u_int32_t *) &comet->brif_cfg, 0x20);
+ else
+ /* Slave Mode(CMODE=1)*/
+ pci_write_32((u_int32_t *) &comet->brif_cfg, 0x21);
+ /* Slave Mode i.e. FPMODE=1 (@0x20) */
+ pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x20);
+ if (cxt1e1_log_level >= LOG_SBEBUG12)
+ pr_info(">> %s: clockslave internal clock\n", __func__);
+ /* oscillator timing */
+ pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
+ }
+
+ /* 32: BRIF parity F-bit cfg */
+ /* Totem-pole operation */
+ /* Receive Backplane Parity/F-bit */
+ pci_write_32((u_int32_t *) &comet->brif_pfcfg, 0x01);
/* dc: RLPS equalizer V ref */
/* Configuration */
- if (isT1mode)
- pci_write_32 ((u_int32_t *) &comet->rlps_eqvr, 0x2c); /* RLPS Equalizer
- * Voltage */
- else
- pci_write_32 ((u_int32_t *) &comet->rlps_eqvr, 0x34); /* RLPS Equalizer
- * Voltage */
+ if (isT1mode)
+ /* RLPS Equalizer Voltage */
+ pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x2c);
+ else
+ /* RLPS Equalizer Voltage */
+ pci_write_32((u_int32_t *) &comet->rlps_eqvr, 0x34);
/* Reserved bit set and SQUELCH enabled */
/* f8: RLPS cfg & status f9: RLPS ALOS detect/clear threshold */
- pci_write_32 ((u_int32_t *) &comet->rlps_cfgsts, 0x11); /* RLPS Configuration
- * Status */
- if (isT1mode)
- pci_write_32 ((u_int32_t *) &comet->rlps_alos_thresh, 0x55); /* ? */
- else
- pci_write_32 ((u_int32_t *) &comet->rlps_alos_thresh, 0x22); /* ? */
+ /* RLPS Configuration Status */
+ pci_write_32((u_int32_t *) &comet->rlps_cfgsts, 0x11);
+ if (isT1mode)
+ /* ? */
+ pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x55);
+ else
+ /* ? */
+ pci_write_32((u_int32_t *) &comet->rlps_alos_thresh, 0x22);
/* Set Full Frame mode (NXDSO[1] = 0, NXDSO[0] = 0) */
/* CMODE=0: Clock slave mode with BTCLK as an input, DE=1: Use rising */
/* edge of BTCLK for data, FE=1: Use rising edge of BTCLK for frame, */
/* CMS=0: Use backplane freq, RATE[1:0]=0,0: T1 */
-/*** Transmit side is always an Input, Slave Clock*/
- /* 40: BTIF cfg 41: BTIF frame pulse cfg */
- if (isT1mode)
- pci_write_32 ((u_int32_t *) &comet->btif_cfg, 0x38); /* BTIF Configuration
- * Reg. */
- else
- pci_write_32 ((u_int32_t *) &comet->btif_cfg, 0x39); /* BTIF Configuration
- * Reg. */
-
- pci_write_32 ((u_int32_t *) &comet->btif_fpcfg, 0x01); /* BTIF Frame Pulse
- * Config. */
+ /*** Transmit side is always an Input, Slave Clock*/
+ /* 40: BTIF cfg 41: loop timing(external) */
+ /*BTIF frame pulse cfg */
+ if (isT1mode)
+ /* BTIF Configuration Reg. */
+ pci_write_32((u_int32_t *) &comet->btif_cfg, 0x38);
+ else
+ /* BTIF Configuration Reg. */
+ pci_write_32((u_int32_t *) &comet->btif_cfg, 0x39);
+ /* BTIF Frame Pulse Config. */
+ pci_write_32((u_int32_t *) &comet->btif_fpcfg, 0x01);
/* 0a: master diag 06: tx timing options */
/* if set Comet to loop back */
/* Comets set to normal */
- pci_write_32 ((u_int32_t *) &comet->mdiag, 0x00);
+ pci_write_32((u_int32_t *) &comet->mdiag, 0x00);
/* BTCLK driven by TCLKI internally (crystal driven) and Xmt Elasted */
/* Store is enabled. */
- WrtXmtWaveformTbl (ci, comet, TWV_table[tix]);
- if (isT1mode)
- WrtRcvEqualizerTbl ((ci_t *) ci, comet, &T1_Equalizer[0]);
- else
- WrtRcvEqualizerTbl ((ci_t *) ci, comet, &E1_Equalizer[0]);
- SetPwrLevel (comet);
+ WrtXmtWaveformTbl(ci, comet, TWV_table[tix]);
+ if (isT1mode)
+ WrtRcvEqualizerTbl((ci_t *) ci, comet, &T1_Equalizer[0]);
+ else
+ WrtRcvEqualizerTbl((ci_t *) ci, comet, &E1_Equalizer[0]);
+ SetPwrLevel(comet);
}
/*
@@ -382,15 +408,15 @@ init_comet (void *ci, comet_t * comet, u_int32_t port_mode, int clockmaster,
** Returns: Nothing
*/
STATIC void
-WrtXmtWaveform (ci_t * ci, comet_t * comet, u_int32_t sample, u_int32_t unit, u_int8_t data)
+WrtXmtWaveform(ci_t *ci, comet_t *comet, u_int32_t sample, u_int32_t unit, u_int8_t data)
{
- u_int8_t WaveformAddr;
+ u_int8_t WaveformAddr;
- WaveformAddr = (sample << 3) + (unit & 7);
- pci_write_32 ((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr);
- pci_flush_write (ci); /* for write order preservation when
- * Optimizing driver */
- pci_write_32 ((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data);
+ WaveformAddr = (sample << 3) + (unit & 7);
+ pci_write_32((u_int32_t *) &comet->xlpg_pwave_addr, WaveformAddr);
+ /* for write order preservation when Optimizing driver */
+ pci_flush_write(ci);
+ pci_write_32((u_int32_t *) &comet->xlpg_pwave_data, 0x7F & data);
}
/*
@@ -400,19 +426,19 @@ WrtXmtWaveform (ci_t * ci, comet_t * comet, u_int32_t sample, u_int32_t unit, u_
** Returns: Nothing
*/
STATIC void
-WrtXmtWaveformTbl (ci_t * ci, comet_t * comet,
- u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS])
+WrtXmtWaveformTbl(ci_t *ci, comet_t *comet,
+ u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS])
{
- u_int32_t sample, unit;
+ u_int32_t sample, unit;
- for (sample = 0; sample < COMET_NUM_SAMPLES; sample++)
- {
- for (unit = 0; unit < COMET_NUM_UNITS; unit++)
- WrtXmtWaveform (ci, comet, sample, unit, table[sample][unit]);
- }
+ for (sample = 0; sample < COMET_NUM_SAMPLES; sample++)
+ {
+ for (unit = 0; unit < COMET_NUM_UNITS; unit++)
+ WrtXmtWaveform(ci, comet, sample, unit, table[sample][unit]);
+ }
/* Enable transmitter and set output amplitude */
- pci_write_32 ((u_int32_t *) &comet->xlpg_cfg, table[COMET_NUM_SAMPLES][0]);
+ pci_write_32((u_int32_t *) &comet->xlpg_cfg, table[COMET_NUM_SAMPLES][0]);
}
@@ -427,60 +453,60 @@ WrtXmtWaveformTbl (ci_t * ci, comet_t * comet,
*/
STATIC void
-WrtRcvEqualizerTbl (ci_t * ci, comet_t * comet, u_int32_t *table)
+WrtRcvEqualizerTbl(ci_t *ci, comet_t *comet, u_int32_t *table)
{
- u_int32_t ramaddr;
- volatile u_int32_t value;
-
- for (ramaddr = 0; ramaddr < 256; ramaddr++)
- {
- /*** the following lines are per Errata 7, 2.5 ***/
- {
- pci_write_32 ((u_int32_t *) &comet->rlps_eq_rwsel, 0x80); /* Set up for a read
- * operation */
- pci_flush_write (ci); /* for write order preservation when
- * Optimizing driver */
- pci_write_32 ((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr); /* write the addr,
- * initiate a read */
- pci_flush_write (ci); /* for write order preservation when
- * Optimizing driver */
- /*
- * wait 3 line rate clock cycles to ensure address bits are
- * captured by T1/E1 clock
- */
- OS_uwait (4, "wret"); /* 683ns * 3 = 1366 ns, approx 2us (but
- * use 4us) */
- }
-
- value = *table++;
- pci_write_32 ((u_int32_t *) &comet->rlps_idata3, (u_int8_t) (value >> 24));
- pci_write_32 ((u_int32_t *) &comet->rlps_idata2, (u_int8_t) (value >> 16));
- pci_write_32 ((u_int32_t *) &comet->rlps_idata1, (u_int8_t) (value >> 8));
- pci_write_32 ((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
- pci_flush_write (ci); /* for write order preservation when
- * Optimizing driver */
-
- /* Storing RAM address, causes RAM to be updated */
-
- pci_write_32 ((u_int32_t *) &comet->rlps_eq_rwsel, 0); /* Set up for a write
- * operation */
- pci_flush_write (ci); /* for write order preservation when
- * Optimizing driver */
- pci_write_32 ((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr); /* write the addr,
- * initiate a read */
- pci_flush_write (ci); /* for write order preservation when
- * Optimizing driver */
- /*
- * wait 3 line rate clock cycles to ensure address bits are captured
- * by T1/E1 clock
- */
- OS_uwait (4, "wret"); /* 683ns * 3 = 1366 ns, approx 2us (but
- * use 4us) */
- }
-
- pci_write_32 ((u_int32_t *) &comet->rlps_eq_cfg, 0xCB); /* Enable Equalizer &
- * set it to use 256
- * periods */
+ u_int32_t ramaddr;
+ volatile u_int32_t value;
+
+ for (ramaddr = 0; ramaddr < 256; ramaddr++) {
+ /*** the following lines are per Errata 7, 2.5 ***/
+ {
+ /* Set up for a read operation */
+ pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0x80);
+ /* for write order preservation when Optimizing driver */
+ pci_flush_write(ci);
+ /* write the addr, initiate a read */
+ pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
+ /* for write order preservation when Optimizing driver */
+ pci_flush_write(ci);
+ /*
+ * wait 3 line rate clock cycles to ensure address bits are
+ * captured by T1/E1 clock
+ */
+
+ /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
+ OS_uwait(4, "wret");
+ }
+
+ value = *table++;
+ pci_write_32((u_int32_t *) &comet->rlps_idata3, (u_int8_t) (value >> 24));
+ pci_write_32((u_int32_t *) &comet->rlps_idata2, (u_int8_t) (value >> 16));
+ pci_write_32((u_int32_t *) &comet->rlps_idata1, (u_int8_t) (value >> 8));
+ pci_write_32((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
+ /* for write order preservation when Optimizing driver */
+ pci_flush_write(ci);
+
+ /* Storing RAM address, causes RAM to be updated */
+
+ /* Set up for a write operation */
+ pci_write_32((u_int32_t *) &comet->rlps_eq_rwsel, 0);
+ /* for write order preservation when optimizing driver */
+ pci_flush_write(ci);
+ /* write the addr, initiate a read */
+ pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
+ /* for write order preservation when optimizing driver */
+ pci_flush_write(ci);
+
+ /*
+ * wait 3 line rate clock cycles to ensure address bits are captured
+ * by T1/E1 clock
+ */
+ /* 683ns * 3 = 1366 ns, approx 2us (but use 4us) */
+ OS_uwait(4, "wret");
+ }
+
+ /* Enable Equalizer & set it to use 256 periods */
+ pci_write_32((u_int32_t *) &comet->rlps_eq_cfg, 0xCB);
}
@@ -491,9 +517,9 @@ WrtRcvEqualizerTbl (ci_t * ci, comet_t * comet, u_int32_t *table)
*/
STATIC void
-SetPwrLevel (comet_t * comet)
+SetPwrLevel(comet_t *comet)
{
- volatile u_int32_t temp;
+ volatile u_int32_t temp;
/*
** Algorithm to Balance the Power Distribution of Ttip Tring
@@ -507,22 +533,20 @@ SetPwrLevel (comet_t * comet)
** Repeat these steps for register F5
** Write 0x01 to register F6
*/
- pci_write_32 ((u_int32_t *) &comet->xlpg_fdata_sel, 0x00); /* XLPG Fuse Data Select */
-
- pci_write_32 ((u_int32_t *) &comet->xlpg_atest_pctl, 0x01); /* XLPG Analog Test
- * Positive control */
- pci_write_32 ((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
-
- temp = pci_read_32 ((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe;
- pci_write_32 ((u_int32_t *) &comet->xlpg_atest_pctl, temp);
-
- pci_write_32 ((u_int32_t *) &comet->xlpg_atest_nctl, 0x01); /* XLPG Analog Test
- * Negative control */
- pci_write_32 ((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
-
- temp = pci_read_32 ((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe;
- pci_write_32 ((u_int32_t *) &comet->xlpg_atest_nctl, temp);
- pci_write_32 ((u_int32_t *) &comet->xlpg_fdata_sel, 0x01); /* XLPG */
+ /* XLPG Fuse Data Select */
+ pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x00);
+ /* XLPG Analog Test Positive control */
+ pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
+ pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, 0x01);
+ temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_pctl) & 0xfe;
+ pci_write_32((u_int32_t *) &comet->xlpg_atest_pctl, temp);
+ pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
+ pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, 0x01);
+ /* XLPG Analog Test Negative control */
+ temp = pci_read_32((u_int32_t *) &comet->xlpg_atest_nctl) & 0xfe;
+ pci_write_32((u_int32_t *) &comet->xlpg_atest_nctl, temp);
+ /* XLPG */
+ pci_write_32((u_int32_t *) &comet->xlpg_fdata_sel, 0x01);
}
@@ -535,33 +559,30 @@ SetPwrLevel (comet_t * comet)
*/
#if 0
STATIC void
-SetCometOps (comet_t * comet)
+SetCometOps(comet_t *comet)
{
- volatile u_int8_t rd_value;
-
- if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2))
- {
- rd_value = (u_int8_t) pci_read_32 ((u_int32_t *) &comet->brif_cfg); /* read the BRIF
- * Configuration */
- rd_value &= ~0x20;
- pci_write_32 ((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
-
- rd_value = (u_int8_t) pci_read_32 ((u_int32_t *) &comet->brif_fpcfg); /* read the BRIF Frame
- * Pulse Configuration */
- rd_value &= ~0x20;
- pci_write_32 ((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value);
- } else
- {
- rd_value = (u_int8_t) pci_read_32 ((u_int32_t *) &comet->brif_cfg); /* read the BRIF
- * Configuration */
- rd_value |= 0x20;
- pci_write_32 ((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
-
- rd_value = (u_int8_t) pci_read_32 ((u_int32_t *) &comet->brif_fpcfg); /* read the BRIF Frame
- * Pulse Configuration */
- rd_value |= 0x20;
- pci_write_32 ((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value);
- }
+ volatile u_int8_t rd_value;
+
+ if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2))
+ {
+ /* read the BRIF Configuration */
+ rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
+ rd_value &= ~0x20;
+ pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
+ /* read the BRIF Frame Pulse Configuration */
+ rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
+ rd_value &= ~0x20;
+ pci_write_32((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value);
+ } else {
+ /* read the BRIF Configuration */
+ rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
+ rd_value |= 0x20;
+ pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
+ /* read the BRIF Frame Pulse Configuration */
+ rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
+ rd_value |= 0x20;
+ pci_write_32(u_int32_t *) & comet->brif_fpcfg, (u_int8_t) rd_value);
+ }
}
#endif
diff --git a/drivers/staging/cxt1e1/functions.c b/drivers/staging/cxt1e1/functions.c
index d9a9aa3..6167dc5 100644
--- a/drivers/staging/cxt1e1/functions.c
+++ b/drivers/staging/cxt1e1/functions.c
@@ -14,7 +14,7 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/slab.h>
-#include <asm/io.h>
+#include <linux/io.h>
#include <asm/byteorder.h>
#include <linux/netdevice.h>
#include <linux/delay.h>
@@ -97,7 +97,7 @@ pci_write_32 (u_int32_t *p, u_int32_t v)
void
-pci_flush_write (ci_t * ci)
+pci_flush_write (ci_t *ci)
{
volatile u_int32_t v;
@@ -202,7 +202,7 @@ sd_line_is_ok (void *user)
{
struct net_device *ndev = (struct net_device *) user;
- return (netif_carrier_ok (ndev));
+ return netif_carrier_ok (ndev);
}
void
@@ -246,7 +246,7 @@ sd_queue_stopped (void *user)
{
struct net_device *ndev = (struct net_device *) user;
- return (netif_queue_stopped (ndev));
+ return netif_queue_stopped (ndev);
}
void sd_recv_consume(void *token, size_t len, void *user)
@@ -279,7 +279,7 @@ VMETRO_TRACE (void *x)
void
-VMETRO_TRIGGER (ci_t * ci, int x)
+VMETRO_TRIGGER (ci_t *ci, int x)
{
comet_t *comet;
volatile u_int32_t data;
diff --git a/drivers/staging/cxt1e1/hwprobe.c b/drivers/staging/cxt1e1/hwprobe.c
index de8ac0b..110c252 100644
--- a/drivers/staging/cxt1e1/hwprobe.c
+++ b/drivers/staging/cxt1e1/hwprobe.c
@@ -50,7 +50,7 @@ struct s_hdw_info hdw_info[MAX_BOARDS];
void __init
-show_two (hdw_info_t * hi, int brdno)
+show_two (hdw_info_t *hi, int brdno)
{
ci_t *ci;
struct pci_dev *pdev;
@@ -102,7 +102,7 @@ show_two (hdw_info_t * hi, int brdno)
void __init
-hdw_sn_get (hdw_info_t * hi, int brdno)
+hdw_sn_get (hdw_info_t *hi, int brdno)
{
/* obtain hardware EEPROM information */
long addr;
@@ -222,7 +222,7 @@ cleanup_devs (void)
STATIC int __init
-c4_hdw_init (struct pci_dev * pdev, int found)
+c4_hdw_init (struct pci_dev *pdev, int found)
{
hdw_info_t *hi;
int i;
diff --git a/drivers/staging/cxt1e1/linux.c b/drivers/staging/cxt1e1/linux.c
index a829b62..e5889ef 100644
--- a/drivers/staging/cxt1e1/linux.c
+++ b/drivers/staging/cxt1e1/linux.c
@@ -144,7 +144,7 @@ getuserbychan (int channum)
char *
-get_hdlc_name (hdlc_device * hdlc)
+get_hdlc_name (hdlc_device *hdlc)
{
struct c4_priv *priv = hdlc->priv;
struct net_device *dev = getuserbychan (priv->channum);
@@ -185,7 +185,7 @@ mkret (int bsd)
* within a port's group.
*/
void
-c4_wk_chan_restart (mch_t * ch)
+c4_wk_chan_restart (mch_t *ch)
{
mpi_t *pi = ch->up;
@@ -203,7 +203,7 @@ c4_wk_chan_restart (mch_t * ch)
}
status_t
-c4_wk_chan_init (mpi_t * pi, mch_t * ch)
+c4_wk_chan_init (mpi_t *pi, mch_t *ch)
{
/*
* this will be used to restart a stopped channel
@@ -218,7 +218,7 @@ c4_wk_chan_init (mpi_t * pi, mch_t * ch)
}
status_t
-c4_wq_port_init (mpi_t * pi)
+c4_wq_port_init (mpi_t *pi)
{
char name[16], *np; /* NOTE: name of the queue limited by system
@@ -241,7 +241,7 @@ c4_wq_port_init (mpi_t * pi)
}
void
-c4_wq_port_cleanup (mpi_t * pi)
+c4_wq_port_cleanup (mpi_t *pi)
{
/*
* PORT POINT: cannot call this if WQ is statically allocated w/in
@@ -278,7 +278,7 @@ c4_ebus_interrupt (int irq, void *dev_instance)
static int
-void_open (struct net_device * ndev)
+void_open (struct net_device *ndev)
{
pr_info("%s: trying to open master device !\n", ndev->name);
return -1;
@@ -286,7 +286,7 @@ void_open (struct net_device * ndev)
STATIC int
-chan_open (struct net_device * ndev)
+chan_open (struct net_device *ndev)
{
hdlc_device *hdlc = dev_to_hdlc (ndev);
const struct c4_priv *priv = hdlc->priv;
@@ -306,7 +306,7 @@ chan_open (struct net_device * ndev)
STATIC int
-chan_close (struct net_device * ndev)
+chan_close (struct net_device *ndev)
{
hdlc_device *hdlc = dev_to_hdlc (ndev);
const struct c4_priv *priv = hdlc->priv;
@@ -320,14 +320,14 @@ chan_close (struct net_device * ndev)
STATIC int
-chan_dev_ioctl (struct net_device * dev, struct ifreq * ifr, int cmd)
+chan_dev_ioctl (struct net_device *dev, struct ifreq *ifr, int cmd)
{
return hdlc_ioctl (dev, ifr, cmd);
}
STATIC int
-chan_attach_noop (struct net_device * ndev, unsigned short foo_1, unsigned short foo_2)
+chan_attach_noop (struct net_device *ndev, unsigned short foo_1, unsigned short foo_2)
{
return 0; /* our driver has nothing to do here, show's
* over, go home */
@@ -335,7 +335,7 @@ chan_attach_noop (struct net_device * ndev, unsigned short foo_1, unsigned short
STATIC struct net_device_stats *
-chan_get_stats (struct net_device * ndev)
+chan_get_stats (struct net_device *ndev)
{
mch_t *ch;
struct net_device_stats *nstats;
@@ -388,14 +388,14 @@ chan_get_stats (struct net_device * ndev)
static ci_t *
-get_ci_by_dev (struct net_device * ndev)
+get_ci_by_dev (struct net_device *ndev)
{
return (ci_t *)(netdev_priv(ndev));
}
STATIC int
-c4_linux_xmit (struct sk_buff * skb, struct net_device * ndev)
+c4_linux_xmit (struct sk_buff *skb, struct net_device *ndev)
{
const struct c4_priv *priv;
int rval;
@@ -417,8 +417,8 @@ static const struct net_device_ops chan_ops = {
};
STATIC struct net_device *
-create_chan (struct net_device * ndev, ci_t * ci,
- struct sbecom_chan_param * cp)
+create_chan (struct net_device *ndev, ci_t *ci,
+ struct sbecom_chan_param *cp)
{
hdlc_device *hdlc;
struct net_device *dev;
@@ -510,7 +510,7 @@ create_chan (struct net_device * ndev, ci_t * ci,
/* the idea here is to get port information and pass it back (using pointer) */
STATIC status_t
-do_get_port (struct net_device * ndev, void *data)
+do_get_port (struct net_device *ndev, void *data)
{
int ret;
ci_t *ci; /* ci stands for card information */
@@ -535,7 +535,7 @@ do_get_port (struct net_device * ndev, void *data)
/* this function copys the user data and then calls the real action function */
STATIC status_t
-do_set_port (struct net_device * ndev, void *data)
+do_set_port (struct net_device *ndev, void *data)
{
ci_t *ci; /* ci stands for card information */
struct sbecom_port_param pp;/* copy data to kernel land */
@@ -557,7 +557,7 @@ do_set_port (struct net_device * ndev, void *data)
/* work the port loopback mode as per directed */
STATIC status_t
-do_port_loop (struct net_device * ndev, void *data)
+do_port_loop (struct net_device *ndev, void *data)
{
struct sbecom_port_param pp;
ci_t *ci;
@@ -572,7 +572,7 @@ do_port_loop (struct net_device * ndev, void *data)
/* set the specified register with the given value / or just read it */
STATIC status_t
-do_framer_rw (struct net_device * ndev, void *data)
+do_framer_rw (struct net_device *ndev, void *data)
{
struct sbecom_port_param pp;
ci_t *ci;
@@ -593,7 +593,7 @@ do_framer_rw (struct net_device * ndev, void *data)
/* set the specified register with the given value / or just read it */
STATIC status_t
-do_pld_rw (struct net_device * ndev, void *data)
+do_pld_rw (struct net_device *ndev, void *data)
{
struct sbecom_port_param pp;
ci_t *ci;
@@ -614,7 +614,7 @@ do_pld_rw (struct net_device * ndev, void *data)
/* set the specified register with the given value / or just read it */
STATIC status_t
-do_musycc_rw (struct net_device * ndev, void *data)
+do_musycc_rw (struct net_device *ndev, void *data)
{
struct c4_musycc_param mp;
ci_t *ci;
@@ -634,7 +634,7 @@ do_musycc_rw (struct net_device * ndev, void *data)
}
STATIC status_t
-do_get_chan (struct net_device * ndev, void *data)
+do_get_chan (struct net_device *ndev, void *data)
{
struct sbecom_chan_param cp;
int ret;
@@ -652,7 +652,7 @@ do_get_chan (struct net_device * ndev, void *data)
}
STATIC status_t
-do_set_chan (struct net_device * ndev, void *data)
+do_set_chan (struct net_device *ndev, void *data)
{
struct sbecom_chan_param cp;
int ret;
@@ -673,7 +673,7 @@ do_set_chan (struct net_device * ndev, void *data)
}
STATIC status_t
-do_create_chan (struct net_device * ndev, void *data)
+do_create_chan (struct net_device *ndev, void *data)
{
ci_t *ci;
struct net_device *dev;
@@ -700,7 +700,7 @@ do_create_chan (struct net_device * ndev, void *data)
}
STATIC status_t
-do_get_chan_stats (struct net_device * ndev, void *data)
+do_get_chan_stats (struct net_device *ndev, void *data)
{
struct c4_chan_stats_wrap ccs;
int ret;
@@ -721,7 +721,7 @@ do_get_chan_stats (struct net_device * ndev, void *data)
return 0;
}
STATIC status_t
-do_set_loglevel (struct net_device * ndev, void *data)
+do_set_loglevel (struct net_device *ndev, void *data)
{
unsigned int cxt1e1_log_level;
@@ -732,7 +732,7 @@ do_set_loglevel (struct net_device * ndev, void *data)
}
STATIC status_t
-do_deluser (struct net_device * ndev, int lockit)
+do_deluser (struct net_device *ndev, int lockit)
{
if (ndev->flags & IFF_UP)
return -EBUSY;
@@ -763,7 +763,7 @@ do_deluser (struct net_device * ndev, int lockit)
}
int
-do_del_chan (struct net_device * musycc_dev, void *data)
+do_del_chan (struct net_device *musycc_dev, void *data)
{
struct sbecom_chan_param cp;
char buf[sizeof (CHANNAME) + 3];
@@ -787,7 +787,7 @@ do_del_chan (struct net_device * musycc_dev, void *data)
int c4_reset_board (void *);
int
-do_reset (struct net_device * musycc_dev, void *data)
+do_reset (struct net_device *musycc_dev, void *data)
{
const struct c4_priv *priv;
int i;
@@ -816,7 +816,7 @@ do_reset (struct net_device * musycc_dev, void *data)
}
int
-do_reset_chan_stats (struct net_device * musycc_dev, void *data)
+do_reset_chan_stats (struct net_device *musycc_dev, void *data)
{
struct sbecom_chan_param cp;
@@ -827,7 +827,7 @@ do_reset_chan_stats (struct net_device * musycc_dev, void *data)
}
STATIC status_t
-c4_ioctl (struct net_device * ndev, struct ifreq * ifr, int cmd)
+c4_ioctl (struct net_device *ndev, struct ifreq *ifr, int cmd)
{
ci_t *ci;
void *data;
@@ -954,7 +954,7 @@ static void c4_setup(struct net_device *dev)
}
struct net_device *__init
-c4_add_dev (hdw_info_t * hi, int brdno, unsigned long f0, unsigned long f1,
+c4_add_dev (hdw_info_t *hi, int brdno, unsigned long f0, unsigned long f1,
int irq0, int irq1)
{
struct net_device *ndev;
diff --git a/drivers/staging/cxt1e1/musycc.c b/drivers/staging/cxt1e1/musycc.c
index b2cc68a..1037086 100644
--- a/drivers/staging/cxt1e1/musycc.c
+++ b/drivers/staging/cxt1e1/musycc.c
@@ -74,7 +74,7 @@ void musycc_update_timeslots(mpi_t *);
#if 1
STATIC int
-musycc_dump_rxbuffer_ring(mch_t * ch, int lockit)
+musycc_dump_rxbuffer_ring(mch_t *ch, int lockit)
{
struct mdesc *m;
unsigned long flags = 0;
@@ -140,7 +140,7 @@ musycc_dump_rxbuffer_ring(mch_t * ch, int lockit)
#if 1
STATIC int
-musycc_dump_txbuffer_ring(mch_t * ch, int lockit)
+musycc_dump_txbuffer_ring(mch_t *ch, int lockit)
{
struct mdesc *m;
unsigned long flags = 0;
@@ -205,7 +205,7 @@ musycc_dump_txbuffer_ring(mch_t * ch, int lockit)
*/
status_t
-musycc_dump_ring(ci_t * ci, unsigned int chan)
+musycc_dump_ring(ci_t *ci, unsigned int chan)
{
mch_t *ch;
@@ -248,7 +248,7 @@ musycc_dump_ring(ci_t * ci, unsigned int chan)
status_t
-musycc_dump_rings(ci_t * ci, unsigned int start_chan)
+musycc_dump_rings(ci_t *ci, unsigned int start_chan)
{
unsigned int chan;
@@ -264,7 +264,7 @@ musycc_dump_rings(ci_t * ci, unsigned int start_chan)
*/
void
-musycc_init_mdt(mpi_t * pi)
+musycc_init_mdt(mpi_t *pi)
{
u_int32_t *addr, cfg;
int i;
@@ -288,7 +288,7 @@ musycc_init_mdt(mpi_t * pi)
/* Set TX thp to the next unprocessed md */
void
-musycc_update_tx_thp(mch_t * ch)
+musycc_update_tx_thp(mch_t *ch)
{
struct mdesc *md;
unsigned long flags;
@@ -443,7 +443,7 @@ musycc_wq_chan_restart(void *arg) /* channel private structure */
*/
void
-musycc_chan_restart(mch_t * ch)
+musycc_chan_restart(mch_t *ch)
{
#ifdef RLD_RESTART_DEBUG
pr_info("++ musycc_chan_restart[%d]: txd_irq_srv @ %p = sts %x\n",
@@ -461,7 +461,7 @@ musycc_chan_restart(mch_t * ch)
void
-rld_put_led(mpi_t * pi, u_int32_t ledval)
+rld_put_led(mpi_t *pi, u_int32_t ledval)
{
static u_int32_t led = 0;
@@ -477,7 +477,7 @@ rld_put_led(mpi_t * pi, u_int32_t ledval)
#define MUSYCC_SR_RETRY_CNT 9
void
-musycc_serv_req(mpi_t * pi, u_int32_t req)
+musycc_serv_req(mpi_t *pi, u_int32_t req)
{
volatile u_int32_t r;
int rcnt;
@@ -578,7 +578,7 @@ rewrite:
#ifdef SBE_PMCC4_ENABLE
void
-musycc_update_timeslots(mpi_t * pi)
+musycc_update_timeslots(mpi_t *pi)
{
int i, ch;
char e1mode = IS_FRAME_ANY_E1(pi->p.port_mode);
@@ -640,7 +640,7 @@ musycc_update_timeslots(mpi_t * pi)
#ifdef SBE_WAN256T3_ENABLE
void
-musycc_update_timeslots(mpi_t * pi)
+musycc_update_timeslots(mpi_t *pi)
{
mch_t *ch;
@@ -703,7 +703,7 @@ musycc_chan_proto(int proto)
#ifdef SBE_WAN256T3_ENABLE
STATIC void __init
-musycc_init_port(mpi_t * pi)
+musycc_init_port(mpi_t *pi)
{
pci_write_32((u_int32_t *) &pi->reg->gbp, OS_vtophys(pi->regram));
@@ -737,7 +737,7 @@ musycc_init_port(mpi_t * pi)
status_t __init
-musycc_init(ci_t * ci)
+musycc_init(ci_t *ci)
{
char *regaddr; /* temp for address boundary calculations */
int i, gchan;
@@ -832,7 +832,7 @@ musycc_init(ci_t * ci)
void
-musycc_bh_tx_eom(mpi_t * pi, int gchan)
+musycc_bh_tx_eom(mpi_t *pi, int gchan)
{
mch_t *ch;
struct mdesc *md;
@@ -1010,7 +1010,7 @@ musycc_bh_tx_eom(mpi_t * pi, int gchan)
STATIC void
-musycc_bh_rx_eom(mpi_t * pi, int gchan)
+musycc_bh_rx_eom(mpi_t *pi, int gchan)
{
mch_t *ch;
void *m, *m2;
@@ -1229,7 +1229,7 @@ unsigned long
#else
void
#endif
-musycc_intr_bh_tasklet(ci_t * ci)
+musycc_intr_bh_tasklet(ci_t *ci)
{
mpi_t *pi;
mch_t *ch;
@@ -1517,7 +1517,7 @@ musycc_intr_bh_tasklet(ci_t * ci)
#if 0
int __init
-musycc_new_chan(ci_t * ci, int channum, void *user)
+musycc_new_chan(ci_t *ci, int channum, void *user)
{
mch_t *ch;
@@ -1546,7 +1546,7 @@ musycc_new_chan(ci_t * ci, int channum, void *user)
#ifdef SBE_PMCC4_ENABLE
status_t
-musycc_chan_down(ci_t * dummy, int channum)
+musycc_chan_down(ci_t *dummy, int channum)
{
mpi_t *pi;
mch_t *ch;
@@ -1597,7 +1597,7 @@ musycc_chan_down(ci_t * dummy, int channum)
int
-musycc_del_chan(ci_t * ci, int channum)
+musycc_del_chan(ci_t *ci, int channum)
{
mch_t *ch;
@@ -1613,7 +1613,7 @@ musycc_del_chan(ci_t * ci, int channum)
int
-musycc_del_chan_stats(ci_t * ci, int channum)
+musycc_del_chan_stats(ci_t *ci, int channum)
{
mch_t *ch;
@@ -1628,7 +1628,7 @@ musycc_del_chan_stats(ci_t * ci, int channum)
int
-musycc_start_xmit(ci_t * ci, int channum, void *mem_token)
+musycc_start_xmit(ci_t *ci, int channum, void *mem_token)
{
mch_t *ch;
struct mdesc *md;
diff --git a/drivers/staging/cxt1e1/pmcc4.h b/drivers/staging/cxt1e1/pmcc4.h
index b0ed4ad..003eb86 100644
--- a/drivers/staging/cxt1e1/pmcc4.h
+++ b/drivers/staging/cxt1e1/pmcc4.h
@@ -85,15 +85,15 @@ void c4_cleanup (void);
status_t c4_chan_up (ci_t *, int channum);
status_t c4_del_chan_stats (int channum);
status_t c4_del_chan (int channum);
-status_t c4_get_iidinfo (ci_t * ci, struct sbe_iid_info * iip);
+status_t c4_get_iidinfo (ci_t *ci, struct sbe_iid_info *iip);
int c4_is_chan_up (int channum);
void *getuserbychan (int channum);
-void pci_flush_write (ci_t * ci);
+void pci_flush_write (ci_t *ci);
void sbecom_set_loglevel (int debuglevel);
-char *sbeid_get_bdname (ci_t * ci);
-void sbeid_set_bdtype (ci_t * ci);
-void sbeid_set_hdwbid (ci_t * ci);
+char *sbeid_get_bdname (ci_t *ci);
+void sbeid_set_bdtype (ci_t *ci);
+void sbeid_set_hdwbid (ci_t *ci);
u_int32_t sbeCrc (u_int8_t *, u_int32_t, u_int32_t, u_int32_t *);
void VMETRO_TRACE (void *); /* put data into 8 LEDs */
diff --git a/drivers/staging/cxt1e1/pmcc4_drv.c b/drivers/staging/cxt1e1/pmcc4_drv.c
index 8d8a22b..32d7a21 100644
--- a/drivers/staging/cxt1e1/pmcc4_drv.c
+++ b/drivers/staging/cxt1e1/pmcc4_drv.c
@@ -28,7 +28,7 @@
#include <linux/sched.h> /* include for timer */
#include <linux/timer.h> /* include for timer */
#include <linux/hdlc.h>
-#include <asm/io.h>
+#include <linux/io.h>
#include "sbecom_inline_linux.h"
#include "libsbew.h"
@@ -123,7 +123,7 @@ c4_find_chan (int channum)
{
if ((ch->state != UNASSIGNED) &&
(ch->channum == channum))
- return (ch);
+ return ch;
}
}
return 0;
@@ -193,7 +193,7 @@ c4_new (void *hi)
#define COMET_LBCMD_READ 0x80 /* read only (do not set, return read value) */
void
-checkPorts (ci_t * ci)
+checkPorts (ci_t *ci)
{
#ifndef CONFIG_SBE_PMCC4_NCOMM
/*
@@ -459,7 +459,7 @@ checkPorts (ci_t * ci)
STATIC void
-c4_watchdog (ci_t * ci)
+c4_watchdog (ci_t *ci)
{
if (drvr_state != SBE_DRVR_AVAILABLE)
{
@@ -512,7 +512,7 @@ c4_cleanup (void)
*/
int
-c4_get_portcfg (ci_t * ci)
+c4_get_portcfg (ci_t *ci)
{
comet_t *comet;
int portnum, mask;
@@ -536,7 +536,7 @@ c4_get_portcfg (ci_t * ci)
/* nothing herein should generate interrupts */
status_t __init
-c4_init (ci_t * ci, u_char *func0, u_char *func1)
+c4_init (ci_t *ci, u_char *func0, u_char *func1)
{
mpi_t *pi;
mch_t *ch;
@@ -670,7 +670,7 @@ c4_init (ci_t * ci, u_char *func0, u_char *func1)
/* better be fully setup to handle interrupts when you call this */
status_t __init
-c4_init2 (ci_t * ci)
+c4_init2 (ci_t *ci)
{
status_t ret;
@@ -698,7 +698,7 @@ c4_init2 (ci_t * ci)
/* This function sets the loopback mode (or clears it, as the case may be). */
int
-c4_loop_port (ci_t * ci, int portnum, u_int8_t cmd)
+c4_loop_port (ci_t *ci, int portnum, u_int8_t cmd)
{
comet_t *comet;
volatile u_int32_t loopValue;
@@ -757,7 +757,7 @@ c4_loop_port (ci_t * ci, int portnum, u_int8_t cmd)
*/
status_t
-c4_frame_rw (ci_t * ci, struct sbecom_port_param * pp)
+c4_frame_rw (ci_t *ci, struct sbecom_port_param *pp)
{
comet_t *comet;
volatile u_int32_t data;
@@ -796,7 +796,7 @@ c4_frame_rw (ci_t * ci, struct sbecom_port_param * pp)
*/
status_t
-c4_pld_rw (ci_t * ci, struct sbecom_port_param * pp)
+c4_pld_rw (ci_t *ci, struct sbecom_port_param *pp)
{
volatile u_int32_t *regaddr;
volatile u_int32_t data;
@@ -834,7 +834,7 @@ c4_pld_rw (ci_t * ci, struct sbecom_port_param * pp)
*/
status_t
-c4_musycc_rw (ci_t * ci, struct c4_musycc_param * mcp)
+c4_musycc_rw (ci_t *ci, struct c4_musycc_param *mcp)
{
mpi_t *pi;
volatile u_int32_t *dph; /* hardware implemented register */
@@ -898,7 +898,7 @@ c4_musycc_rw (ci_t * ci, struct c4_musycc_param * mcp)
}
status_t
-c4_get_port (ci_t * ci, int portnum)
+c4_get_port (ci_t *ci, int portnum)
{
if (portnum >= ci->max_port) /* sanity check */
return ENXIO;
@@ -913,7 +913,7 @@ c4_get_port (ci_t * ci, int portnum)
}
status_t
-c4_set_port (ci_t * ci, int portnum)
+c4_set_port (ci_t *ci, int portnum)
{
mpi_t *pi;
struct sbecom_port_param *pp;
@@ -942,7 +942,7 @@ c4_set_port (ci_t * ci, int portnum)
if ((ret = c4_wq_port_init (pi))) /* create/init
* workqueue_struct */
- return (ret);
+ return ret;
}
init_comet (ci, pi->cometbase, pp->port_mode, 1 /* clockmaster == true */ , pp->portP);
@@ -1018,7 +1018,7 @@ c4_set_port (ci_t * ci, int portnum)
unsigned int max_int = 0;
status_t
-c4_new_chan (ci_t * ci, int portnum, int channum, void *user)
+c4_new_chan (ci_t *ci, int portnum, int channum, void *user)
{
mpi_t *pi;
mch_t *ch;
@@ -1111,7 +1111,7 @@ c4_del_chan_stats (int channum)
status_t
-c4_set_chan (int channum, struct sbecom_chan_param * p)
+c4_set_chan (int channum, struct sbecom_chan_param *p)
{
mch_t *ch;
int i, x = 0;
@@ -1162,7 +1162,7 @@ c4_set_chan (int channum, struct sbecom_chan_param * p)
status_t
-c4_get_chan (int channum, struct sbecom_chan_param * p)
+c4_get_chan (int channum, struct sbecom_chan_param *p)
{
mch_t *ch;
@@ -1173,7 +1173,7 @@ c4_get_chan (int channum, struct sbecom_chan_param * p)
}
status_t
-c4_get_chan_stats (int channum, struct sbecom_chan_stats * p)
+c4_get_chan_stats (int channum, struct sbecom_chan_stats *p)
{
mch_t *ch;
@@ -1185,7 +1185,7 @@ c4_get_chan_stats (int channum, struct sbecom_chan_stats * p)
}
STATIC int
-c4_fifo_alloc (mpi_t * pi, int chan, int *len)
+c4_fifo_alloc (mpi_t *pi, int chan, int *len)
{
int i, l = 0, start = 0, max = 0, maxstart = 0;
@@ -1222,7 +1222,7 @@ c4_fifo_alloc (mpi_t * pi, int chan, int *len)
}
void
-c4_fifo_free (mpi_t * pi, int chan)
+c4_fifo_free (mpi_t *pi, int chan)
{
int i;
@@ -1236,7 +1236,7 @@ c4_fifo_free (mpi_t * pi, int chan)
status_t
-c4_chan_up (ci_t * ci, int channum)
+c4_chan_up (ci_t *ci, int channum)
{
mpi_t *pi;
mch_t *ch;
@@ -1467,7 +1467,7 @@ errfree:
/* stop the hardware from servicing & interrupting */
void
-c4_stopwd (ci_t * ci)
+c4_stopwd (ci_t *ci)
{
OS_stop_watchdog (&ci->wd);
SD_SEM_TAKE (&ci->sem_wdbusy, "_stop_"); /* ensure WD not running */
@@ -1476,7 +1476,7 @@ c4_stopwd (ci_t * ci)
void
-sbecom_get_brdinfo (ci_t * ci, struct sbe_brd_info * bip, u_int8_t *bsn)
+sbecom_get_brdinfo (ci_t *ci, struct sbe_brd_info *bip, u_int8_t *bsn)
{
char *np;
u_int32_t sn = 0;
@@ -1485,7 +1485,7 @@ sbecom_get_brdinfo (ci_t * ci, struct sbe_brd_info * bip, u_int8_t *bsn)
bip->brdno = ci->brdno; /* our board number */
bip->brd_id = ci->brd_id;
bip->brd_hdw_id = ci->hdw_bid;
- bip->brd_chan_cnt = MUSYCC_NCHANS * ci->max_port; /* number of channels
+ bip->brd_chan_cnt = MUSYCC_NCHANS *ci->max_port; /* number of channels
* being used */
bip->brd_port_cnt = ci->max_port; /* number of ports being used */
bip->brd_pci_speed = BINFO_PCI_SPEED_unk; /* PCI speed not yet
@@ -1535,7 +1535,7 @@ sbecom_get_brdinfo (ci_t * ci, struct sbe_brd_info * bip, u_int8_t *bsn)
status_t
-c4_get_iidinfo (ci_t * ci, struct sbe_iid_info * iip)
+c4_get_iidinfo (ci_t *ci, struct sbe_iid_info *iip)
{
struct net_device *dev;
char *np;
@@ -1624,7 +1624,7 @@ wanpmcC4T1E1_getBaseAddress (int cardID, int deviceID)
}
ci = ci->next; /* next board, if any */
}
- return (base);
+ return base;
}
#endif /*** CONFIG_SBE_PMCC4_NCOMM ***/
diff --git a/drivers/staging/cxt1e1/sbecom_inline_linux.h b/drivers/staging/cxt1e1/sbecom_inline_linux.h
index 68ed445..3c6d1c0 100644
--- a/drivers/staging/cxt1e1/sbecom_inline_linux.h
+++ b/drivers/staging/cxt1e1/sbecom_inline_linux.h
@@ -177,7 +177,7 @@ struct watchdog
static inline int
-OS_start_watchdog (struct watchdog * wd)
+OS_start_watchdog (struct watchdog *wd)
{
wd->h.expires = jiffies + wd->ticks;
add_timer (&wd->h);
@@ -186,7 +186,7 @@ OS_start_watchdog (struct watchdog * wd)
static inline int
-OS_stop_watchdog (struct watchdog * wd)
+OS_stop_watchdog (struct watchdog *wd)
{
del_timer_sync (&wd->h);
return 0;
@@ -194,7 +194,7 @@ OS_stop_watchdog (struct watchdog * wd)
static inline int
-OS_free_watchdog (struct watchdog * wd)
+OS_free_watchdog (struct watchdog *wd)
{
OS_stop_watchdog (wd);
OS_kfree (wd);
diff --git a/drivers/staging/cxt1e1/sbeid.c b/drivers/staging/cxt1e1/sbeid.c
index a2243b1..0f9bd5f 100644
--- a/drivers/staging/cxt1e1/sbeid.c
+++ b/drivers/staging/cxt1e1/sbeid.c
@@ -27,7 +27,7 @@
char *
-sbeid_get_bdname (ci_t * ci)
+sbeid_get_bdname (ci_t *ci)
{
char *np = 0;
@@ -73,7 +73,7 @@ sbeid_get_bdname (ci_t * ci)
/* given the presetting of brd_id, set the corresponding hdw_id */
void
-sbeid_set_hdwbid (ci_t * ci)
+sbeid_set_hdwbid (ci_t *ci)
{
/*
* set SBE's unique hardware identification (for legacy boards might not
@@ -170,7 +170,7 @@ sbeid_set_hdwbid (ci_t * ci)
/* given the presetting of hdw_bid, set the corresponding brd_id */
void
-sbeid_set_bdtype (ci_t * ci)
+sbeid_set_bdtype (ci_t *ci)
{
/* set SBE's unique PCI VENDOR/DEVID */
switch (ci->hdw_bid)
diff --git a/drivers/staging/cxt1e1/sbeproc.h b/drivers/staging/cxt1e1/sbeproc.h
index e5c072c..37285df 100644
--- a/drivers/staging/cxt1e1/sbeproc.h
+++ b/drivers/staging/cxt1e1/sbeproc.h
@@ -28,11 +28,11 @@ int __init sbecom_proc_brd_init (ci_t *);
#else
-static inline void sbecom_proc_brd_cleanup(ci_t * ci)
+static inline void sbecom_proc_brd_cleanup(ci_t *ci)
{
}
-static inline int __init sbecom_proc_brd_init(ci_t * ci)
+static inline int __init sbecom_proc_brd_init(ci_t *ci)
{
return 0;
}