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2015-10-14fmd: fix policer spelling issuesMandy Lavi
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
2015-10-14fmd: Remove FM_PORT_PcdPrsModifyStartOffset routine - not supportedMandy Lavi
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
2015-10-13fsl_qbman: enable sending cscn to dcp for old qman revisionHaiying Wang
Set CSCN_TARG with correct DCP portal in qman_create_cgr_to_dcp() funciton for the qman revision < qman_3.0 JIRA issue# QLINUX-3814 Signed-off-by: Haiying Wang <Haiying.wang@freescale.com>
2015-10-13t4240dts: correct the ceetm nodeHaiying Wang
The patch e9cacc46fcd4ebd1b2238a2655d08ad42e87f7d2 only added CEETM node qman-ceetm0 in t4240si-post.dts, and defined 8 ceetm channels. It is not correct for T4240 which has QMan 3.x version to support 32 CEETM channels. Besides, T4240 supports 2 CEETMs, so 2 ceetm nodes should be included in this device tree. JIRA issue# QLINUX-3737 Signed-off-by: Haiying Wang <Haiying.wang@freescale.com>
2015-09-24dpaa_eth: Add a configurable dpa_tx callCamelia Groza
Signed-off-by: Camelia Groza <camelia.groza@freescale.com>
2015-09-24mmc: sdhci-of-esdhc: fix compile error on ARM platformYangbo Lu
Fix two compile errors below, error: implicit declaration of function 'of_iomap' error: implicit declaration of function 'out_be32' Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
2015-09-24QorIQ/TMU: add TMU node to device tree for QorIQ T1023/T1024Jia Hongtao
The Thermal Monitoring Unit node for T1023/T1024. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
2015-09-24QorIQ/TMU: add thermal management support based on TMUJia Hongtao
It supports one critical trip point and one passive trip point. The cpufreq is used as the cooling device to throttle CPUs when the passive trip is crossed. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
2015-09-24QorIQ/TMU: add TMU node to device tree for QorIQ T1040/T1042Jia Hongtao
This is Thermal Monitoring Unit for QorIQ platform. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
2015-09-24thermal: fix cpu_cooling max_level behaviorEduardo Valentin
As per Documentation/thermal/sysfs-api.txt, max_level is an index, not a counter. Thus, in case a CPU has 3 valid frequencies, max_level is expected to be 2, for instance. The current code makes max_level == number of valid frequencies, which is bogus. This patch fix the cpu_cooling device by ranging max_level properly. Reported-by: Carlos Hernandez <ceh@ti.com> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2015-09-24mmc: sdhci-of-esdhc: add SDR50 mode support for SD/MMC Legacy Adapter CardYangbo Lu
The eSDHC is not compatible with SD spec well, so we need to use eSDHC-specific code to switch to SDR50 mode. 1. IO signal voltage switching, eSDHC uses SDHC_VS to switch io voltage and it's needed to configure a global utilities register SCFG_SDHCIOVSELCR(if it has) and SDHC_VS signal. 2. Before executing tuning procedure, eSDHC should set its own tuning block. static const struct sdhci_ops sdhci_esdhc_ops = { ... .set_tuning_block = esdhc_set_tuning_block, .signal_voltage_switch = esdhc_signal_voltage_switch, }; Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
2015-09-24mmc: esdhc: add eMMC45 Adapter Card HS200 mode supportYangbo Lu
The eSDHC is not compatible with SD spec well, it's needed to add callbacks for signal voltage switching and tuning block setting for eSDHC for eMMC45 Adapter Card HS200 mode support. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
2015-09-23QorIQ/TMU: add TMU node to device tree for LS1021AJia Hongtao
The Thermal Monitoring Unit node for LS1021A. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
2015-09-07Merge branch 'feature/LS1-for-SDK' of ↵jason
ssh://sw-stash.freescale.net/dnnpi/ls1-linux-jason into LS1-SDKV04-SDK1.9
2015-08-21t104xd4rdb: add DS26522 nodes to device treeZhao Qiang
DS26522 is used for tdm, configured by SPI bus. Add nodes under spi node to t104xd4rdb.dtsi. Signed-off-by: Zhao Qiang <qiang.zhao@freescale.com>
2015-07-20Merge branch 'qoriq-sdk' into LS1-SDK-Rev2.0jason
2015-07-14arm: ls1021a: mask interrupts before entering deep sleepChenhui Zhao
Before entering deep sleep, interrupts should be masked. Or, unexpected interrupts may block the process of deep sleep. So, mask interrupts by the following steps: 1. Mask interrupts to RCPM 2. Disable the GIC This will make deep sleep more stable. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: I601062f8406324a308ef44491fed7cf479eaeba9 Reviewed-on: http://git.am.freescale.net:8181/39602 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-07-10arm: dts: ls1021a: Add transfer mode property in DSPI2 nodeHaikun Wang
DSPI new driver can select transfer mode(tcfq/eoq) to work. The property will be read from dtsi node. Add the property tcfq-mode for LS1021a. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Change-Id: I09efa9277364b79d075a1de94bd04111e2434576 Reviewed-on: http://git.am.freescale.net:8181/39515 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-07-10arm: dts: ls1021atwr: Enable DSPI2 dts nodeHaikun Wang
Erratum A-008022 has been fixed on LS1021A Rev2.0. So we can use DSPI2 now, this patch enable DSPI2 in dts for LS1021ATWR. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Change-Id: I00c76415c155a290eecbde8b37e6148b11ed2c07 Reviewed-on: http://git.am.freescale.net:8181/39514 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-07-09arm: ls1021a: change the order of setting PMC interrupt registersChenhui Zhao
In deep sleep process, set interrupt status and polarity registers before enabling PMC interrupts. It is more stable, especially on ls1021a-twr board. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: I8305e25a76f0bcc636b58178495165c915ac3c1a Reviewed-on: http://git.am.freescale.net:8181/39478 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-07-09crypto: caam - fix SEC ERA readingAlex Porosanu
In order to ensure that the SEC ERA property is properly read from DTS, of_property_read* functions need to be used. Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com> Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Change-Id: I3fe958ca9b0ab91c2dbd089d1b2f090042cc3fd0 Reviewed-on: http://git.am.freescale.net:8181/39374 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-07-09crypto: caam - fix snooping for write transactionsHoria Geantă
HW coherency won't work properly for CAAM write transactions if AWCACHE is left to default (POR) value - 4'b0001. It has to be programmed to 4'b0010. For platforms that have HW coherency support: -PPC-based: the update has no effect; CAAM coherency already works due to the IOMMU (PAMU) driver setting the correct memory coherency attributes -ARM-based: the update fixes cache coherency issues, since IOMMU (SMMU) driver is not programmed to behave similar to PAMU Change-Id: I1f91a526c0bdf28b799d19cab9599b115cad55b3 Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/39256 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-07-03arm/dts: Add node for ina220 on LS1021ATWR-RevYuan Yao
Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Change-Id: Iae6ec5f13ae85e26c2bf50efe55e81d91eba3d8d Reviewed-on: http://git.am.freescale.net:8181/39246 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-07-03arm/defconfig: Add Atheros AT803X PHYs supportYuan Yao
Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Change-Id: Iaba32fdf49bddbd7ee9b8f0f77847f7399c08a3f Reviewed-on: http://git.am.freescale.net:8181/39245 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16QE/HDLC: modify QE-HDLC for both ARM and POWERPCZhao Qiang
ls1021 support QE IP block and it is arm, So modify QE-HDLC code to adapt bothe arm and powerpc Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I9e02e53ae1fafffeec3bf7145309002db19c2dc1 Reviewed-on: http://git.am.freescale.net:8181/38130 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16Test patch: Enable CAN SoC level loopbackBhupesh Sharma
This patch enables the SoC level CAN loopback. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: I5efd40f5d853d11b2476b2bbab0db66c7b1711fa Reviewed-on: http://git.am.freescale.net:8181/38097 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16arm/dts: Add nodes for flexcan devices present on LS1021A-Rev2 SoCBhupesh Sharma
This patch adds the device nodes for flexcan controller(s) present on LS1021A-Rev2 SoC. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com> Change-Id: Ia301d4db49d337e37def2e6667b6e4e1586fd8fc Reviewed-on: http://git.am.freescale.net:8181/38096 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16can: flexcan: Add support for non RX-FIFO modeBhupesh Sharma
This patch adds support for non RX-FIFO (legacy) mode in the flexcan driver. On certain SoCs, the RX-FIFO support might be broken, as a result we need to fall-back on the legacy (non RX-FIFO) mode to receive CAN frames. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com> Change-Id: I8b07e851b68fcca9716d02b14b6712c2da654ad5 Reviewed-on: http://git.am.freescale.net:8181/38095 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16can: flexcan: Remodel FlexCAN register r/w APIs for BE instancesBhupesh Sharma
The FlexCAN IP on certain SoCs like (Freescale's LS1021A) is modelled in a big-endian fashion, i.e. the registers and the message buffers are organized in a BE way. More details about the LS1021A SoC can be seen here: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=LS1021A&nodeId=018rH325E4017B# This patch ensures that the register read/write APIs are remodelled to address such cases, while ensuring that existing platforms (where the FlexCAN IP was modelled in LE way) do not break. Tested on LS1021A-QDS board. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com> Change-Id: I4116956dfc92ae565a2aea96356014c77f506c1c Reviewed-on: http://git.am.freescale.net:8181/38094 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16can: flexcan: Add ls1021a flexcan device entryBhupesh Sharma
This patch adds ls1021a flexcan device entry to the flexcan driver code. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: Iad4f7caf7be878784414d194335f203ea02743e5 Reviewed-on: http://git.am.freescale.net:8181/38093 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16doc/bindings: Add 'endianess' optional-property for FlexCAN controllerBhupesh Sharma
This patch adds 'endianess' as the optional-property for describing the FlexCAN controller present on various FSL platforms. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com> Change-Id: I35f5860a3b900ee6344ad807aa04923f0f82dd55 Reviewed-on: http://git.am.freescale.net:8181/38092 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16Revert 'can: flexcan: Add ls1021a flexcan device entry'Bhupesh Sharma
This reverts commit 61af51e63ff5a3666788b1c5c2d42c3df3a03c34. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: I196e1fbc30a97ae0102b13eddd25bdf9230e02f4 Reviewed-on: http://git.am.freescale.net:8181/38091 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16Revert 'net: can: Remodel FlexCAN register read/write APIs for BE instances'Bhupesh Sharma
This reverts commit 4966cbb525a2acfb7c2782f1994949e97b45f242. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: Ifec4963a1ed01fb60f949575e1c2be4da5c38cf6 Reviewed-on: http://git.am.freescale.net:8181/38090 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16Revert 'can: flexcan: Add support for non RX-FIFO mode and conditional ↵Bhupesh Sharma
ERRATA ERR005829 handling' This reverts commit 0ec580b6a604a4fcfd65c3515459def643c8517a. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: I64fb32407f7083aa433d4d7ec34d7171c2bdc02b Reviewed-on: http://git.am.freescale.net:8181/38089 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16mmc: sdhci: more efficient interrupt enable register handlingYangbo Lu
Rather than wasting cycles read-modify-writing the interrupt enable registers, cache the value locally instead. This patch is from upstreaming linux, commit id b537f94ce19583de1882f539a5cc49aa99260aca Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Change-Id: I3c1bb4d4b3f7d7dccbaa4748816bfe381edc484c Reviewed-on: http://git.am.freescale.net:8181/37869 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-12pci/layerscape: update MSI code for ls1021 rev2 MSI supportMinghuan Lian
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I68ac4e509f41c249d38579b34cb78d35e9231b0f Reviewed-on: http://git.am.freescale.net:8181/37558 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-11mmc: sdhci-pltfm: enable interrupt mode to detect cardYangbo Lu
Enable interrupt mode to detect card instead of polling mode for ls1021a by removing the quirk SDHCI_QUIRK_BROKEN_CARD_DETECTION. This could improve data transferring performance and avoid the call trace caused by polling card status sometime. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Change-Id: Id965cd89b16f3f4d8327f1ca3d7ba9ed146e7a44 Reviewed-on: http://git.am.freescale.net:8181/37819 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-10fsl_qbman: hardcode mps field to 60Haiying Wang
In LNI shaper setup, setting mps to 60 to round up the frame length to 60 for shaper calculations, for any dequeued frame length less than 60 bytes. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Change-Id: I88013d2ee39b3620a4e97f3366a87664ec0ea9dc Reviewed-on: http://git.am.freescale.net:8181/37437 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Roy Pledge <roy.pledge@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-06-10drivers: usb: gadget: Correct NULL pointer checking in fsl gadgetNikhil Badola
Correct NULL pointer checking for endpoint descriptor before it gets dereferenced Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Change-Id: I449d00d49f2ae842aa256907021b95b7885ccaf5 Reviewed-on: http://git.am.freescale.net:8181/37641 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-06-09VFIO: Check for null pointer after mallocBharat Bhushan
Add the check whether malloc allocated memory successfully or not Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Change-Id: If306002aa8541cf76286b7b78d0027c3395672a6 Reviewed-on: http://git.am.freescale.net:8181/37576 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-06-05fsl_usdpaa: Ensure map name is initialized and clearedRoy Pledge
Make sure that map name is null terminated when a memory map is split and is cleared when a map is destroyed Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com> Change-Id: If779b54817b9c2d49d6e18106b333a51ca2b2dcf Reviewed-on: http://git.am.freescale.net:8181/37436 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-06-05spi: fsl-espi: Workaround for the deep sleep issue when boot from SPIHou Zhiqiang
On T1042D4RDB, system can't resume and warm reset to uboot prompt sometimes. Disable eSPI controller hardware before enter deep sleep, and enable it after resume. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Change-Id: I0f091890ef3e3219697ff7f5bbf4a02809e6e45b Reviewed-on: http://git.am.freescale.net:8181/37469 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-06-04arm: ls1021a: enable sleep and deep sleep for rev 2.0 siliconChenhui Zhao
On the rev 2.0 silicon of LS1021A, set the WFIL2EN bit in the SCFG_CLUSTERPMCR register to enable sleep and deep sleep. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: I0ec6933dc1805749d7e4a815f9049301dfcfb63e Reviewed-on: http://git.am.freescale.net:8181/37396 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-04crypto: caam - remove SEC pool channelAlex Porosanu
For improved performance in case of unbalanced flows, all FQs from SEC to cores were added into a pool channel. Adverse effects have been observed for e5500 platforms. This patch removes the creation and subsequent usage of the pool channel. Change-Id: I49dbb93bfede16985fa2ed451cde17e7c2658648 Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/37366 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mircea Pop <mircea.pop@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-06-04fsl_usdpaa: Fix mem_create behaviorAhmed Mansour
Remove check added in previous patch to disallow size zero to be passed from user space in dma_mem_create(). Size zero is deemed valid if the memory region is already created and a second user wishes to get a mapping to the existent memory. Corrected values copied back to the user to include the length of the memory and the flags. This is important to reflect a memory size correction when the user passes size zero. The user can check the new size using dma_mem_params() Added a warning message if the user attempts to map to an existing area in memory, but specifies a non-zero size that does not match the original memory mapping. In the future this case will trigger an error and the mapping will fail. Currently the behavior is to print a warning message and the kernel passes back to user space the corrected size. Signed-off-by: Ahmed Mansour <Ahmed.Mansour@freescale.com> Change-Id: Ib8535ada6f0fb616986bce3c52eae65f3bf583da Reviewed-on: http://git.am.freescale.net:8181/37365 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Haiying Wang <Haiying.Wang@freescale.com> Reviewed-by: Roy Pledge <roy.pledge@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-06-03ls1021a: dts: Add eTSEC info for 2nd interrupt groupsClaudiu Manoil
Enable support for the second interrupt group register block and the corresponding Rx/Tx/Err interrupt sources, for each eTSEC node. Fix following non-critical issues and inconsistencies: - eTSEC can support 8 H/W queues, show this in the device tree; - remove "fsl,[r|t]x-bit-map" properties, they are obsoleted; - register block size is 0x1000 (4kB memory page), not 0x8000; - reg property has 2 "address" and resp. 2 "size" cells, not 1; - use register block address as queue-group id for consistency; Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Change-Id: Iada02221d1f3e06cc019a7b067c9b676c7c0b77d Reviewed-on: http://git.am.freescale.net:8181/37273 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-03powerpc/fsl_lbc: removal of dead codeRaghav Dogra
The condition check was not used Signed-off-by: Raghav Dogra <raghav@freescale.com> Change-Id: I82ee7f37db81bb198765857f8fa924d1c633fcc6 Reviewed-on: http://git.am.freescale.net:8181/37262 Reviewed-by: Prabhakar Kushwaha <prabhakar@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-06-01Merge branch 'qoriq-sdk' into LS1-SDK-Rev2.0jason
2015-06-01clk: fix type cast warningLijun Pan
Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> Change-Id: Ife4ad017add52bdd911b373d5d8dbb55a7e680ec Reviewed-on: http://git.am.freescale.net:8181/37122 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
2015-06-01crypto: caam - fix size_t print formatHoria Geantă
ARRAY_SIZE() returns a size_t value. Thus, when printing these values, %zu or %zx must be used, or else warnings show up: CC drivers/crypto/caam//caamalg.o In file included from include/linux/thread_info.h:11:0, from include/linux/preempt.h:9, from include/linux/spinlock.h:50, from include/linux/seqlock.h:35, from include/linux/time.h:5, from include/linux/stat.h:18, from include/linux/module.h:10, from drivers/crypto/caam//compat.h:9, from drivers/crypto/caam//caamalg.c:47: drivers/crypto/caam//caamalg.c: In function 'caam_cra_init': include/linux/bug.h:33:45: warning: format '%d' expects argument of type 'int', but argument 4 has type 'long unsigned int' [-Wformat=] #define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:-!!(e); })) ^ include/linux/compiler-gcc.h:47:28: note: in expansion of macro 'BUILD_BUG_ON_ZERO' #define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0])) ^ include/linux/kernel.h:41:59: note: in expansion of macro '__must_be_array' #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr)) ^ drivers/crypto/caam//caamalg.c:4396:13: note: in expansion of macro 'ARRAY_SIZE' op_id, ARRAY_SIZE(digest_size)); ^ CC drivers/crypto/caam//caamhash.o In file included from include/linux/thread_info.h:11:0, from include/linux/preempt.h:9, from include/linux/spinlock.h:50, from include/linux/seqlock.h:35, from include/linux/time.h:5, from include/linux/stat.h:18, from include/linux/module.h:10, from drivers/crypto/caam//compat.h:9, from drivers/crypto/caam//caamhash.c:56: drivers/crypto/caam//caamhash.c: In function 'caam_hash_cra_init': include/linux/bug.h:33:45: warning: format '%d' expects argument of type 'int', but argument 4 has type 'long unsigned int' [-Wformat=] #define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:-!!(e); })) ^ include/linux/compiler-gcc.h:47:28: note: in expansion of macro 'BUILD_BUG_ON_ZERO' #define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0])) ^ include/linux/kernel.h:41:59: note: in expansion of macro '__must_be_array' #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr)) ^ drivers/crypto/caam//caamhash.c:1782:12: note: in expansion of macro 'ARRAY_SIZE' op_id, ARRAY_SIZE(runninglen)); ^ Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Change-Id: Ica005a337d654f7d55eea6f5e5aee911cbd016b2 Reviewed-on: http://git.am.freescale.net:8181/37071 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tudor-Dan Ambarus <tudor.ambarus@freescale.com> Reviewed-by: Honghua Yin <Hong-Hua.Yin@freescale.com>
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