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Including: P3041DS P5020DS P5040DS B4QDS
The kernel config for this device is CONFIG_SENSORS_INA2XX.
Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
(cherry picked from commit bb192142c33657ec9f2e667878766031514829db)
Signed-off-by: Matthew Weigel <Matthew.Weigel@freescale.com>
Conflicts:
arch/powerpc/boot/dts/b4qds.dtsi
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MSI_LS1021A_DATA that is used to generate MSI interrupt by PCI
device is a little endian value. It should be converted to big
endian when writing to SCFG_SPIMSICLRCR a big endian register.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Change-Id: Ie26dd7320f54ee7410d29cca38f4218044549307
Reviewed-on: http://git.am.freescale.net:8181/23098
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Including: T1040RDB T1042RDB T208xQDS T208xRDB B4QDS T4240QDS
For T208xRDB and T4240QDS, ADT7481 is used. But kernel now only supports
ADT7461. So for now ADT7481 is treated as ADT7461.
The kernel config for thermal monitor is CONFIG_SENSORS_LM90.
Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
Change-Id: Ifae889c238fd53e0abc3b75516e484f1ccf6e659
Reviewed-on: http://git.am.freescale.net:8181/23080
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Yuantian Tang <yuantian.tang@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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Support PTPd 1588 stack by adding PTP 1588 clock
using the dTSEC
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Change-Id: I4f6fb9a721cede75c6cf23560014b55b46c84fef
Reviewed-on: http://git.am.freescale.net:8181/20295
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Support for FSL_FMAN_CPC_STASH option was partially implemented.
The FMAN operation mapping didn't allow support for write transaction
stashing. Write transaction stashing support is required in certain
data path intensive tasks. Without this support "FMAN writes" to DDR
take more time complete, with this option FMAN transactions are stashed
to CPC. Stashing reduces the overall completion time for FMAN transactions.
This in turn prevents buffer over run issues in FMAN. Without this support
it has been observed, while handling high traffic rate FMAN starts reporting
Rx errors.
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Change-Id: Iae7b2e9108204e64d336feb39517f4c72235feb4
Reviewed-on: http://git.am.freescale.net:8181/21040
Reviewed-by: Vakul Garg <vakul@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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LNI shaper is disabled by setting all 1's to both CR/ER
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: I7b680ecbcfcfa41860dddcca34044116719cda08
Reviewed-on: http://git.am.freescale.net:8181/22075
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Pass device-tree usb node offset to each usb device structure.
This is required by rcpm driver to get mask setting for
ip exception register to make/remove usb as wake-up source
for sleep/deep-sleep
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Change-Id: I4e6b0f931fb29a6311b36a97255d994c2ce0ad05
Reviewed-on: http://git.am.freescale.net:8181/22478
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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Some functions are powerpc specific which cause error when the
driver is used on ARM platforms.
Added micro to make them only be used on powerpc platforms.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Change-Id: I7ab009fa13f47e23d67aef875185a23882dd1813
Reviewed-on: http://git.am.freescale.net:8181/23070
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
(cherry picked from commit 44a0893a220ef1906359aa283837fba8b18e20f7)
Signed-off-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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The hardware can automatically generate pause frames when the number
of free buffers drops under a certain threshold, but in order to do this,
the address of the last free buffer needs to be written to a specific
register for each RX queue.
This has to be done in 'gfar_clean_rx_ring' which is called for each
RX queue. In order not to impact performance, by adding a register write
for each incoming packet, this operation is done only when the PAUSE frame
transmission is enabled.
Whenever the link is readjusted, this capability is turned on or off.
Change-Id Ib4751d205a00c0813355cf23c4428bf6dcbda003
Signed-off-by: Matei Pavaluca <matei.pavaluca@freescale.com>
Change-Id: I22a836b86f256128ea1bd39e87902321030f7742
Reviewed-on: http://git.am.freescale.net:8181/23138
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
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Local flow control options needed in order to resolve the negotiation
are incorrectly calculated.
Previously 'mii_advertise_flowctrl' was called to determine the local advertising
options, but these were determined based on FLOW_CTRL_RX/TX flags which are
never set through ethtool.
The patch simply translates from ethtool flow options to mii flow options.
Change-Id: I3ed7801eecaa6b5b8501ba1c8e860c92f959d559
Signed-off-by: Pavaluca Matei <matei.pavaluca@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/23137
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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The phy device supports 802.3x flow control, but the specific flags are not set
in the phy initialisation code. Flow control flags need to be added to the
supported capabilities of the phydev by the driver.
This is needed in order for ethtool to work ('ethtool -A' code checks for these
flags)
Change-Id: I71d8411a82777aff36bf98a09097eef1935ff113
Signed-off-by: Pavaluca Matei <matei.pavaluca@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/23136
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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CONFIG_MEMORY is required for IFC
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Change-Id: I6605a908a4ee2bd0e8ef5b4f81456ee697138c63
Reviewed-on: http://git.am.freescale.net:8181/22565
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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Define and use CONTROL_REGISTER_W1C_MASK to make sure that
w1c bits of usb control register do not get reset while
writing any other bit
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Change-Id: Ie56814b6f6c4d05fbf862619330d2e505438e1c7
Reviewed-on: http://git.am.freescale.net:8181/22464
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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Change string format for errata property in USB node that is
checked in device tree for applicablilty of corresponding erratum
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Change-Id: Ic07fa5b5a8ce93ac3845332f23b3b71338956266
Reviewed-on: http://git.am.freescale.net:8181/22463
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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The original u32 define limited the ceetm shaping speed.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: I02fe21c541e5c78151b181b8ab75cc84d019661d
Reviewed-on: http://git.am.freescale.net:8181/22074
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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which has 8KB CCSR memory space instead of 4KB on QMan rev1.
Change back 4KB CCSR memory space for QMan rev1 and rev2, then
update soc *-post device trees for those SoCs which have QMan v3.
Change-Id: I5878c1b87430c5f7f6f098399d7d55202109adcf
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/22072
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Ensure that idle line is asserted before leaving suspend function.
If not, fail the request as system could hang waiting for idle line
to be asserted which might never happen.
Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Change-Id: I95390751160b8825d58d9c04a6884b37e91424b4
Reviewed-on: http://git.am.freescale.net:8181/21956
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Reviewed-by: Haiying Wang <Haiying.Wang@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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It is really only wanting to duplicate a check which is already done by the
cgroup subsystem.
With this patch, user jdoe still cannot move pid 1 into a devices cgroup
he owns, but now he can move his own other tasks into devices cgroups.
Signed-off-by: Serge Hallyn <serge.hallyn@ubuntu.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Cc: Aristeu Rozanski <aris@redhat.com>
(cherry picked from commit 73ba353471e0b692f398f3d63018b7f46ccf1d3e)
Change-Id: I34af7b6399d1219cfdaf41746685bf9955e47dd7
Reviewed-on: http://git.am.freescale.net:8181/21804
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mihai Caraman <mihai.caraman@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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mpc85xx_pmc_set_wake() is only for powerpc platform. For LS1 platform,
no such function. Use a weak function definition to void compile
problem.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Change-Id: I84ab02a65addabd2f8d7a9681e5f80c7b06c5ad0
Reviewed-on: http://git.am.freescale.net:8181/22821
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
---
upstream link of the patch:
http://patchwork.ozlabs.org/patch/400406/
Change-Id: I55e42d2515bcd35d0bc5198cb13d5ed91850b50e
Reviewed-on: http://git.am.freescale.net:8181/22796
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This variable should represent the clock number per PLL.
So, rename it and re-calculate it.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Change-Id: I2817f76a076d468073a870edc47e41ef43ffa07f
Reviewed-on: http://git.am.freescale.net:8181/22795
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Remove qspi the second flash support for LS1 SDK.
The QSPI driver was back-ported from the upstream QSPI driver. The
upstream version does not support the reading/writing for the second
flash chip. This patch removed the second flash support to avoid error information during kernel bringup.
Signed-off-by: Chao Fu <B44548@freescale.com>
Change-Id: I57b02083ebe8e9a34673243be74d8cfd1c80aa9d
Reviewed-on: http://git.am.freescale.net:8181/22587
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Added the compatible "simple-bus" to fix the problem.
Change-Id: I629a6f5c54f51dbe18c65c2ff8cdc6e97bb0ed0f
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/22481
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch only for LS1021A PCIe Power Managment, because there has
a PCIe hardware issue, we need a workaround to support it.
LS1021A Workaround for internal TKT228622 to fix the INTx hang issue.
If this hardware be fixed, we not need to do anything for PCIe PM.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Change-Id: I7b689e4780322f77bebd8671da71d82f6fdb18a3
Reviewed-on: http://git.am.freescale.net:8181/22585
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch adds Power Management support for SAI.
Activate regmap cache with REGCACHE_RBTREE, and use
regmap cache code to save and restore registers in
suspend and resume. The Transmit Control Register
(TCSR) and Receive Control Register(RCSR) should
be volatile registers.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
---
This patch has been sent to upstream for review:
https://patchwork.kernel.org/patch/5183621/.
Change-Id: I46a53b91fa005d9833e289d06430e26569897b2d
Reviewed-on: http://git.am.freescale.net:8181/22361
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Commit 1fcf7ce0c602 (arm: kvm: implement CPU PM notifier) added
support for CPU power-management, using a cpu_notifier to re-init
KVM on a CPU that entered CPU idle.
The code assumed that a CPU entering idle would actually be powered
off, loosing its state entierely, and would then need to be
reinitialized. It turns out that this is not always the case, and
some HW performs CPU PM without actually killing the core. In this
case, we try to reinitialize KVM while it is still live. It ends up
badly, as reported by Andre Przywara (using a Calxeda Midway):
[ 3.663897] Kernel panic - not syncing: unexpected prefetch abort in Hyp mode at: 0x685760
[ 3.663897] unexpected data abort in Hyp mode at: 0xc067d150
[ 3.663897] unexpected HVC/SVC trap in Hyp mode at: 0xc0901dd0
The trick here is to detect if we've been through a full re-init or
not by looking at HVBAR (VBAR_EL2 on arm64). This involves
implementing the backend for __hyp_get_vectors in the main KVM HYP
code (rather small), and checking the return value against the
default one when the CPU notifier is called on CPU_PM_EXIT.
Reported-by: Andre Przywara <osp@andrep.de>
Tested-by: Andre Przywara <osp@andrep.de>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Rob Herring <rob.herring@linaro.org>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit b20c9f29c5c25921c6ad18b50d4b61e6d181c3cc)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I3f123215dfd2673e3abae201b6e75c11ac9cfe63
Reviewed-on: http://git.am.freescale.net:8181/22059
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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unmap_range() was utterly broken, to quote Marc, and broke in all sorts
of situations. It was also quite complicated to follow and didn't
follow the usual scheme of having a separate iterating function for each
level of page tables.
Address this by refactoring the code and introduce a pgd_clear()
function.
Reviewed-by: Jungseok Lee <jays.lee@samsung.com>
Reviewed-by: Mario Smarduch <m.smarduch@samsung.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 4f853a714bf16338ff5261128e6c7ae2569e9505)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I478878114142926836b4f6674c4a04cb94b23955
Reviewed-on: http://git.am.freescale.net:8181/22058
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch adds support for running Cortex-A7 guests on Cortex-A7 hosts.
As Cortex-A7 is architecturally compatible with A15, this patch is largely just
generalising existing code. Areas where 'implementation defined' behaviour
is identical for A7 and A15 is moved to allow it to be used by both cores.
The check to ensure that coprocessor register tables are sorted correctly is
also moved in to 'common' code to avoid each new cpu doing its own check
(and possibly forgetting to do so!)
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit e8c2d99f8277d68d28a9f99d16289712bc2aee7f)
Conflicts:
arch/arm/kvm/reset.c
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: Id420a5e767cb428dc5b9735673c87ef97322c8df
Reviewed-on: http://git.am.freescale.net:8181/22057
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Upon CPU shutdown and consequent warm-reboot, the hypervisor CPU state
must be re-initialized. This patch implements a CPU PM notifier that
upon warm-boot calls a KVM hook to reinitialize properly the hypervisor
state so that the CPU can be safely resumed.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
(cherry picked from commit 1fcf7ce0c60213994269fb59569ec161eb6e08d6)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I09e329449b8e5e767cdfec1000f2c8f82193a0b8
Reviewed-on: http://git.am.freescale.net:8181/22056
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The ARM architected timer driver doesn't compile without
GENERIC_CLOCKEVENTS selected, so ensure that we select it when building
for a platform that has the timer.
Without this patch, mach-virt fails to build without something like
mach-vexpress also selected.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit 0c403462d6822227ea37fb0293a3e9f511e6929f)
Change-Id: I349317968df072d8539702adcf376e4bea4b43cb
Reviewed-on: http://git.am.freescale.net:8181/22055
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: Ia801e4e9ee128b35a5ec0fad42c71e2b91e4e808
Reviewed-on: http://git.am.freescale.net:8181/22054
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The use of p*d_addr_end with stage-2 translation is slightly dodgy,
as the IPA is 40bits, while all the p*d_addr_end helpers are
taking an unsigned long (arm64 is fine with that as unligned long
is 64bit).
The fix is to introduce 64bit clean versions of the same helpers,
and use them in the stage-2 page table code.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit a3c8bd31af260a17d626514f636849ee1cd1f63e)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I1db223265c876a17edbc79777f59479f12bafa19
Reviewed-on: http://git.am.freescale.net:8181/22053
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The mach-virt machine is entirely specified by device tree.
However the kernel does not initialize the clocks from device tree
and it will refuse to probe the PL011 console.
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I5f90396a872f2db9a0164cd003babaf9b8efdcad
Reviewed-on: http://git.am.freescale.net:8181/22052
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Compiling with THP enabled leads to the following warning:
arch/arm/kvm/mmu.c: In function ‘unmap_range’:
arch/arm/kvm/mmu.c:177:39: warning: ‘pte’ may be used uninitialized in this function [-Wmaybe-uninitialized]
if (kvm_pmd_huge(*pmd) || page_empty(pte)) {
^
Code inspection reveals that these two cases are mutually exclusive,
so GCC is a bit overzealous here. Silence it anyway by initializing
pte to NULL and testing it later on.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 56041bf920d2937b7cadcb30cb206f0372eee814)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: Ie4c704ea6441c405cd409cc6a2b1e833936a2df4
Reviewed-on: http://git.am.freescale.net:8181/22051
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Now when the main kvm code relying on these defines has been moved to
the x86 specific part of the world, we can get rid of these.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
(cherry picked from commit ef0cfe71c2b1710cd4ae747537e36c56f9a26ccf)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I962079f2935ab652bedffc64f038e269bcd1986e
Reviewed-on: http://git.am.freescale.net:8181/22050
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The KVM_HPAGE_DEFINES are a little artificial on ARM, since the huge
page size is statically defined at compile time and there is only a
single huge page size.
Now when the main kvm code relying on these defines has been moved to
the x86 specific part of the world, we can get rid of these.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
(cherry picked from commit dc6f6763dfeaf2dfec906bb78875dcea162accd9)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I057413e3c7268842e6e12b0b158c1c498da0cb58
Reviewed-on: http://git.am.freescale.net:8181/22049
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Now when the main kvm code relying on these defines has been moved to
the x86 specific part of the world, we can get rid of these.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
(cherry picked from commit bbba7938d181bdd0b02a5fbbc7b7391b1d8f44e7)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I4350d56598097538f842c5022e9a56e2da9474d0
Reviewed-on: http://git.am.freescale.net:8181/22048
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Now when the main kvm code relying on these defines has been moved to
the x86 specific part of the world, we can get rid of these.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
(cherry picked from commit 015e0513a07467b34bb3a466ec5f5156765770dc)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I0d1857814eb76415cdee4cd843d7aad3e39741bf
Reviewed-on: http://git.am.freescale.net:8181/22047
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Now when the main kvm code relying on these defines has been moved to
the x86 specific part of the world, we can get rid of these.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
(cherry picked from commit 2c5350e934501f1af8010c608d8dbf72ad25fdc6)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: Ia80e905cb81e7c88e82b5efd64f5f81eb3f4aa83
Reviewed-on: http://git.am.freescale.net:8181/22046
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Now when the main kvm code relying on these defines has been moved to
the x86 specific part of the world, we can get rid of these.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
(cherry picked from commit a7efdf6bec34f1a693a926ebd08de6ba6e700dff)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: Ic5c8c659116031969bbf7912fd3b8eae00cb633f
Reviewed-on: http://git.am.freescale.net:8181/22045
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Support transparent huge pages in KVM/ARM and KVM/ARM64. The
transparent_hugepage_adjust is not very pretty, but this is also how
it's solved on x86 and seems to be simply an artifact on how THPs
behave. This should eventually be shared across architectures if
possible, but that can always be changed down the road.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 9b5fdb9781f74fb15827e465bfb5aa63211953c8)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I0a35b3b7cbb482b0fd8ad828c6db2a5e7b59869f
Reviewed-on: http://git.am.freescale.net:8181/22044
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Support huge pages in KVM/ARM and KVM/ARM64. The pud_huge checking on
the unmap path may feel a bit silly as the pud_huge check is always
defined to false, but the compiler should be smart about this.
Note: This deals only with VMAs marked as huge which are allocated by
users through hugetlbfs only. Transparent huge pages can only be
detected by looking at the underlying pages (or the page tables
themselves) and this patch so far simply maps these on a page-by-page
level in the Stage-2 page tables.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit ad361f093c1e31d0b43946210a32ab4ff5c49850)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I74ce26713f4720f8024692664ebfb14a364bd84d
Reviewed-on: http://git.am.freescale.net:8181/22043
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The gfn_to_index function relies on huge page defines which either may
not make sense on systems that don't support huge pages or are defined
in an unconvenient way for other architectures. Since this is
x86-specific, move the function to arch/x86/include/asm/kvm_host.h.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
(cherry picked from commit 6d9d41e57440e32a3400f37aa05ef7a1a09ced64)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: Iaf39a658cb1300b06dd59e1b84aa6f8c173cf948
Reviewed-on: http://git.am.freescale.net:8181/22042
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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KVM does not have a notion of multiple clusters for CPUs, just a linear
array of CPUs. When using a system with cores in more than one cluster, the
current method for calculating the virtual MPIDR will leak the (physical)
cluster information into the virtual MPIDR. One effect of this is that
Linux under KVM fails to boot multiple CPUs that aren't in the 0th cluster.
This patch does away with exposing the real MPIDR fields in favour of simply
using the virtual CPU number (but preserving the U bit, as before).
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 1158fca401e09665c440a9fe4fd4f131ee85c13b)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: Iaf8b973671e1ea2a203fb2d69c3c8aa9cafbf91f
Reviewed-on: http://git.am.freescale.net:8181/22041
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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To implement CPU=Host we have added KVM_ARM_PREFERRED_TARGET
vm ioctl which provides information to user space required for
creating VCPU matching underlying Host.
This patch adds info related to this new KVM_ARM_PREFERRED_TARGET
vm ioctl in the KVM API documentation.
Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 740edfc0a35dd688c97ae8907c4377df49219bf3)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I8f296cf1489e3095211137182ff457285671da8e
Reviewed-on: http://git.am.freescale.net:8181/22040
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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For implementing CPU=host, we need a mechanism for querying
preferred VCPU target type on underlying Host.
This patch implements KVM_ARM_PREFERRED_TARGET vm ioctl which
returns struct kvm_vcpu_init instance containing information
about preferred VCPU target type and target specific features
available for it.
Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 42c4e0c77ac91505ab94284b14025e3a0865c0a5)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: Iaace1d63c4bd6f66b7808f4b8e9201b8326ed4ee
Reviewed-on: http://git.am.freescale.net:8181/22039
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch implements kvm_vcpu_preferred_target() function for
KVM ARM64 which will help us implement KVM_ARM_PREFERRED_TARGET
ioctl for user space.
Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 473bdc0e6565ebb22455657a40daa21b6b4ee16b)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: If4340022e8f7f396eeb760c9f6c0aa46225e3315
Reviewed-on: http://git.am.freescale.net:8181/22038
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch implements kvm_vcpu_preferred_target() function for
KVM ARM which will help us implement KVM_ARM_PREFERRED_TARGET ioctl
for user space.
Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Pranavkumar Sawargaonkar <pranavkumar@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 4a6fee805d5e278e4733bf933cb5b184b7a8be1f)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I10beaa7f4275742c9f86ba957a7d70adcf5babb0
Reviewed-on: http://git.am.freescale.net:8181/22037
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The T{0,1}SZ fields of TTBCR are 3 bits wide when using the long descriptor
format. Likewise, the T0SZ field of the HTCR is 3-bits. KVM currently
defines TTBCR_T{0,1}SZ as 3, not 7.
The T0SZ mask is used to calculate the value for the HTCR, both to pick out
TTBCR.T0SZ and mask off the equivalent field in the HTCR during
read-modify-write. The incorrect mask size causes the (UNKNOWN) reset value
of HTCR.T0SZ to leak in to the calculated HTCR value. Linux will hang when
initializing KVM if HTCR's reset value has bit 2 set (sometimes the case on
A7/TC2)
Fixing T0SZ allows A7 cores to boot and T1SZ is also fixed for completeness.
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(cherry picked from commit 5e497046f005528464f9600a4ee04f49df713596)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: I1c5fc3e65d8821f50fab529ab1ff320cc10b9649
Reviewed-on: http://git.am.freescale.net:8181/22036
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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