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2011-05-16drm/nouveau: Associate memtimings with performance levels on cards <= nv98Martin Peres
v2 (Ben Skeggs): fix ramcfg strap, and remove bogus handling of perf 0x40 Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nva3/pm: initial pass at set_clock() hookBen Skeggs
I still discourage anyone from actually doing this yet. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nvc0/gr: calculate some more of our magic numbersBen Skeggs
Again, doesn't quite match NVIDIA's, but not sure it really matters. This will however, match the same rules we use to calculate the other related grctx magics. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nv50: respect LVDS link count from EDID on SPWG panelsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: recognise DCB connector type 0x41 as LVDSBen Skeggs
After looking at a number of different logs, it appears 0x41 likely indicates the presense of an LVDS panel following the SPWG spec (http://www.spwg.org/) Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: fix uninitialised variable warningBen Skeggs
Looks like a false positive to me, but, anyways! Reported-by: Jimmy Rentz <jb17bsome@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: Fix a crash at card takedown for NV40 and older cardsJimmy Rentz
NV40 and older cards (pre NV50) reserve a vram bo for the vga memory at card init. This bo is then freed at card shutdown. The problem is that the ttm bo vram manager was already freed. So a crash occurs when the vga bo is freed. The fix is to free the vga bo prior to freeing the ttm bo vram manager. There might be other solutions but this seemed the simplest to me. Signed-off-by: Jimmy Rentz <jb17bsome@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: Free nv04 instmem ramin heap at card takedownJimmy Rentz
Add a missing nv04 instmem ramin heap shutdown call. Signed-off-by: Jimmy Rentz <jb17bsome@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nva3: somewhat improve clock reportingBen Skeggs
Definitely not 100% correct, but, for the configurations I've seen used it'll read back the correct clocks now. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: pull refclk from vbios on limits 0x40 boardsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nv40/gr: oops, fix random bits getting set in engine objBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nv50: improve nv50_pm_get_clock()Emil Velikov
Many of the nv50 cards have their shader and/or memory pll disabled at some stage. This patch addresses those cases, so that the function returns the correct frequency. When the shader pll is disabled, the blob reports 2*core clock Whereas for memory, the data stored in the vbios. This action is incorrect as some vbioses store a clock value that is less than the refference clock of the pll. Thus we are reporting the reff_clk as it is the frequency the pll actually operates v2 - Convert NV_INFO() messages to NV_DEBUG() Provide more information in the actuall message Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau/pm: fix compilation failure when CONFIG_POWER_SUPPLY is not setMartin Peres
Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr> Reported-by: Stratos Psomadakis <psomas@ece.ntua.gr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nvc0/fifo: stick user area into a gpuobj rather than a boBen Skeggs
Contents will now be preserved across a suspend, unlike a pinned bo Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nvc0/gr: no need to store context in graph_fini()Ben Skeggs
PFIFO kickoff should have handled this for us. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nvc0/fifo: restore context table on resumeBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nvc0/fifo: kick channels off during suspendBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nvc0/gr: better handling of fuc firmwareBen Skeggs
Allows per-chipset firmware to be installed, and keeps a copy in memory for suspend/resume purposes. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nv50: support PMPEG on original nv50Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nv50: rename nv84_mpeg to nv50_mpegBen Skeggs
In preparation for adding 0x50 support. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nv84: add support for PMPEGBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nv40/vpe: add support for PMPEGBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nvc0: implement support for copy enginesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nva3: implement support for copy engineBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: remove remnants of nouveau_pgraph_engineBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: fix suspend failure path to reinitialise all enginesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: remove remnants of nouveau_pgraph_engine from nouveau_channelBen Skeggs
The nouveau_wait_for_idle() call should hopefully not have been actually necessary, we *do* wait for the channel to go idle already. If it's an issue somehow, the chipset-specific hooks can wait for idle themselves before taking the lock. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: move set_tile_region to nouveau_exec_engineBen Skeggs
In the very least VPE (PMPEG and friends) also has this style of tile region regs, lets make them just work if/when they get added. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nv04/gr: move to exec engine interfacesBen Skeggs
Like nv10-nv50, needs cleanup. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nv10/gr: move to exec engine interfacesBen Skeggs
Like nv20-nv50, needs cleanup. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nv20-nv30/gr: move to exec engine interfaceBen Skeggs
A bit of cleanup done along the way, but, like nv40/nv50, needs more. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nv40/gr: move to exec engine interfacesBen Skeggs
Like nv50, this needs a good cleanup. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nvc0/gr: move to exec engine interfacesBen Skeggs
Much nicer to do that nv50, the code was pretty much written to expect such a change in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nv50/gr: move to exec engine interfacesBen Skeggs
This needs a massive cleanup, but to catch bugs from the interface changes vs the engine code cleanup, this will be done later. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: working towards a common way to represent enginesBen Skeggs
There's lots of more-or-less independant engines present on NVIDIA GPUs these days, and we generally want to perform the same operations on them. Implementing new ones requires hooking into lots of different places, the aim of this work is to make this simpler and cleaner. NV84:NV98 PCRYPT moved over as a test. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: remove some unused members from dev_privBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: move engine object creation into per-engine hooksBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: use static vidshift of 2 on volt 0x30 tablesBen Skeggs
Explanation is in the commit. If anyone has an example of where this is *not* the case, please report it! Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: improve memtiming table parsingRoy Spliet
Improves the parsing of the memory timing table on NV50-NV98revA1 chipsets. Added stepping to drm_nouveau_private to make sure newer NV98 (105M) is zero rather than incorrect. Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nvc0: decode gpc/hubclient on vm faultBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nvc0: more vm fault reasonsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nvc0: more vm fault enginesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16drm/nouveau: Fix missing whitespace checkpatch.pl errors.Emil Velikov
This patch fixes messages such as ERROR: space required after that ',' ERROR: spaces required around that '=' Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net>
2011-05-16drm/nouveau: Fix brace placement checkpatch.pl errors.Emil Velikov
Fix 'ERROR: that open brace { should be on the previous line' Fix 'ERROR: else should follow close brace }' Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net>
2011-05-16drm/nouveau: Clean up trailing whitespace and C99-style comments.Emil Velikov
Fix 'ERROR: trailing whitespace', Fix 'ERROR: do not use C99 // comments' Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net>
2011-05-16drm/nouveau: Fix indentation-related checkpatch.pl error messages.Emil Velikov
Fix 'ERROR: code indent should use tabs where possible' Fix 'ERROR: space required before the open parenthesis (' Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Francisco Jerez <currojerez@riseup.net>
2011-05-16drm/nouveau: name the boot perflvl "boot"Martin Peres
Signed-off-by: Martin Peres <martin.peres@ensi-bourges.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2011-05-16Merge remote branch 'keithp/drm-intel-next' of /ssd/git/drm-next into ↵Dave Airlie
drm-core-next * 'keithp/drm-intel-next' of /ssd/git/drm-next: (301 commits) drm/i915: split PCH clock gating init drm/i915: add Ivybridge clock gating init function drm/i915: Update the location of the ringbuffers' HWS_PGA registers for IVB. drm/i915: Add support for fence registers on Ivybridge. drm/i915: Use existing function instead of open-coding fence reg clear. drm/i915: split clock gating init into per-chipset functions drm/i915: set IBX pch type explicitly drm/i915: add Ivy Bridge PCI IDs and driver feature structs drm/i915: add PantherPoint PCH ID agp/intel: add Ivy Bridge support drm/i915: ring support for Ivy Bridge drm/i915: page flip support for Ivy Bridge drm/i915: interrupt & vblank support for Ivy Bridge drm/i915: treat Ivy Bridge watermarks like Sandy Bridge drm/i915: manual FDI training for Ivy Bridge drm/i915: add swizzle/tiling support for Ivy Bridge drm/i915: Ivy Bridge has split display and pipe control drm/i915: add IS_IVYBRIDGE macro for checks drm/i915: add IS_GEN7 macro to cover Ivy Bridge and later drm/i915: split enable/disable vblank code into chipset specific functions ...
2011-05-14drm/i915: split PCH clock gating initJesse Barnes
Ibex Peak and CougarPoint already require a different setting (added here), and future chips will likely follow that precedent. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-14drm/i915: add Ivybridge clock gating init functionJesse Barnes
Some of the bits have changed, including one we were setting that enables a VGA test mode, preventing pipe B from working at all. So add a new IVB specific function with the right bits. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Keith Packard <keithp@keithp.com> Signed-off-by: Keith Packard <keithp@keithp.com>
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