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The FIXME and NOTE have already been fixed (we have FAST_READ support).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Sourav Poddar <sourav.poddar@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
(cherry picked from commit 1a874e91018ea99d7f012a0824669aa9ed833d6f)
Change-Id: I02d75e34033100678d65466628217bd493e82135
Reviewed-on: http://git.am.freescale.net:8181/20034
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add a struct pcie_host_ops .get_msi_data() method for platforms to return
their special MSI message data.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=next&id=24832b4de315ad00e5430a53772750dfcf18514d
Change-Id: Iecbb0f94a4f04eb96e6a1c2a8d9c3768a1aa11bf
Reviewed-on: http://git.am.freescale.net:8181/19710
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The struct pcie_host_ops .get_msi_data() method returns the MSI message
address. To accurately express its purpose, rename it to .get_msi_addr().
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=next&id=450e344e421b9f555261a2d97952d9e71d4cb082
Change-Id: I34a975f242addd70a7c7682e9e867b1414137d12
Reviewed-on: http://git.am.freescale.net:8181/19709
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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End address should be equal to start_addr + size - 1. Fix PCI IO resource
end address calculation.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=next&id=0c61ea77cceafd1134225099961c2df0866b500f
Change-Id: I1c820af498f99bca3ea235f297182a6620fa7ee1
Reviewed-on: http://git.am.freescale.net:8181/19708
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The code has calculated cfg0_base and cfg1_base when parsing 'reg' or
'ranges' property of PCI DTS node, so remove duplicate calculation. When
using 'reg', resource cfg is not used, so this code computed an incorrect
configuration base.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=next&id=ec98e9ab6f2475ff57c12d069e78b90548c0f60e
Change-Id: Iac12f15871759879a572b77c0f1e44fd50e0bd4f
Reviewed-on: http://git.am.freescale.net:8181/19707
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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"msi_attrib.pos" is only used for MSI (not MSI-X), and we already cache the
MSI capability offset in "dev->msi_cap".
Remove "pos" from the struct msi_attrib and use "dev->msi_cap" directly.
[bhelgaas: changelog, fix whitespace]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The patch is part of:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=next&id=d591f2eeaf13bc6759069f14b6bf1b1ada116774
Change-Id: Ib04e9b6db0c44b4d8e003fadd25e2f14e071c39c
Reviewed-on: http://git.am.freescale.net:8181/19706
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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of_get_address() expects pointers in the third and fourth parameters.
Pass NULL in order to fix the following sparse warnings:
drivers/pci/host/pcie-designware.c:433:51: warning: Using plain integer as NULL pointer
drivers/pci/host/pcie-designware.c:433:58: warning: Using plain integer as NULL pointer
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Jingoo Han <jg1.han@samsung.com>
The patch comes from
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=next&id=9f0dbe087bff6cfffcf8b0c25c08891d66b987be
Change-Id: I5c034c7ceeb951b308fb2dcb82d6a191db94c935
Reviewed-on: http://git.am.freescale.net:8181/19705
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The struct pcie_port_info doesn't contain any exclusive information
compared to other elements of struct pcie_port. So, keeping a separate
structure does not seem very logical. Therefore remove this struct and
embed its elements directly into struct pcie_port.
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=next&id=adf70fc087b1750c3792cd56abc6a45e49bb3a11
Change-Id: I2f67951e1c7fb3f29477a2889b7ae468071dd1f1
Reviewed-on: http://git.am.freescale.net:8181/19704
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The driver had checks for this sprinkled all over. As we call
sys_to_pcie() before every instance of this check, we can move the
check to this single location to make things clear.
Removing the statements after BUG[_ON]() is safe as the kernel is halted at
this point anyway.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=next&id=84a263f39403ca3b399af77499876e02e634b00b
Change-Id: I79866011d82e6b12daaef6464bdf79c5adccc0ca
Reviewed-on: http://git.am.freescale.net:8181/19703
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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dw_pcie_host_init()
The pci_common_init_dev() call right before will already handle the device
resource allocation, so this call was a no-op.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=next&id=8ddebc4103e6544bd31f0c97e55491387717a124
Change-Id: I99d25006888b16545605bf87ee33c394c22e2f55
Reviewed-on: http://git.am.freescale.net:8181/19702
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Use pci_create_root_bus() similar to other PCI host controller drivers.
The main problem with pci_scan_root_bus() is that it not only creates the
root bus, but also activates all devices on the bus. This triggers PCI
device driver probe routines, which fail because resources haven't been
allocated.
To work around this we made sure that the host controller driver is probed
early and finishes resource allocation before any other device drivers are
registered. Switching to pci_create_root_bus() allows us to get rid of
this special handling.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=next&id=92483df2bad7649caacad60ec7b0f8016e894e11
Change-Id: I7cd41d6390b2586b0f319c5ad4e844454776bf32
Reviewed-on: http://git.am.freescale.net:8181/19701
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This allows to explicitly specify the covered bus numbers in the
devicetree, which will come in handy once we see a SoC with more than one
PCIe host controller instance.
Previously the driver relied on the behavior of pci_scan_root_bus() to fill
in a range of 0x00-0xff if no valid range was found. We fall back to the
same range if no valid DT entry was found to keep backwards compatibility,
but now do it explicitly.
[bhelgaas: use %pR in error message to avoid duplication]
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
The patch is part of:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=next&id=4f2ebe00597c44f7dc6f88a052a2981ddcf6a0b6
Change-Id: Ib2a849e0d1399b16eaafccfdb2c77e6d4fc916bc
Reviewed-on: http://git.am.freescale.net:8181/19700
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The Keystone PCI controller is based on v3.65 DesignWare hardware. This
version differs from newer versions of the hardware in functional areas
discussed below that make it necessary to change dw_pcie_host_init() to
support v3.65 based PCI controller.
1. No support for ATU port. Any ATU-specific resource handling code is
to be bypassed for v3.65 h/w.
2. MSI controller uses application space to implement MSI and 32 MSI
interrupts are multiplexed over 8 IRQs to the host. Hence the code
to process MSI IRQ needs to be different. This patch allows
platform driver to provide its own irq_domain_ops ptr to
irq_domain_add_linear() through an API callback from the DesignWare
core driver.
3. MSI interrupt generation requires EP to write to the RC's
application register. So enhance the driver to allow setup of
inbound access to MSI IRQ register as a post scan bus API callback.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
CC: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Jingoo Han <jg1.han@samsung.com>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=next&id=b14a3d1784a9252aa3bbe0bb9d14588be32f18a1
Change-Id: I077e4084dd1148bb40ea006cf06f26619f3bf639
Reviewed-on: http://git.am.freescale.net:8181/19699
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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DesignWare v3.65 hardware implements MSI controller registers in
application space. This requires updates to the DesignWare core to
support controllers based on this older hardware.
Add msi_irq_set()/clear() interfaces to allow Set/Clear MSI IRQ enable bit
in the application register. Also, v3.65 hardware uses the MSI_IRQ
register in application register space to raise MSI IRQ to the RC from EP.
Current code uses the standard mechanism as per PCI spec. So add
get_msi_data() to get the address of this register so common code can
work on both v3.65 and newer hardware.
[bhelgaas: changelog]
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=2f37c5a81cff2c341fa19fdd132ece6aea30a735
Change-Id: I5c235d4cd8727dd1bbac51278a132dd1463b77a3
Reviewed-on: http://git.am.freescale.net:8181/19698
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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DesignWare v3.65 hardware requires application space registers to be
configured to access the remote EP config space.
To support this, add rd_other_conf() and wr_other_conf() to pcie_host_ops.
[bhelgaas: changelog]
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=a1c0ae9c24627a12c781ebd9947a6442861f6168
Change-Id: I067670dda92d175b15034146c5e6269c74aeb0aa
Reviewed-on: http://git.am.freescale.net:8181/19697
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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In DRA7, the CPU sees 32-bit addresses, but the PCIe controller can see
only 28-bit addresses. So whenever the CPU issues a read/write request,
the 4 most significant bits are used by L3 to determine the target
controller. For example, the CPU reserves [mem 0x20000000-0x2fffffff]
for the PCIe controller but the PCIe controller will see only
[0x00000000-0x0fffffff]. For programming the outbound translation
window the *base* should be programmed as 0x00000000. Whenever we try to
write to, e.g., 0x20000000, it will be translated to whatever we have
programmed in the translation window with base as 0x00000000.
This is needed when the dt node is modelled something like this:
axi {
compatible = "simple-bus";
#size-cells = <1>;
#address-cells = <1>;
ranges = <0x0 0x20000000 0x10000000 // 28-bit bus
0x51000000 0x51000000 0x3000>;
pcie@51000000 {
reg = <0x1000 0x2000>, <0x51002000 0x14c>, <0x51000000 0x2000>;
reg-names = "config", "ti_conf", "rc_dbics";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x03000 0 0x00010000
0x82000000 0 0x20013000 0x13000 0 0xffed000>;
};
};
Here the CPU address for configuration space is 0x20013000 and the
controller address for configuration space is 0x13000. The controller
address should be used while programming the ATU (in order for translation
to happen properly in DRA7xx).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=f4c55c5a3f7f68c06cc559ed7af8b2d017cbb0a7
Change-Id: I4868d44de5bfd1eb81a1a54ce5ba62ef1068887a
Reviewed-on: http://git.am.freescale.net:8181/19696
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address space
in the designware driver.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
The patch is part of:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=4dd964df36d0e548e1806ec2ec275b62d4dc46e8
Change-Id: Ie78a1c43233c789a746801f9e49651a102d45936
Reviewed-on: http://git.am.freescale.net:8181/19695
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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On i.MX6 the host controller MSI IRQ is shared with PCI legacy INTD. Make
sure we don't bail too early from the IRQ handler.
The issue is fairly theoretical as it would require a system setup with a
PCIe switch where one connected device is using legacy INTD and another one
using MSI, but better fix it now.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Richard Zhu <r65037@freescale.com>
The patch is part of:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=7f4f16eef5aeba31bdfb7702ced06a42f2777e04
Change-Id: Ief02f9b15fa69316a067154dfcd727148687af9c
Reviewed-on: http://git.am.freescale.net:8181/19694
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Serialization of configuration accesses is provided by 'pci_lock' in
drivers/pci/access.c thus making the driver's 'conf_lock' superfluous.
Signed-off-by: Andrew Murray <amurray@embedded-bits.co.uk>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Richard Zhu <r65037@freescale.com>
The patch is part of:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=11c6fbd8d982617996fbc39097a84092eb6e8005
Change-Id: I6e879fc331aafd62d231ac0abb97ac5f0c535f09
Reviewed-on: http://git.am.freescale.net:8181/19693
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Use new OF interrupt mapping (of_irq_parse_and_map_pci()) when possible.
This is the recommended method of doing the IRQ mapping. For old
devicetrees we fall back to the previous practice.
This makes INTB, INTC, and INTD work on i.MX.
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jingoo Han <jg1.han@samsung.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=f86b3e392780050e5907f1c0f3cb6c4cc05fd6bb
Change-Id: Ic2bb7c8d649a867fe39f03ecff5c589dfbda93e8
Reviewed-on: http://git.am.freescale.net:8181/19692
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Corrects comment for setting number of lanes.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=66c5c34bf80c28d370eb9bcf30153ea0304a288a
Change-Id: I7e20ddc2d977de0fb9eb29d3f4ba6163077aabcf
Reviewed-on: http://git.am.freescale.net:8181/19691
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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There is no reason to care about irq_desc in that context, escpecially
as irq_data for that interrupt is retrieved as well.
Use the proper accessor for the msi descriptor
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: pci <linux-pci@vger.kernel.org>
Link: http://lkml.kernel.org/r/20140223212736.987803648@linutronix.de
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=f7bfca6db60a6ca0a73126918b2fb6f851065947
Change-Id: Iccd04b791032d0e48d4907f11e2274b3eaa0131d
Reviewed-on: http://git.am.freescale.net:8181/19690
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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pp->io_base, which is the input of the outbound IO address translation
unit, should be the CPU address. It was incorrectly programmed to the
realio address.
We should pass global_io_offset rather than sys->io_offset to
pci_ioremap_io(), so we map the new window into the first available spot in
the Linux view of the I/O space.
We must also pass CPU address instead of realio address to pci_ioremap_io().
This patch fixes above issue. It has been tested with Lecroy PTC in AIC
mode and Pericom PI7C9X2G303EL PCIe switch, which does not work otherwise.
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=fce8591f73c6a30c231f220d1092362aae0b985c
Change-Id: I32d0d6f638c4d9f27eea11a2f9df377c6d31ab2d
Reviewed-on: http://git.am.freescale.net:8181/19688
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The cfg_read/write functions are DesignWare-specific. Add dw_pcie prefix
to avoid collision in global name space.
Tested-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
The patch is part of:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=a01ef59e131b78b0fa7af235ea958bd17e5e86ca
Change-Id: I3562a37f35993bf4428bd092d6de11e60ebc2906
Reviewed-on: http://git.am.freescale.net:8181/19687
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The interrupts were cleared after the IRQ handler was called. This means
that new interrupts that occur after the handler handled the previous IRQ
but before the interrupt is cleared will be missed.
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Matthias Mann <m.mann@arkona-technologies.de>
Signed-off-by: Harro Haan <hrhaan@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Richard Zhu <hong-xing.zhu@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Juergen Beisert <jbe@pengutronix.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Siva Reddy Kallam <siva.kallam@samsung.com>
Cc: Srikanth T Shivanand <ts.srikanth@samsung.com>
Cc: Sean Cross <xobs@kosagi.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=ca1658921b63e5771423603367c5bee528acc977
Change-Id: I9f23d8e1d96d1e580d3efa43b755d9a79103217c
Reviewed-on: http://git.am.freescale.net:8181/19686
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
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It's conventional to use "for" rather than "while" for simple iteration.
No functional change.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=0b8cfb6aa3aabc96177b1e68ef13d2eb5c686606
Change-Id: Idc9f17b671cd3798ea8976f61a4574f556e93141
Reviewed-on: http://git.am.freescale.net:8181/19685
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
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write_msi_msg() does exactly the same so there is no need to explicitly
call pci_write_config_word() and do the same twice.
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Bjørn Erik Nilsen <ben@datarespons.no>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Jingoo Han <jg1.han@samsung.com>
The patch comes from
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=64989e7399f09b72689e25fb40f2d0d5e073b13a
Change-Id: Iae9f87518a96114d4c64d9c925f252a8aeab9d14
Reviewed-on: http://git.am.freescale.net:8181/19684
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
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904d0e788993 ("PCI: designware: Add irq_create_mapping()") resulted in
pre-allocated irq descs. Problem was that in assign_irq() these descs were
explicitly allocated and hence also freed, resulting in a crash. We also
need to clear the entire irq range in teardown. With this commit the
teardown basically does exactly the opposite of what was done in setup.
The crash this fixes looks like:
Unable to handle kernel NULL pointer dereference at virtual address 00000020
PC is at dw_msi_teardown_irq+0x40/0x118
LR is at trace_hardirqs_on_caller+0xf4/0x1c0
Backtrace:
[<802c401c>] (dw_msi_teardown_irq+0x0/0x118) from [<802c1844>] (arch_teardown_msi_irq+0x3c/0x40)
[<802c1808>] (arch_teardown_msi_irq+0x0/0x40) from [<802c1a08>] (default_teardown_msi_irqs+0x68/0x84)
[<802c19a0>] (default_teardown_msi_irqs+0x0/0x84) from [<802c1a34>] (arch_teardown_msi_irqs+0x10/0x14)
[<802c1a24>] (arch_teardown_msi_irqs+0x0/0x14) from [<802c1ad0>] (free_msi_irqs+0x98/0x144)
[<802c1a38>] (free_msi_irqs+0x0/0x144) from [<802c2570>] (pci_disable_msi+0x48/0x60)
[<802c2528>] (pci_disable_msi+0x0/0x60) from [<7f0057d4>] (sxdma_irq_free+0x44/0x48 [sxdma])
[bhelgaas: add crash info]
Tested-by: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: Bjørn Erik Nilsen <ben@datarespons.no>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Jingoo Han <jg1.han@samsung.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=be3f48cb21c1ca4907a0822eea406c8dd4a73ddb
with changing code style to avoid checkpatch errors and warnings
Change-Id: Iea3c4fa303fa64a0a6f94a53b615725e83433b51
Reviewed-on: http://git.am.freescale.net:8181/19683
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Fix whitespace, capitalization, and spelling errors. No functional change.
I know "busses" is not an error, but "buses" was more common, so I used it
consistently.
Signed-off-by: Marta Rybczynska <rybczynska@gmail.com> (pci_reset_bridge_secondary_bus())
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
The patch is part of:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=f7625980f5820edd1a73536e1a03bcbc1f889fec
Change-Id: If74f035977847d4890ef2bd341d7db33765c0c58
Reviewed-on: http://git.am.freescale.net:8181/19682
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
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Without irq_create_mapping(), the correct IRQ number cannot be
provided. In this case, it makes problems such as NULL dereference.
Thus, irq_create_mapping() should be added for MSI.
Suggested-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=904d0e7889933fb48d921c998fd1cabb3a9d6635
Change-Id: I79a67a778cc2b1de70aef538786f37c83d31d0de
Reviewed-on: http://git.am.freescale.net:8181/19681
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The following variables and functions are used only in pcie-designware.c,
so make them static:
global_io_offset
dw_pcie_rd_own_conf()
dw_pcie_wr_own_conf()
dw_pcie_setup()
dw_pcie_scan_bus()
dw_pcie_map_irq()
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=73e408508bf6c76d8dc06f044f0e4703a1e27f14
Change-Id: If9e312b452807d927347d1b0044ec0251de01ab4
Reviewed-on: http://git.am.freescale.net:8181/19680
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
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Add header guards to prevent redundant inclusion.
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
The patch comes from:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=18edf4512cfa3e3662bdbdfc5f11c2eb20721734
Change-Id: I31f0750a64fdbc04a6f4716bac5e1a9d843cb020
Reviewed-on: http://git.am.freescale.net:8181/19679
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
|
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This patch adds support for Message Signaled Interrupt in the
Exynos PCIe driver using Synopsys designware PCIe core IP.
Signed-off-by: Siva Reddy Kallam <siva.kallam@samsung.com>
Signed-off-by: Srikanth T Shivanand <ts.srikanth@samsung.com>
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
The patch is part of:
https://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?id=f342d940ee0e3a2b5197fd4fbade1cb6bbc960b7
Change-Id: I38a751701499e994463b4bbbefa588bc24129f7b
Reviewed-on: http://git.am.freescale.net:8181/19678
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The patch addes of_irq_parse_and_map_pci() and related function
which will be used by Layerscape PCIe driver.
of_irq_parse_raw() and of_irq_parse_one() are copied from
Linux 3.17 drivers/of/irq.c.
The related commit ID include:
7dc2e1134a22dc242175d5321c0c9e97d16eb87b
2361613206e66ce59cc0e08efa8d98ec15b84ed1
624cfca534f9b1ffb1326617b4e973a3d5ecff4a
a9ecdc0fdc54aa499604dbd43132988effcac9b4
355e62f5ad12b005c862838156262eb2df2f8dff
a7c194b007ec40a130207e9ace9cecf598fc6ac5
0c02c8007ea5554d028f99fd3e29fc201fdeeab3
530210c7814e83564c7ca7bca8192515042c0b63
of_irq_parse_pci() and of_irq_parse_and_map_pci() are copied
from Linux 3.17 drivers/of/of_pci_irq.c
The related commit ID include:
98d9f30c820d509145757e6ecbc36013aa02f7bc
2361613206e66ce59cc0e08efa8d98ec15b84ed1
16b84e5a505c790538e534ad8dfda9c288691e40
0c02c8007ea5554d028f99fd3e29fc201fdeeab3
530210c7814e83564c7ca7bca8192515042c0b63
irq_create_of_mapping_new() is copied from Linux 3.17
kernel/irq/irqdomain.c irq_create_of_mapping().
The related commit ID include:
e6d30ab1e7d1281784672c0fc2ffa385cfb7279e
The copyright is owned by the author of the related commit ID
You can find out the detailed copyright information based on
the commit ID in the upstream repository.
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Change-Id: I24bcaaea4c6cbe43229bccaceb80e74f57a9ef93
Reviewed-on: http://git.am.freescale.net:8181/19677
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This is the SGTL5000 codec based audio driver supported with both
playback and capture dai link implemention.
This implementation is only compatible with device tree definition.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
---
This patch has almost been reviewed okay in the mail list. However
the maintainer Mark Brown suggested to use simple-card framework
instead of individual machine driver.
The discussion could be found:
URL: http://lkml.iu.edu//hypermail/linux/kernel/1312.2/02078.html
Since from Linux Kernel V3.12 to V3.14, it changes to much for ALSA
ASoC framework for supporting simple-card, and there will be about
more than 100 patches to backport it, and will also be many potiential
risks, so here just using individual machine driver instead of simple-card on SDK branch.
Change-Id: Ia37f752f8ee6362e726c3a9c602977aa7c0991b2
Reviewed-on: http://git.am.freescale.net:8181/19755
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Change-Id: I7cde95ba1ca9acbf6d2d01649b3ecb3d08db02c1
Reviewed-on: http://git.am.freescale.net:8181/19912
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Hongtao Jia <hongtao.jia@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
Change-Id: I08008c3dcd2b85b0c54b9f9ee939287f57745517
Reviewed-on: http://git.am.freescale.net:8181/19641
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add ftm0 node, cause of ftm0 can be set as a alarm before system
going to deep sleep.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Change-Id: Ie337ec554f6acd625cd691a0e07ffb96807cfa10
Reviewed-on: http://git.am.freescale.net:8181/19838
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Only Ftm0 can be used when system going to deep sleep. So this driver
to support ftm0 as a wakeup source.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Change-Id: Ib5fa7f7b72ab1f47fc80d1d816f112168ab84982
Reviewed-on: http://git.am.freescale.net:8181/19839
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Some Freescale device driver need to move to soc, because these drivers
are specific drivers. Before the soc/ to be created, the drivers had been
there arch/ or drivers/misc/, but now soc/ dir is a better choice.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Change-Id: Iba92df04682bae45f1a40d20e4a848814d3d895a
Reviewed-on: http://git.am.freescale.net:8181/19837
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Based on earlier thread "https://lkml.org/lkml/2013/10/7/662" and
discussion at Kernel Summit'2013, it was agreed to create
'driver/soc' for drivers which are quite SOC specific.
Further discussion on the subject is in response to
the earlier version of the patch is here:
http://lwn.net/Articles/588942/
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Olof Johansson <olof@lixom.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Sandeep Nair <sandeep_n@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Change-Id: I53101824ec18c3cb58fa2db61060ae1247705fcd
Reviewed-on: http://git.am.freescale.net:8181/19836
Reviewed-by: Emilian Medve <Emilian.Medve@freescale.com>
Tested-by: Emilian Medve <Emilian.Medve@freescale.com>
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Device-Tree binding for device endianness
Index Device Endianness properties
---------------------------------------------------
1 BE 'big-endian'
2 LE 'little-endian'
For one device driver, which will run in different scenarios above
on different SoCs using the devicetree, we need one way to simplify
this.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
---
This patch is pulled back from upstream:
commit 275876e208e28abf4b96ec89030e482b1331ee75
Change-Id: I28bbebb0b8e191555b7a7b001d9f4d04453a3106
Reviewed-on: http://git.am.freescale.net:8181/19856
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The Freescale FlexTimer Module time reference is a 16-bit counter
that can be used as an unsigned or signed increase counter.
CNTIN defines the starting value of the count and MOD defines the
final value of the count. The value of CNTIN is loaded into the FTM
counter, and the counter increments until the value of MOD is reached,
at which point the counter is reloaded with the value of CNTIN. That's
also when an overflow interrupt will be generated.
Here using the 'evt' prefix or postfix as clock event device and
the 'src' as clock source device.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Jingchang Lu <b35083@freescale.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
This patch is pulled back from upstream:
commit 2529c3a330797000d699d70c9a65b8525c6652de
Change-Id: I9a224167f82b13b2f868af82f9bdc5dc1ebb5e48
Reviewed-on: http://git.am.freescale.net:8181/19870
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Change-Id: I7aa37e4914623a303eb520c6d8fd6d4f84e9ddb2
Reviewed-on: http://git.am.freescale.net:8181/19815
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The same FTM PWM device can have a different endianness on different
SoCs. The device tree provides a property to describing this so that an
operating system device driver can handle all variants of the device.
Refer to the table below for the endianness of the FTM PWM block as
integrated into the existing SoCs:
SoC | FTM-PWM endianness
--------+-------------------
Vybrid | LE
LS1 | BE
LS2 | LE
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
This patch is pulled back from upstream:
commit a535e2e0debc2255fcf60a11d73fbb0534454cc3
Change-Id: Icf9f1efe7a4fd121cb5568f8552c01043110b108
Reviewed-on: http://git.am.freescale.net:8181/19867
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The regmap core supports different endian modes for devices. This patch
convert to direct regmap API usage, preparing to support big endianness
for LS1 SoC.
Using the regmap framework it will be easy to support devices that only
differ in endianness with the same device driver.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
This patch is pulled back from upstream:
commit 42fa98a9c3609c1aff466cb847e421c611cc9157
Change-Id: If7905b70eed8296dffa7ebde0dc03e951fcb7536
Reviewed-on: http://git.am.freescale.net:8181/19866
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch intends to prepare for converting to direct regmap API usage.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
This patch is pulled back from upstream:
commit cd6d92d2aa1556b22cd05acbc5f2cc8e5caafcc4
Change-Id: Iffdb310f7254bebfe65ca81594b25e4cbd546c9a
Reviewed-on: http://git.am.freescale.net:8181/19865
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The implementation of .config(), .enable() and .disable() operations in this
driver may sleep, thus set pwm_chip can_sleep flag.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
This patch is pulled back from upstream:
commit 39fd3f99aba3f7683fc9b62e916e4c886a1cb6b0
Change-Id: I06b3dac78d4acc12d96c8d248814eaaf6dc0ca33
Reviewed-on: http://git.am.freescale.net:8181/19864
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This adds the binding documentation for Freescale FlexTimer Module
(FTM) PWM driver under Documentation/devicetree/bindings/pwm/.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Yuan Yao <yao.yuan@freescale.com>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
This patch is pulled back from upstream:
commit 42586315b7b6e682bd4136a1a2bc2b1d50113487
Change-Id: I5bf1419bcfbb4bd84c6e3eb2285fad660835fda3
Reviewed-on: http://git.am.freescale.net:8181/19863
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The FTM PWM device can be found on Vybrid VF610 Tower and
Layerscape LS-1 SoCs.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Jingchang Lu <b35083@freescale.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
---
This patch is pulled back from upstream:
commit b505183b5117ce149c65ae62f8c00e889acafa69
Change-Id: I49cb21cbeeb944adf54958d29101e95204f1d693
Reviewed-on: http://git.am.freescale.net:8181/19862
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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