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2013-04-08fmd: fmd19 integrationMandy Lavi
Add fmd19 codebase, plus a minimal set of sources from dpaa-eth, necessary for bare compilation Change-Id: I390df8717671204e3d98a987135393bef4534e95 Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/1029 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-08phy/marvell: select copper registers in SGMII to copper modeMadalin Bucur
For the Marvel 88e1111 PHY only two SGMII modes are available, both allowing only SGMII to copper mode (with or without clock). SGMII to fiber mode is not supported. Make sure the fiber/copper registers selector bit is cleared, selecting copper mode registers. The bit is found set after the Auto-Negotiation restart erratum is performed. Change-Id: I21c829260e0f2440f66170d5d8721e7569d8154d Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com> (cherry picked from commit 2db23c6bd45fc4e6833dd86bb3ca28e37199b6ba) Reviewed-on: http://git.am.freescale.net:8181/1028 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05Merge tag 'v3.8.4-rt2'Scott Wood
2013-04-05phylib: Fix compile errors on xgmac_mdioBogdan Hamciuc
To be squashed with original commit 3c7bc7d99 Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com> Change-Id: Ifa7cd8d12c4f3f460d1dffbacbd6b7857bb54364 Reviewed-on: http://git.am.freescale.net:8181/1027 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05gianfar: Add support for nfc rx-flow hashing based on SPIClaudiu Manoil
Program the filer to perform hashing based on SPI (Secutity Parameter Index) for the AH/ESP incoming packets. The aim is to speed up processing of IPSEC flows on eTSEC platforms, by distributing them to separate Rx queues which gives the possibility to process the flows on separate CPUs. Signed-off-by: Pankaj Chauhan <pankaj.chauhan@freescale.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Change-Id: I9c7525b18589e28bb819a8bff7310c4f0ce08765 Reviewed-on: http://git.am.freescale.net:8181/1009 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05ethtool: Add define for nfc rx-flow hashing based on SPIClaudiu Manoil
This define makes it possible to enable hashing of AH or ESP flows (IPSEC) based on their SPI (Security Parameter Index) field. Signed-off-by: Pankaj Chauhan <pankaj.chauhan@freescale.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Change-Id: Ifb26f878e34f10ccde72507e157809c1807d00c6 Reviewed-on: http://git.am.freescale.net:8181/1008 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05gianfar: Fix Rx/Tx ring sizes setup by ethtool -GClaudiu Manoil
Remove the assumption that num_rx_queues==num_tx_queues from ethtool -G option. Rx and Tx ring sizes shall be configured independently by ethtool, according to the corresponding num_rx_queues and resp. num_tx_queues values. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Change-Id: I0e2af163eb37637b373e2fe49d14bfe2bfdfbd68 Reviewed-on: http://git.am.freescale.net:8181/983 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05KVM: PPC: add kvm handlers for altivec exceptionsStuart Yoder
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Change-Id: I9e9e71d52978e63d8388aa3fc413b2c11ea930f6 Reviewed-on: http://git.am.freescale.net:8181/925 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05iommu/fsl: PAMU driver fixes.Varun Sethi
This patch contains the following fixes: 1. Support for finding guts node on T4 & B4 platforms. 2. Make iova dma_addr_t constistent with iova_to_phys API change. 3. Disable SPAACE while reconfiguring it. 4. Make API and internal function static. 5. Free data pointer in case of an error. 6. Update comment description and remove unneeded comment. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I4763d9783e9f3d8057c991ca424e48e337c20f3b Reviewed-on: http://git.am.freescale.net:8181/884 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05iommu/fsl: Make iova dma_addr_t in the iova_to_phys API.Varun Sethi
Make iova dma_addr_t instead of u64. dma_addrt_t is more appropriate in our case as it is a DMA address. Also, as we support 64 bit physical addresses dma_addr_t is u64 even on 32 bit e500mc based platforms. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: Icbb83a6eae00a2be86c20b272eb537b095173f36 Reviewed-on: http://git.am.freescale.net:8181/883 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05powerpc/85xx: Adds IEEE1588 node in dtsXie Xiaobo
The new property "fsl,ts-to-buffer" is introduced for platforms which can get tx time stamp from skb buffer. Some platforms, like mpc8572ds, can only get tx time stamp from register, so these platforms have no this property. Signed-off-by: Tang Yuantian <b29983@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Change-Id: I4b2c9a7ad0c3a47c2c791ac7193f4ba5dc0c7627 Reviewed-on: http://git.am.freescale.net:8181/867 Reviewed-by: Manoil Claudiu-B08782 <claudiu.manoil@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05P1025RDB: Add QE TDM supportJiucheng Xu
The P1025RDB-PC have PMC sockets that support QE-TDM function. The patch enable Quicc Engine and the related signals of QE-TDM. Change-Id: Ia694253a9b16754aed41ae04e7c136905dea69d6 Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/908 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05powerpc/dts: Add TDM device tree nodes for P1025RDBJiucheng Xu
The dts file support QE-TDM function and PQ-MDS-T1 card for P1025RDB PQ-MDS-T1 is connected to the board by PMC. There is a zarlink le88266 on the card, we configure it by QE-SPI. Because P1025RDB uccs have been assigned to geth and uart as default, add four new node with a new name "tdm" to act as ucc, then do dts fixup in u-boot to delete the nodes don't be used. Change-Id: I577fae8a0ce4876d96f5ec1f98b295e29233dbaf Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/907 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05TDM: QUICC Engine UCC TDM test moduleXu Jiucheng
This is a small test module to transfer and receive data via tdm. It also supports zarlink LM card phone call. Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Kai.Jiang <Kai.Jiang@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Change-Id: I47396d43b37e31e8de926af353dadfdaf637f13f Reviewed-on: http://git.am.freescale.net:8181/906 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05TDM: Add fsl pq-mds-t1 card supportJiucheng Xu
The patch enable Freescale PQ-MDS-T1 card to work in T1 or E1 mode. This card is connected to the board by PMC socket, it aslo supports Line Module extended e.g. zarlink,le88266, we can use "fsl,card_support" in dts to select which module you want. Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Kai.Jiang <Kai.Jiang@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Change-Id: I3f39fed84e137f7a19859935dbf71fac01330b47 Reviewed-on: http://git.am.freescale.net:8181/905 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05TDM: Add a directly R/W API for tdm coreJiucheng Xu
Tdm core exported the simple function interfaces for user in kernel space. Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Kai.Jiang <Kai.Jiang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Change-Id: Ifc8ef6b14f7cbc3c88fcfc5e4a1afd59564d8059 Reviewed-on: http://git.am.freescale.net:8181/904 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05powerpc/qe: UCC transparent and TSA function support for TDMJiucheng Xu
This patch enabled UCC as transparent controller, working in continue mode, and enabled TSA A/B/C/D ports to send and receive data from UCC. This TDM function can transfer and receive data at different time slot based on tdm dts setting. Different UCC and TSA port can be binded to one TDM based on dts. Change-Id: I0da63966c82ca7da8e6bfc5fbb37f54596aef52a Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Kai.Jiang <Kai.Jiang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/903 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05P1021RDB: Add QE TDM supportJiucheng Xu
The P1021RDB-PC have PMC sockets that support QE-TDM function. The patch enable Quicc Engine and the related signals of QE-TDM. Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Change-Id: Ic1b01085322b92442b4e1b3df928b6247580d889 Reviewed-on: http://git.am.freescale.net:8181/902 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05powerpc/qe: Setup clock source for TDMJiucheng Xu
Add tdm clock configuration in both qe clock system and ucc fast controler. Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Kai.Jiang <Kai.Jiang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Change-Id: I93021e6132767d0bb29ecc859f083250eb962c86 Reviewed-on: http://git.am.freescale.net:8181/901 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05powerpc/dts: Add TDM device tree nodes for P1021RDBJiucheng Xu
The dts file support QE-TDM function and PQ-MDS-T1 card for P1021RDB. PQ-MDS-T1 is connected to the board by PMC, there is a zarlink le88266 on the card, we configure it by QE-SPI. Because PMC has a shared CS pin with L2switch, so we do the device tree fixup in uboot. Change-Id: I7ecee0d93a105ef158455238fb003a2ad2ca32e7 Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/900 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05TDM: The device tree bindings for QE TDM.Jiucheng Xu
Add tdm node's devicetreee binding to ucc, descrbe the new properties, add fsl pq-mds-t1 card's devicetree binding for TDM, Change-Id: If27bace105874c8e947d134d2932b1d5908fd0fb Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/899 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05powerpc: Enable FSL_PAMU config option.Varun Sethi
Enable FSL_PAMU config option in corenet32_smp_defconfig and corenet64_smp_defconfig. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: Ibf2ca5742f9c6eb464f079ce06adb37ff93aad3c Reviewed-on: http://git.am.freescale.net:8181/885 Reviewed-by: Medve Emilian-EMMEDVE1 <Emilian.Medve@freescale.com> Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-05Revert "Dummy Build"Schmitt Richard-B43082
This reverts commit 72c7e87f92fdc8593fd4e3c1b5cb703c0aee330c Change-Id: Ib97cb6e0633777a2e2aa98e70be538f284be53eb Reviewed-on: http://git.am.freescale.net:8181/1075 Reviewed-by: Schmitt Richard-B43082 <B43082@freescale.com> Tested-by: Schmitt Richard-B43082 <B43082@freescale.com>
2013-04-05Dummy BuildRich Schmitt
Signed-off-by: Rich Schmitt <B43082@freescale.com>
2013-04-04mmc:block Add Fixup of BROKEN CMD23 for SANDISK cardHaijun.Zhang
Some sandisk card can't support CMD23, cmd timeout will generate. SO add FIX-UP for two type of these Sandisk cards. "SDMB-32" and "SDM032" Error log: mmcblk0: timed out sending SET_BLOCK_COUNT command, card status 0x400900 mmcblk0: timed out sending SET_BLOCK_COUNT command, card status 0x400900 mmcblk0: timed out sending SET_BLOCK_COUNT command, card status 0x400900 end_request: I/O error, dev mmcblk0, sector 0 Buffer I/O error on device mmcblk0, logical block 0 mmcblk0: timed out sending SET_BLOCK_COUNT command, card status 0x400900 Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Change-Id: I14efdaa447b9c683a7a0bc3444a58df030112806 Reviewed-on: http://git.am.freescale.net:8181/886 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-04Revert "Merge sdk-v1.3.x config and device tree files"Fleming Andrew-AFLEMING
This reverts commit 7a8b241fba87dac3d52f3af01cf8382b75b72ccd I'm guessing it was applied accidentally. To be frank, it doesn't look like most of my comments from the previous version were resolved by this version. Change-Id: I9af40bff5021a432f7fad805771ec4d6c4fc39b7 Reviewed-on: http://git.am.freescale.net:8181/1012 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-04kconfig-preempt-rt-full.patchThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-04-04kconfig-disable-a-few-options-rt.patchThomas Gleixner
Disable stuff which is known to have issues on RT Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-04-04completion: Use simple wait queuesThomas Gleixner
Completions have no long lasting callbacks and therefor do not need the complex waitqueue variant. Use simple waitqueues which reduces the contention on the waitqueue lock. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-04-04wait-simple: Rework for use with completionsThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-04-04sched: Check for idle task in might_sleep()Thomas Gleixner
Idle is not allowed to call sleeping functions ever! Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-04-04sched: Init idle->on_rq in init_idle()Thomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-04-04slub: delay ctor until the object is requestedSebastian Andrzej Siewior
It seems that allocation of plenty objects causes latency on ARM since that code can not be preempted Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2013-04-04slub: Enable irqs for __GFP_WAITThomas Gleixner
SYSTEM_RUNNING might be too late for enabling interrupts. Allocations with GFP_WAIT can happen before that. So use this as an indicator. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-04-04mmci: Remove bogus local_irq_save()Thomas Gleixner
On !RT interrupt runs with interrupts disabled. On RT it's in a thread, so no need to disable interrupts at all. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-04-04mm: bounce: Use local_irq_save_nortThomas Gleixner
kmap_atomic() is preemptible on RT. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-04-04block: Use cpu_chill() for retry loopsThomas Gleixner
Retry loops on RT might loop forever when the modifying side was preempted. Steven also observed a live lock when there was a concurrent priority boosting going on. Use cpu_chill() instead of cpu_relax() to let the system make progress. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: stable-rt@vger.kernel.org
2013-04-04sched: Consider pi boosting in setschedulerThomas Gleixner
If a PI boosted task policy/priority is modified by a setscheduler() call we unconditionally dequeue and requeue the task if it is on the runqueue even if the new priority is lower than the current effective boosted priority. This can result in undesired reordering of the priority bucket list. If the new priority is less or equal than the current effective we just store the new parameters in the task struct and leave the scheduler class and the runqueue untouched. This is handled when the task deboosts itself. Only if the new priority is higher than the effective boosted priority we apply the change immediately. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: stable@vger.kernel.org Cc: stable-rt@vger.kernel.org
2013-04-04sched: Queue RT tasks to head when prio dropsThomas Gleixner
The following scenario does not work correctly: Runqueue of CPUx contains two runnable and pinned tasks: T1: SCHED_FIFO, prio 80 T2: SCHED_FIFO, prio 80 T1 is on the cpu and executes the following syscalls (classic priority ceiling scenario): sys_sched_setscheduler(pid(T1), SCHED_FIFO, .prio = 90); ... sys_sched_setscheduler(pid(T1), SCHED_FIFO, .prio = 80); ... Now T1 gets preempted by T3 (SCHED_FIFO, prio 95). After T3 goes back to sleep the scheduler picks T2. Surprise! The same happens w/o actual preemption when T1 is forced into the scheduler due to a sporadic NEED_RESCHED event. The scheduler invokes pick_next_task() which returns T2. So T1 gets preempted and scheduled out. This happens because sched_setscheduler() dequeues T1 from the prio 90 list and then enqueues it on the tail of the prio 80 list behind T2. This violates the POSIX spec and surprises user space which relies on the guarantee that SCHED_FIFO tasks are not scheduled out unless they give the CPU up voluntarily or are preempted by a higher priority task. In the latter case the preempted task must get back on the CPU after the preempting task schedules out again. We fixed a similar issue already in commit 60db48c (sched: Queue a deboosted task to the head of the RT prio queue). The same treatment is necessary for sched_setscheduler(). So enqueue to head of the prio bucket list if the priority of the task is lowered. It might be possible that existing user space relies on the current behaviour, but it can be considered highly unlikely due to the corner case nature of the application scenario. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: stable@vger.kernel.org Cc: stable-rt@vger.kernel.org
2013-04-04sched: Adjust sched_reset_on_fork when nothing else changesThomas Gleixner
If the policy and priority remain unchanged a possible modification of sched_reset_on_fork gets lost in the early exit path. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: stable@vger.kernel.org Cc: stable-rt@vger.kernel.org
2013-04-04treercu-use-simple-waitqueueRT patchquilt
2013-04-04rcutiny: Use simple waitqueueThomas Gleixner
Simple waitqueues can be handled from interrupt disabled contexts. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-04-04wait-simple: Simple waitqueue implementationThomas Gleixner
wait_queue is a swiss army knife and in most of the cases the complexity is not needed. For RT waitqueues are a constant source of trouble as we can't convert the head lock to a raw spinlock due to fancy and long lasting callbacks. Provide a slim version, which allows RT to replace wait queues. This should go mainline as well, as it lowers memory consumption and runtime overhead. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-04-04powerpc-preempt-lazy-support.patchThomas Gleixner
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-04-04gpu/i915: don't open code these thingsSebastian Andrzej Siewior
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2013-04-04fs/fscache: done merge spin_lock() in while()Sebastian Andrzej Siewior
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2013-04-04HACK: printk: drop the logbuf_lock more oftenSebastian Andrzej Siewior
The lock is hold with irgs off. The latency drops 500us+ on my arm bugs with a "full" buffer after executing "dmesg" on the shell. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2013-04-04spi/omap-mcspi: check condition also after timeoutSebastian Andrzej Siewior
It is possible that the handler gets interrupted after checking the status. After it resumes it the time out is due but the condition it was waiting for might be true. Therefore it is necessary to check the condition in case of an time out to be sure that the condition is not true _and_ the time passed by. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2013-04-04i2c/omap: drop the lock hard irq contextSebastian Andrzej Siewior
The lock is taken while reading two registers. On RT the first lock is taken in hard irq where it might sleep and in the threaded irq. The threaded irq runs in oneshot mode so the hard irq does not run until the thread the completes so there is no reason to grab the lock. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2013-04-04powerpc/fsl-msi: use a different locklcass for the cascade interruptSebastian Andrzej Siewior
lockdep thinks that it might deadlock because it grabs a lock of the same class while calling the generic_irq_handler(). This annotation will inform lockdep that it will not. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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