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2014-03-18fsl/qman: Modifications for new stash attribute setup API.Varun Sethi
An additional parameter (window number) is required for API. Add the window number parameter while invoking the API. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I7ff2552bf15bee25a7e41fd5e0a1781a323aceed Reviewed-on: http://git.am.freescale.net:8181/9618 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18iommu/fsl: PAMU driver changes for DSP stasing support.Varun Sethi
Modifications to PAMU driver for supporting DSP stashing. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I1462806c85f0f398a332ac321bb7b67a8cabc1bb Reviewed-on: http://git.am.freescale.net:8181/9617 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18iommu/fsl: Setup operation mapping for FMAN.Varun Sethi
Setup operation mapping for FMAN. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I1803c366979a28fe3f547526ee0e2f23a5dd03b7 Reviewed-on: http://git.am.freescale.net:8181/9616 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18iommu/fsl : Factor out default PAACE setup code andVarun Sethi
enable all LIODNs. Factor out default PAACE entry setup code and enable all LIODNs for handling the autonomous case. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I31b81576e590569be614511b27d09f01cc4fcf86 Reviewed-on: http://git.am.freescale.net:8181/9615 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18e6500/defconfig: Enabled FSL_UIO_DMAVakul Garg
To enable direct access of DMA channels from user space, CONFIG_UIO_FSL_DMA needs to be turned on. User space DMA driver is used by applications using ipc and usdpaa sdk submodules. Signed-off-by: Vakul Garg <vakul@freescale.com> Change-Id: Id874ead3d373281614f7638a52b1dc074a648ebe Reviewed-on: http://git.am.freescale.net:8181/9817 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Naveen Burmi <NaveenBurmi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18powerpc/p1010rdb:update dts to adapt to both old and new p1010rdbZhao Qiang
P1010rdb-pa and p1010rdb-pb have different phy interrupts. So update dts to adapt to both p1010rdb-pa and p1010rdb-pb. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I2e80e63576396a8fe726a6306246b16c25744cff Reviewed-on: http://git.am.freescale.net:8181/5607 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Zang Tiefei-R61911 <tie-fei.zang@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9593 Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17crypto: caam - use NAPI instead of taskletNitesh Lal
This patch updates the current tasklet implementation to NAPI so as the system is more balanced in the terms that the packet submission and the packet forwarding after being processed can be done at the same priority Signed-off-by: Naveen Burmi <naveenburmi@freescale.com> rebased and tuned NAPI_WEIGHT. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> (cherry picked from commit c74e14d7ff270f8d85c7988e9286f64b721f34ee) Change-Id: I3a31db49a1a6060b3ad5cd0fc4ee4044858438bc Reviewed-on: http://git.am.freescale.net:8181/520 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Signed-off-by: Nitesh Lal <NiteshNarayanLal@freescale.com> Change-Id: I685d687d89a53387287912cd2273f8c1d6a6e4e4 Reviewed-on: http://git.am.freescale.net:8181/9753 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Vakul Garg <vakul@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: update fsl_pci_ep.c according to kernel changesMinghuan Lian
1. Now in kernel the dev_attrs field is removed from struct class, and is converted to use dev_groups. So the patch uses pci_ep_groups instead of pci_ep_attrs. 2. The field pci_mem_offset of struct pci_controller has been changed to mem_offset[], so the patch update the related code. 3. Remove is_pcie initialization for this field has been removed from struct pci_dev. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I9a664b79a1528b52728dae60a929afe4b62aa8c2 Reviewed-on: http://git.am.freescale.net:8181/9607 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: fix ATMU window attribute settingMinghuan Lian
If window size is 0, the bits of size will be 0xffffffff, so window attribute will be set a wrong value. The patch fixes this issue. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: Ieac8428eb1b41a245c89637186d4eb27eedcff55 Reviewed-on: http://git.am.freescale.net:8181/9606 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: add MSIX supportMinghuan Lian
1. The patch initializes MSIX trap outbound window, the application can map this window and trigger the MSIX interrupt. 2. The patch initializes MSIX inbound window which is used to store MSIX vector and PBA data. 3. Add sysfs node to display MSIX vector setting for example: # cat /sys/class/pci_ep/pci0-pf0/msix MSIX venctor 0: control:0x0 data:0x0000406c addr:0x00000000fee00000 MSIX venctor 1: control:0x0 data:0x0000407c addr:0x00000000fee00000 MSIX venctor 2: control:0x0 data:0x0000408c addr:0x00000000fee00000 MSIX venctor 3: control:0x0 data:0x0000409c addr:0x00000000fee00000 MSIX venctor 4: control:0x0 data:0x000040ac addr:0x00000000fee00000 MSIX venctor 5: control:0x0 data:0x00000000 addr:0x0000000000000000 MSIX venctor 6: control:0x0 data:0x00000000 addr:0x0000000000000000 MSIX venctor 7: control:0x0 data:0x00000000 addr:0x0000000000000000 Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I18a6f9056b3c630bba91f5f1dfef2eee01995926 Reviewed-on: http://git.am.freescale.net:8181/9605 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: add VF ATMU access supportMinghuan Lian
All VFs of a PF share the common inbound/outbound windows except translation registers of outbound windows. A VF can only change translation registers of outbound windows. A PF can change all ATMU of VF. The patch provides VF ATMU register definition and provides interfaces to access inbound/outbound windows. It also adds PCI_EP_REGION_MEM type to return PF's memory resource. The application can get and reassign the memory resource to VF. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: Iec877a8054ac47b64d9d94abb9bc32dc0450211e Reviewed-on: http://git.am.freescale.net:8181/9604 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: initialize PF and VF ATMUMinghuan Lian
The first PCI controller of T4 has two physical functions(PF). Each physical functions supports 64 virtual functions(VF). There may be multiple functions to share PCI memory resource. The patch first disables all the inbound/outbound windows then, divides the PCI memory resource equally among all functions and enable a PF/VF outbound window to cover assigned memory. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I84f2211438f1dae32a32d22c4ac60f3f53993159 Reviewed-on: http://git.am.freescale.net:8181/9603 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: fix PCI configuration accessMinghuan Lian
PCI controller which supports SR_IOV and works in End Point mode provides a different method to access configuration. It dose not use bus number device number and function number, instead, it uses physical function number and virtual function number. Different PF may use different offset and stride. It is hard to calculate PF VF number by bus and device number. The original calculation is not suitable for all situations. The patch traverse all functions to find the correct PF VF number. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: Id4a475114c24775d1098483e727a6f824ecada05 Reviewed-on: http://git.am.freescale.net:8181/9602 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: fix checking PCI register sizeMinghuan Lian
For T4240, the first PCI controller whose register size is 0x10000, has two physical functions and each physical function register size is 0x2000. But for some older platform PCI controller size is 0x1000 less than 0x2000. The original checking of PCI register size is mistaken. The patch is to fix this issue. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I089adfb5f31f09f57ea1c2ee29572ac3c68992f4 Reviewed-on: http://git.am.freescale.net:8181/9601 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fman/dts: fix compatible of mdio node for fman v3Shaohui Xie
Mdio node's compatible for each MAC should be "fsl,fman-memac-mdio" instead of "fsl,fman-memac-tbi" in fman v3. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Change-Id: I848527f67b4e5d033fcfbb739d78341de576f6d0 Reviewed-on: http://git.am.freescale.net:8181/9661 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17powerpc/t4240/dts: add XFI PHY device nodes for 10GBASE-KRShaohui Xie
10GBASE-KR use XFI PCS(Physical Coding Sublayer) module. Each PCS is driven by the corresponding MAC's MDIO. 10GBASE-KR will use PCS module to do auto-negotiation and link training. So, add XFI PHY device nodes for each 10G MAC. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Change-Id: I69609ff42eba95dbed978850bf07fe0c360c9ce2 Reviewed-on: http://git.am.freescale.net:8181/9664 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17powerpc/pci: Fix IMMRBAR addressMinghuan Lian
For PEXCSRBAR, bits 3-0 indicate prefetchable and address type. So when getting base address, these bits should be masked, otherwise we may get incorrect base address. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I03ca7c1201cf0de1042173488e9e8dd4c48faf6e Reviewed-on: http://git.am.freescale.net:8181/9818 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17xfrm_asf: Patch to revert the changes of multi-policy.Sandeep Malik
This patch reverts the changes for multi-policy being merged into master branch as the compilation of ASF will break. Signed-off-by: Sandeep Malik <Sandeep.Malik@freescale.com> Change-Id: Ifb748be84574daef6ba9adcf0a5db58df5b790b9 Reviewed-on: http://git.am.freescale.net:8181/9807 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17mpc85xx: Expand the size of u-boot Bootloader ImageYing Zhang
Because the size of u-boot Bootloader gets bigger, this patch adjust the size for NAND bootloader to 768KB and adjust the size for SPI bootloader to 1MB. Signed-off-by: Ying Zhang <b40530@freescale.com> Change-Id: Ida21977b15cc25c9e2667138222537b3af7138c7 Reviewed-on: http://git.am.freescale.net:8181/9454 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-13asf_ipsec_linux: Patch to add support for multiple SPD entries mapping to ↵Sandeep Malik
single SA entry. This patch adds the support for multiple SPD entries to map to single SA entry. CQ: ENGR00267797 Signed-off-by: Sandeep Malik <Sandeep.Malik@freescale.com> Change-Id: I2db3620f9b8262d047c1ffc847d4337e73be02f7 Reviewed-on: http://git.am.freescale.net:8181/8828 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Nipun Gupta <Nipun.Gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-13powerpc/t2080rdb: Add T2080RDB board supportShengzhou Liu
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. The board feature overview: Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz DDR Memory: - Single memory controller capable of supporting DDR3 and DDR3-LP devices - 72bit 4GB DDR3-LP SODIMM in slot Ethernet interfaces: - Two 10M/100M/1Gbps RGMII ports on-board - Two 10Gbps SFP+ ports on-board - Two 10Gbps Base-T ports on-board Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes 16 lanes configuration: - SerDes-1 Lane A-B: to two 10G SFP+ (MAC9 & MAC10) - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) - SerDes-1 Lane E-H: to PCIe goldfinger (PCIe1 x4, Gen3) - SerDes-2 Lane A-D: to PCIe connector (PCIe4 x4, Gen3) - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) - SerDes-2 Lane G-H: to SATA1 & SATA2 IFC/Local Bus - NOR: 128MB 16-bit NOR flash - NAND: 1GB 8-bit NAND flash - CPLD: for system controlling with programable header on-board eSPI: - 64MB N25Q512 SPI flash USB: - Two USB2.0 ports with internal PHY (both Type-A) PCIe: - One PCIe x4 gold-finger - One PCIe x4 connector - One PCIe x2 end-point device (C293 crypto co-processor) SATA: - Two SATA 2.0 ports on-board SDHC: - support a TF-card on-board I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports This board can work in two mode: standalone mode and PCIe endpoint mode. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Change-Id: Id30adfba9b78b0707aecae33dbc03a44e4c38b59 Reviewed-on: http://git.am.freescale.net:8181/9459 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-13gianfar: Add skb recyclingClaudiu Manoil
Add global per-CPU skb recycle lists to improve packet forwarding throughput. Having per-interface recycle lists doesn't allow skb recycling when you're e.g. unidirectionally routing from eth0 to eth1, as eth1 will be producing a lot of recycled skbuffs but eth0 won't have any skbuffs to allocate from its recycle list. Reclaiming resp. recycling of skbs is done on the Rx resp. Tx confirmation paths, in softirq context, and the access to the driver's per-CPU skb lists is lockless and preemption safe. The skb recycling support was removed from the mainline kernel (starting with v3.0). Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Change-Id: I40d47d1d4da337f4e9b0b18136848aa807fc24f7 Reviewed-on: http://git.am.freescale.net:8181/9707 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-13Adding a field in net_device struct to storeSandeep Malik
the cii used by ASF for device mapping. Added an extra field cii(Common interface id) in linux struct net_device. This field will be filled with the free cii when ASF try to create the device mapping in asfctrl_create_dev_map(). CQ:ENGR296530 Signed-off-by: Sahil Malhotra <sahilmalhotra@freescale.com> Signed-off-by: Sandeep Malik <Sandeep.Malik@freescale.com> Change-Id: Ifaee2341886e206a5c5d9bf8e847fb5840a267d3 Reviewed-on: http://git.am.freescale.net:8181/8826 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-13spi/fsl-espi: fix the return value judgment of irq_of_parse_and_mapHou Zhiqiang
Signed-off-by: Hou Zhiqiang <b48286@freescale.com> Change-Id: Ieb821f465dd8dd6b63264208c9eaf7d41ffb5cc8 Reviewed-on: http://git.am.freescale.net:8181/9580 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-13spi/fsl-espi: Add Power Management support for eSPI controllerHou Zhiqiang
Add PM support for eSPI controller using callback function suspend and resume in .driver.pm of platform_driver. Signed-off-by: Hou Zhiqiang <b48286@freescale.com> Change-Id: Ibc1dbdbe830f136ffc26a3610f6a4a1581e0e8cb Reviewed-on: http://git.am.freescale.net:8181/9579 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-13t2080qds : Add USDPAA device trees for T2080QDSKuldip Giroh
- 42G configuration (4x10G + 2x1G) is selected for USDPAA. - Add USDPAA device tree for shared MAC and macless interfaces also. 10GEC4 is made shared MAC in the tree. Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Change-Id: Iff57cc9a722f0cde187f841ab7e5001d9ef2dd28 Reviewed-on: http://git.am.freescale.net:8181/6911 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Vakul Garg <vakul@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> (cherry picked from commit 662f83e43b86d291026251eb080a599c142f0040) Reviewed-on: http://git.am.freescale.net:8181/9652 Reviewed-by: Sandeep Singh <sandeep@freescale.com>
2014-03-12gianfar: Fix multi-queue support checks @probe()Claudiu Manoil
priv is not instantiated at gfar_of_init() time, when parsing the DT for info on supported HW queues. Before the netdev can be allocated, the number of supported queues must be known. Because the number of supported queues depends on device type, move the compatibility checks before netdev allocation. Local vars are used to hold the operation mode info before netdev allocation. This fixes the null accesses for priv->.., in gfar_of_init. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net> Change-Id: I7b3c4c65196bb443d7e1eccf01ef0a2b5cf6f193 Reviewed-on: http://git.am.freescale.net:8181/9706 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
2014-03-12gianfar: Use Single-Queue polling for "fsl,etsec2"Claudiu Manoil
For the "fsl,etsec2" compatible models the driver currently supports 8 Tx and Rx DMA rings (aka HW queues). However, there are only 2 pairs of Rx/Tx interrupt lines, as these controllers are integrated in low power SoCs with 2 CPUs at most. As a result, there are at most 2 NAPI instances that have to service multiple Tx and Rx queues for these devices. This complicates the NAPI polling routine having to iterate over the mutiple Rx/Tx queues hooked to the same interrupt lines. And there's also an overhead at HW level, as the controller needs to service all the 8 Tx rings in a round robin manner. The combined overhead shows up for multi parallel Tx flows transmitted by the kernel stack, when the driver usually starts returning NETDEV_TX_BUSY leading to NETDEV WATCHDOG Tx timeout triggering if the Tx path is congested for too long. As an alternative, this patch makes the driver support only one Tx/Rx DMA ring per NAPI instance (per interrupt group or pair of Tx/Rx interrupt lines) by default. The simplified single queue polling routine (gfar_poll_sq) will be the default napi poll routine for the etsec2 devices too. Some adjustments needed to be made to link the Tx/Rx HW queues with each NAPI instance (2 in this case). The gfar_poll_sq() is already successfully used by older SQ_SG_MODE (single interrupt group) controllers. This patch fixes Tx timeout triggering under heavy Tx traffic load (i.e. iperf -c -P 8) for the "fsl,etsec2" (currently the only MQ_MG_MODE devices). There's also a significant memory footprint reduction by supporting 2 Rx/Tx DMA rings (at most), instead of 8, for these devices. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net> Change-Id: Id9a2f2737ea0d1d0413e68c6401d86d43a7dc237 Reviewed-on: http://git.am.freescale.net:8181/9705 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
2014-03-12gianfar: Separate out the Tx interrupt handling (Tx NAPI)Claudiu Manoil
There are some concurrency issues on devices w/ 2 CPUs related to the handling of Rx and Tx interrupts. eTSEC has separate interrupt lines for Rx and Tx but a single imask register to mask these interrupts and a single NAPI instance to handle both Rx and Tx work. As a result, the Rx and Tx ISRs are identical, both are invoking gfar_schedule_cleanup(), however both handlers can be entered at the same time when the Rx and Tx interrupts are taken by different CPUs. In this case spurrious interrupts (SPU) show up (in /proc/interrupts) indicating a concurrency issue. Also, Tx overruns followed by Tx timeout have been observed under heavy Tx traffic load. To address these issues, the schedule cleanup ISR part has been changed to handle the Rx and Tx interrupts independently. The patch adds a separate NAPI poll routine for Tx cleanup to be triggerred independently by the Tx confirmation interrupts only. Existing poll functions are modified to handle only the Rx path processing. The Tx poll routine does not need a budget, since Tx processing doesn't consume NAPI budget, and hence it is registered with minimum NAPI weight. NAPI scheduling does not require locking since there are different NAPI instances between the Rx and Tx confirmation paths now. So, the patch fixes the occurence of spurrious Rx/Tx interrupts. Tx overruns also occur less frequently now. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net> Change-Id: I6951e2a4b057519a966214e7d7e874cc9524123a Reviewed-on: http://git.am.freescale.net:8181/9704 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
2014-03-12fsl/usb: Modify PHY_CLK_VALID bit usageRamneek Mehresh
PHY_CLK_VALID bit is de-featured for all controller versions before 2.4, and is only to be used for internal UTMI phy Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Change-Id: Ie1f5d9f6f75f759e482e6ff39a557ee888ee66ae Reviewed-on: http://git.am.freescale.net:8181/9299 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Suresh Gupta <suresh.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-12powerpc/85xx/dts: add third elo3 dma componentShengzhou Liu
Add elo3-dma-2.dtsi to support the third DMA controller. This is used on T2080, T4240, B4860, etc. FSL MPIC v4.3 adds a new discontiguous address range for internal interrupts, e.g. internal interrupt 0 is at offset 0x200 and thus interrupt number is: 0x200 >> 5 = 16 in the device tree. DMA controller 3 channel 0 internal interrupt 240 is at offset 0x3a00, and thus the corresponding interrupt number is: 0x3a00 >> 5 = 464, it's similar for other 7 interrupt numbers of DMA 3 channels. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com> Change-Id: Iee7019bb1729274327db598d935c0c5560fc2418 Reviewed-on: http://git.am.freescale.net:8181/9455 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-12crypto: caam - Fix crash in caamalg_qi module_initNitesh Lal
Added NULL check for private structure in caamalg_qi module. It is NULL when the caam driver fails to properly initialize (e.g. RNG4 init failed), then the module should gracefully do a failed initialization. Signed-off-by: Nitesh Lal <NiteshNarayanLal@freescale.com> Change-Id: Ief8596b9fcc5e16384e4b71ae70ec19b959ea201 Reviewed-on: http://git.am.freescale.net:8181/9578 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yashpal Dutta <yashpal.dutta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-12powerpc/t2081qds: Add ethernet supportShengzhou Liu
Add T2081QDS Ethernet configuration to support RGMII, SGMII, XFI. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Change-Id: I347a2e000d0ed616e33fdb96bfbda8f6c25b6d3b Reviewed-on: http://git.am.freescale.net:8181/8971 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9460
2014-03-12powerpc/t2080qds: add dpaa ethernet and rman nodesShengzhou Liu
- Add DPAA related nodes for ethernet on T2080QDS - Add RMan node Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Change-Id: I1f92de8d646b8ea08ddbb582660e7a14eba9af13 Reviewed-on: http://git.am.freescale.net:8181/9458 Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-12powerpc/fsl-booke: Add initial T208x QDS board supportShengzhou Liu
Add support for Freescale T2080/T2081 QDS Development System Board. T2081QDS board shares the same PCB with T1040QDS with some differences. The T2080QDS Development System is a high-performance computing, evaluation, and development platform that supports T2080 QorIQ Power Architecture processor, with following major features: T2080QDS feature overview: Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz Memory: - Single memory controller capable of supporting DDR3 and DDR3-LV devices - Two DDR3 memory, 4GB, Dual rank @ 1866 Mbps data rate, and ECC support Ethernet interfaces: - Two 1Gbps RGMII on-board ports - Four 10Gbps XFI on-board cages - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes: - 16 lanes up to 10.3125GHz - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI IFC: - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA eSPI: - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040) USB: - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB) PCIE: - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0) SATA: - Two SATA 2.0 ports on-board SRIO: - Two Serial RapidIO 2.0 ports up to 5 GHz eSDHC: - Supports SD/MMC/eMMC Card DMA: - Three 8-channels DMA controllers I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports System Logic: - QIXIS-II FPGA system controll Differences between T2080 and T2081: Feature T2080 T2081 1G Ethernet numbers: 8 6 10G Ethernet numbers: 4 2 SerDes lanes: 16 8 Serial RapidIO,RMan: 2 no SATA Controller: 2 no Aurora: yes no SoC Package: 896-pins 780-pins Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Change-Id: I957e25509ee47dab0d8e9d780241728358c609a5 Reviewed-on: http://git.am.freescale.net:8181/9457 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-12powerpc/fsl-booke: Add initial device tree support for T2080/T2081 SoCShengzhou Liu
Add initial device tree for T2080/T2081 without DPAA components. The T2080 SoC includes the following function and features: - Four dual-threaded 64-bit Power architecture e6500 cores, up to 1.8GHz - 2MB L2 cache and 512KB CoreNet platform cache (CPC) - Hierarchical interconnect fabric - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving - Data Path Acceleration Architecture (DPAA) incorporating acceleration - 16 SerDes lanes up to 10.3125 GHz - 8 Ethernet interfaces (multiple 1G/2.5G/10G MACs) - High-speed peripheral interfaces - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0) - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz - Additional peripheral interfaces - Two serial ATA (SATA 2.0) controllers - Two high-speed USB 2.0 controllers with integrated PHY - Enhanced secure digital host controller (SD/SDXC/eMMC) - Enhanced serial peripheral interface (eSPI) - Four I2C controllers - Four 2-pin UARTs or two 4-pin UARTs - Integrated Flash Controller supporting NAND and NOR flash - Three eight-channel DMA engines - Support for hardware virtualization and partitioning enforcement - QorIQ Platform's Trust Architecture 2.0 T2081 personality is a reduced personality of T2080 without SATA, sRIO, RMan, Aurora, and with less SerDes lanes and ethernet interfaces. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Change-Id: Idb3b97d617fc2dd9ce6c778560f95d44542bbdfd Reviewed-on: http://git.am.freescale.net:8181/9456 Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-12Added support for PKC keygenYashpal Dutta
As a part of PKC support, RSA, DSA DH, ECDH, ECDSA requires key generation. The patch adds support for key generation support for DSA, ECDSA, DH, ECDH. Signed-off-by: Yashpal Dutta <yashpal.dutta@freescale.com> Change-Id: Ifc90734302e0b581db1b3c30f9e62266bb4674e7 Reviewed-on: http://git.am.freescale.net:8181/9545 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-11Entry of CEETM in DTS fileGanga Negi
Adding details regarding CEETM QDisc qportal in DTS file. Signed-off-by: Ganga Negi <ganga.negi@freescale.com> CQ: ENGR299854 Change-Id: I36bc185227bfef275470be001deb5bebb6a151b9 Reviewed-on: http://git.am.freescale.net:8181/9510 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Haiying Wang <Haiying.Wang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-07fmd: fix flow id classification to work after PCD re-init"Mandy Lavi
For KG & Policer: Renamed pointedOwners --> RequiredActionFlag changed from counter to flag added flag clear at delete Change-Id: I55dd4125202d59e7659a3ffb8e39f56eaac7cd62 Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9261 Reviewed-by: Eyal Harari <Eyal.Harari@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9449
2014-03-07fmd: extend workaround of fman reset on t208x and t4160v2Shengzhou Liu
The same hang issue was observed on T208x and T4160v2 also. So extend the workaround for now. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Change-Id: If75d58a3d609f3607050c0cf306d9c86aa69cfaf Reviewed-on: http://git.am.freescale.net:8181/7205 Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9450 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
2014-03-07FMD: DSAR: added accumulate mode when entering deep sleepEyal Harari
Change-Id: Iad7a7c608e738661c1a9205fa2da45681ab2bc84 Signed-off-by: Eyal Harari <Eyal.Harari@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9305 Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com> Reviewed-by: Sunil Kumar Kori <Sunil.Kori@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9446
2014-03-07fmd: adjust allocation of fifo resources for fmanv3lMandy Lavi
Change-Id: I249456d0f157547fab221286e1c18e59ce5345d3 Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9257 Reviewed-by: Igal Liberman <Igal.Liberman@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9448
2014-03-07FMD: DSAR: Establish the auto-response driverEyal Harari
- New code for auto-response - Changed parser init - Added DsarCheckParams and fm_port_dsar_dump_regs - Added snmp support - Added statistics features - Fixed SNMP oid table - Removed usage of create_proc_entry - for merging to master Change-Id: Icd6292c8d68ddb4ee60ecfed87419c1f4cbf5e74 Signed-off-by: Eyal Harari <Eyal.Harari@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/8711 Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com> Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9445
2014-03-07FMD: DSAR: Added dsar device tree sourceEyal Harari
Change-Id: I1da08cec47972011c871796ab0d1b7a8fbe3024e Signed-off-by: Eyal Harari <Eyal.Harari@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9306 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com> Reviewed-by: Sunil Kumar Kori <Sunil.Kori@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9447 Tested-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-07fmd: fix mis-assignment of compat and pcd structuresMandy Lavi
Fixes memory corruption issues within lnxwrp_ioctls_fm.c Caused by wrong usage of some data structures. Change-Id: I75b710dd5888cc6ab3b86f0604cd5ef177396e23 Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9041 Reviewed-by: Nir Erez <nir.erez@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9386 Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
2014-03-06fmd: correct compilation warning in lnxwrp_sysfs_fm_port.c Mandy Lavi
Change-Id: I1d0661f217d96c530ad03e797be85edf2c8a3b1e Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9077 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Nir Erez <nir.erez@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> (cherry picked from commit 431aea6cc98e1c0350214dc3bdb2a32269307211) Change-Id: I1d0661f217d96c530ad03e797be85edf2c8a3b1e Reviewed-on: http://git.am.freescale.net:8181/9431 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-06Only initalize fragment owner when fragement is first createdRoy Pledge
When a USDPAA memory fragment is mapped into a user space process the owner should only be initialized if the fragment has just been created. Failure to do this will cause an error if another process is using the fragment when the mapping is done. Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com> Change-Id: I0fdeb195f5d1910ec70f6f56d772dd2b8cedab4c Reviewed-on: http://git.am.freescale.net:8181/9427 Reviewed-by: Haiying Wang <Haiying.Wang@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-05Add support for raw portal allocationRoy Pledge
Add support for allocation of raw (unconfigured) portals to the USDPAA kernel driver. This allows a USDPAA process to allocate a portal on behalf of another user. Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com> Change-Id: I5764ff1f8e46c8d22cb28367a70ce5a83a8ede85 Reviewed-on: http://git.am.freescale.net:8181/9381 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Vakul Garg <vakul@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-05fmd: add wake-on-lan support Mandy Lavi
Change-Id: I1898186679983caccc4e51a8674ee7909955e346 Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9076 Reviewed-by: Igal Liberman <Igal.Liberman@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com> (cherry picked from commit 19640982a1c57f9f81508f9fa15dcc6ec1841cb4) Change-Id: I1898186679983caccc4e51a8674ee7909955e346 Reviewed-on: http://git.am.freescale.net:8181/9385 Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-05fmd: change port_frame counter printout to unsigned Mandy Lavi
Change-Id: I308873aa47e84169f51840b10340da30a5689d36 Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/8638 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Nir Erez <nir.erez@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> (cherry picked from commit 6d27c61eccf7b68e5bdcb751f8bc829e9317da47) Change-Id: I308873aa47e84169f51840b10340da30a5689d36 Reviewed-on: http://git.am.freescale.net:8181/9384 Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com>
generated by cgit v0.10.2 at 2024-11-01 08:06:59 (GMT)