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2014-12-11powerpc/e6500rev2_defconfig: enable CONFIG_MTD_SPI_NOR_BASEChunhe Lan
Because m25p80.c depends on this option. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Change-Id: I599d54566a2b1c725bf34a08f1cf2ec446ab40c2 Reviewed-on: http://git.am.freescale.net:8181/22633 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
2014-12-11mtd: spi-nor: Add support for flag status register on Micron chipsChunhe Lan
Some new Micron SPI N25Q512 chips require reading the flag status register to determine when operations have completed. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Change-Id: I52a87e1ae55da75248108d6db39f027318bacf22 Reviewed-on: http://git.am.freescale.net:8181/22632 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
2014-12-11Integrate linux-pm treeRich Schmitt
Merge commit 'a8341457254bcbf5253109ac8c54904643f13e6f'
2014-12-11cpufreq: qoriq: Added workaround for T4240 errataTang Yuantian
T4240 has a errata A-008083: Dynamic frequency switch (DFS) can hang SoC when changing frequency of a cluster with active cores or snoop transactions. This patch provided a workaround for this errata by putting a cluster to PCL10 status before changing its frequency. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Change-Id: Ie25f25d2f75a02aec10b80b4012af018278b2aaa Reviewed-on: http://git.am.freescale.net:8181/22415 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com>
2014-12-11powerpc/cpu-hotplug: Support PCL10 state for e6500Zhang Zhuoyu
PCL10 is a cluster low power state in which cluster clock is gated off. For e6500-based platform, cluster will enter PCL10 state automatically when all cores of this cluster are offline. Signed-off-by: Hongtao Jia <hongtao.jia@freescale.com> Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com> Change-Id: Ibac7138ff685bbaeaed139629e9f2833e3148379 Reviewed-on: http://git.am.freescale.net:8181/22315 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com>
2014-12-11powerpc/cache: add cluster shared L2 cache operation for e6500Zhang Zhuoyu
E6500 cluster shared L2 configuration and control uses the same general formats as the integrated backside L2 cache provided in previous Freescale cores. But L2 cache control is accomplished through MMRs instead of SPRs. This patch provides cluster shared L2 cache operations for e6500. Signed-off-by: Hongtao Jia <hongtao.jia@freescale.com> Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com> Change-Id: I74d02c5bfda397723bb2feab251c7cc3c680105c Reviewed-on: http://git.am.freescale.net:8181/22314 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yuantian Tang <yuantian.tang@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com>
2014-12-11Fix e6500-based platform CPU hotplug issueZhang Zhuoyu
Fix thread 1 of core 0 online issue. Besides, put offline thread into PW10 state, give it a chance to enter PW20 state when threads of the same core are in PW10 state. Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com> Change-Id: I9018c4499f02b79f2ec684798c54bf3cfe6723de Reviewed-on: http://git.am.freescale.net:8181/21206 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com>
2014-12-11powerpc/fsl_msi: support vmpic msi with mpic 4.3Tudor Laurentiu
The new MSI block in MPIC 4.3 added the MSIIR1 register, with a different layout, in order to support 16 MSIR registers. The msi binding was also updated so that the "reg" reflects the newly introduced MSIIR1 register. Virtual machines advertise these msi nodes by using the compatible "fsl,vmpic-msi-v4.3" so add support for it. Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> (cherry picked from commit 67e35c3a79b7349a9b0dbe1dd0bf82def0296714) Change-Id: Idc79f35267300ad1fecc673798f1d865adea5f6f Reviewed-on: http://git.am.freescale.net:8181/21935 Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com> Tested-by: Matthew Weigel <Matthew.Weigel@freescale.com>
2014-12-11Deep sleep: fix build error on master cause by miss a macro defineWang Dongsheng
In the process of merging LS1 deepsleep and t104x deep sleep codes, we lost a macro define. add RCPM_BLOCK_OFFSET define for PowerPC deepsleep. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: Ic31cfea884f14b0731bb15bb40ecbb8134b4cc6b Reviewed-on: http://git.am.freescale.net:8181/22400 Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com> Tested-by: Matthew Weigel <Matthew.Weigel@freescale.com>
2014-12-11ifc : fix build error on master cause by nand driver miss a dependWang Dongsheng
Nand driver miss a depend, so add depends on MEMORY. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: Ia6d25836dff0f513eb63ee7089626f2728d26f3f Reviewed-on: http://git.am.freescale.net:8181/22414 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
2014-12-11Merge branch 'ls1-linux/LS1-SDK' to commit 2ec9fb2.Matthew Weigel
2014-12-11serial: fsl-lpuart: add lpuart32 Power Management supportJingchang Lu
This adds 32-bit register lpuart32 power management support, this also updates the 8-bit register lpuart resume function. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent upstream for review: https://patchwork.kernel.org/patch/5145341/ Change-Id: I0ed49f80d48407394cb0788f422374236da171b1 Reviewed-on: http://git.am.freescale.net:8181/21931 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11pm: ls1: diable QE device to make deep sleep workChenhui Zhao
The temporary workaround will disable the QE device before entering deep sleep. It makes deep sleep work, and should be removed after resolving the problem. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: Ib8c079ef67773eb3e058cf03331a0ed9c7707113 Reviewed-on: http://git.am.freescale.net:8181/21981 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11dmaengine: fsl-edma: add PM suspend/resume supportJingchang Lu
This adds eDMA power management suspend/resume support. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch depends on patch "dmaengine: fsl-edma: fixup reg offset and hw S/G support in big-endian model", and the upstream will be done after that patch upstreamed. Change-Id: I596bf0934ea1ee4292f2cc64f9db8996becca14c Reviewed-on: http://git.am.freescale.net:8181/21930 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi:dspi:revert devm_kzalloc for calltrace issueChao Fu
ac279ed96fd1262aa99c57246174(spi: fsl-dspi: Fix memory leak) converted the SPI device controller state to use devm_kzalloc(). Unfortunately, this is used against an unbound struct device, which results in the following when the device is eventually bound to its driver: ------------[ cut here ]------------ WARNING: CPU: 1 PID: 1 at drivers/base/dd.c:272 driver_probe_device+0x58/0x1d8() Modules linked in: CPU: 1 PID: 1 Comm: swapper/0 Not tainted 3.12.19-rt30+ #358 Backtrace: [<80010a08>] (dump_backtrace+0x0/0x100) from [<80010cb8>] (show_stack+0x18/0x1c) r6:804cef6e r5:00000009 r4:00000000 r3:00200140 [<80010ca0>] (show_stack+0x0/0x1c) from [<803e5c24>] (dump_stack+0x78/0x94) [<803e5bac>] (dump_stack+0x0/0x94) from [<8001c554>] (warn_slowpath_common+0x6c/0x90) r4:00000000 r3:60000113 [<8001c4e8>] (warn_slowpath_common+0x0/0x90) from [<8001c61c>] (warn_slowpath_null+0x24/0x2c) r8:e6ffc314 r7:805652e4 r6:8059498c r5:e6ffc200 r4:e6ffc200 [<8001c5f8>] (warn_slowpath_null+0x0/0x2c) from [<80231590>] (driver_probe_device+0x58/0x1d8) [<80231538>] (driver_probe_device+0x0/0x1d8) from [<80231740>] (__device_attach+0x30/0x4c) r7:00000000 r6:80231710 r5:e6ffc200 r4:805652e4 [<80231710>] (__device_attach+0x0/0x4c) from [<8022fc18>] (bus_for_each_drv+0x80/0x94) r5:e6ffc200 r4:00000000 [<8022fb98>] (bus_for_each_drv+0x0/0x94) from [<802314f8>] (device_attach+0x70/0x88) r6:e6ffc200 r5:e6ffc234 r4:e6ffc200 [<80231488>] (device_attach+0x0/0x88) from [<80230aa4>] (bus_probe_device+0x30/0xa0) r6:e6ffc200 r5:80565e3c r4:e6ffc200 r3:00000001 [<80230a74>] (bus_probe_device+0x0/0xa0) from [<8022ef0c>] (device_add+0x4f0/0x5c8) r6:e6ffc208 r5:00000000 r4:e6ffc200 r3:00000001 [<8022ea1c>] (device_add+0x0/0x5c8) from [<8026fb20>] (spi_add_device+0xe8/0x138) [<8026fa38>] (spi_add_device+0x0/0x138) from [<80270a78>] (spi_register_master+0x5e4/0x6c8) r7:00000000 r6:815b9ec8 r5:e6ffc200 r4:e6ff8000 [<80270494>] (spi_register_master+0x0/0x6c8) from [<8027196c>] (dspi_probe+0x268/0x314) [<80271704>] (dspi_probe+0x0/0x314) from [<80232668>] (platform_drv_probe+0x1c/0x20) [<8023264c>] (platform_drv_probe+0x0/0x20) from [<802315dc>] (driver_probe_device+0xa4/0x1d8) [<80231538>] (driver_probe_device+0x0/0x1d8) from [<802317cc>] (__driver_attach+0x70/0x94) r7:00000000 r6:80565f88 r5:e6d07e44 r4:e6d07e10 [<8023175c>] (__driver_attach+0x0/0x94) from [<8022fb60>] (bus_for_each_dev+0x7c/0x90) r6:8023175c r5:80565f88 r4:00000000 r3:8023175c [<8022fae4>] (bus_for_each_dev+0x0/0x90) from [<80231148>] (driver_attach+0x20/0x28) r6:e6fd6e00 r5:80563ab8 r4:80565f88 [<80231128>] (driver_attach+0x0/0x28) from [<80230cec>] (bus_add_driver+0xe4/0x248) [<80230c08>] (bus_add_driver+0x0/0x248) from [<80231c1c>] (driver_register+0xa4/0xe8) r7:80572440 r6:8052d464 r5:8053a1cc r4:80565f88 [<80231b78>] (driver_register+0x0/0xe8) from [<80232b80>] (__platform_driver_register+0x50/0x64) r5:8053a1cc r4:00000006 [<80232b30>] (__platform_driver_register+0x0/0x64) from [<8052d47c>] (fsl_dspi_driver_init+0x18/0x20) [<8052d464>] (fsl_dspi_driver_init+0x0/0x20) from [<800087fc>] (do_one_initcall+0x98/0x134) [<80008764>] (do_one_initcall+0x0/0x134) from [<80515c68>] (kernel_init_freeable+0x110/0x1d8) r9:0000009f r8:80572440 r7:80572440 r6:80541324 r5:8053a1cc r4:00000006 [<80515b58>] (kernel_init_freeable+0x0/0x1d8) from [<803e0838>] (kernel_init+0x14/0xec) r9:00000000 r8:00000000 r7:00000000 r6:00000000 r5:803e0824 r4:80572440 [<803e0824>] (kernel_init+0x0/0xec) from [<8000dd58>] (ret_from_fork+0x14/0x3c) r4:00000000 r3:00000000 ---[ end trace ef66b8df97ff1e33 ]--- Fix this by partially reverting the original commit. Signed-off-by: Chao Fu <B44548@freescale.com> Change-Id: I234e49f6cda0f5125d1b6d6990112b4ff3fe33a4 Reviewed-on: http://git.am.freescale.net:8181/21975 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11dts: ls1021a: add the RCPM node and change FPGA's compatibleChenhui Zhao
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: Ib0ecd4424f3d356fe1bcd687d3befd61527be5ab Reviewed-on: http://git.am.freescale.net:8181/21974 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm:dts:ls1021aqds: reduce the frequency for dspi flashChao Fu
Dspi flash is at45db021d on ls1021aqds board. Reduce its frequency to improve the data transfer stability. Signed-off-by: Chao Fu <B44548@freescale.com> Change-Id: If4e4d03d52fc28dea2dca3e6c6872024d3d1229a Reviewed-on: http://git.am.freescale.net:8181/21973 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11PCI: Layerscape: Fix PCIe link stateMinghuan Lian
The SCFG has been set bit-reverse as default, so the value of SCFG_PEXMSCPORTSR does not need do bitrev. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I6827bd2831176e3e0e968240f2d87f84a66e1225 Reviewed-on: http://git.am.freescale.net:8181/21970 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11esdhc: mmc: Add LS1021A SD support.Qiu Wujie
Signed-off-by: Qiu Wujie <B49553@freescale.com> --- This patch will be merged into the previous patch as below. URL: https://patchwork.kernel.org/patch/3976141/ Change-Id: I5c860dd5b58400aa25f9cce444ee8e94b4488cc4 Reviewed-on: http://git.am.freescale.net:8181/21965 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11esdhc: defconfig: Add LS1021A SD support.Qiu Wujie
Signed-off-by: Qiu Wujie <B49553@freescale.com> Change-Id: I30e6c4e9c5f6859aecc586b21d6426a802160699 Reviewed-on: http://git.am.freescale.net:8181/21964 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11tty: of-serial: fixup info uninitialized bugJingchang Lu
The kmalloc space may cause info->clk have random value if the dts node doesn't define clk property, thus cause all if(info->clk) condition wrong. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I309ff5cc881e00dc4475649e050263243027326c Reviewed-on: http://git.am.freescale.net:8181/21934 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11i2c: pca954x: put the mux to disconnected state after resumeJisheng Zhang
pca954x may be power lost during suspend, so after resume we also suffer the issue fixed by commit cd823db8b1161ef0d756514d280715a576d65cc3, "pca954x power-on default is channel 0 connected. If multiple pca954x muxes are connected to the same physical I2C bus, the parent bus will see channel 0 devices behind both muxes by default." What's more, when resume bootloader may also operate the mux, so the the channel connected after that may not be the one driver thought. We fix this problem by putting the mux to disconnected state and clearing last_chan in the resume hook. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> -- Cherry-pickded from linux.git: f5e596cd9f0ec6c03660fe4196d395bc3da919a4 Change-Id: I43da37cf2f854e023f5ff645d20134b919347142 Reviewed-on: http://git.am.freescale.net:8181/21929 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: pm: add deep sleep support for LS1Chenhui Zhao
LS1 supports deep sleep feature that can switch off most parts of the SoC when it is in deep sleep state. The DDR controller will also be powered off in deep sleep. Therefore, copy the last stage code to enter deep sleep to SRAM and run it with disabling MMU and caches. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> --- Patch Sent Upstream url: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296411.html Change-Id: If96ace364c21786cc88ea4979d7cbb4e177da0a2 Reviewed-on: http://git.am.freescale.net:8181/21920 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11fsl: fsm: use same interface to support T104x and LS1021AChenhui Zhao
T104x is based on PowerPC platform, LS1021A is based on ARM platform. Make T104x and LS1021A use same interface to set/clear EPU registers. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> --- Patch Sent Upstream url: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296410.html Change-Id: I00fdfc0b15e0f7cdc9ebc9970798d6669d7c22aa Reviewed-on: http://git.am.freescale.net:8181/21919 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM:LS1021aQDS: add CPU hotplug platform supportZhang Zhuoyu
This is only a CPU pseudo-hotplug, and incompatible with kexec mechanics. As per the discussion with Russell King in opensource community, CPU hotplug should reset the secondary core to be compatible with kexec. "In the kexec case, when the secondary CPU wakeup, the code it is executing can already been overwritten, which then means that the CPU ends up executing some random code instead." For LS102x platforms, resetting core can be realized, but come across cache coherence problem which is still unresolved, we will submit another patch to implement CPU hotplug by resetting core once cache coherence issue resloved. Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com> --- Patch Sent Upstream url: https://lkml.org/lkml/2014/9/26/422 Change-Id: I36509f99299f874ef0df891a33c907a749649527 Reviewed-on: http://git.am.freescale.net:8181/21918 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: 7861/1: cacheflush: consolidate single-CPU ARMv7 cache disabling codeNicolas Pitre
This code is becoming duplicated in many places. So let's consolidate it into a handy macro that is known to be right and available for reuse. Signed-off-by: Nicolas Pitre <nico@linaro.org> Acked-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> --- cherry-pick from 39792c7cf3111d69dc4aa0923859d8b929e9039f Change-Id: I9e2e9715425bcb8493c32b46ecb41c568d8235c5 Reviewed-on: http://git.am.freescale.net:8181/21917 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: 7885/1: Save/Restore 64-bit TTBR registers on LPAE suspend/resumeMahesh Sivasubramanian
LPAE enabled kernels use the 64-bit version of TTBR0 and TTBR1 registers. If we're running an LPAE kernel, fill the upper half of TTBR0 with 0 because we're setting it to the idmap here (the idmap is guaranteed to be < 4Gb) and fully restore TTBR1 instead of just restoring the lower 32 bits. Failure to do so can cause failures on resume from suspend when these registers are only half restored. Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> --- cherry-pick from f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8 Change-Id: I7e91a04ac2fda61f9c8a5e60d8d503d00a3cf9c1 Reviewed-on: http://git.am.freescale.net:8181/21910 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: 8053/1: kernel: sleep: restore HYP mode configuration in cpu_resumeLorenzo Pieralisi
On CPUs with virtualization extensions the kernel installs HYP mode configuration on both primary and secondary cpus upon cold boot. On platforms where CPUs are shutdown in idle paths (ie CPU core gating), when a CPU resumes from low-power states it currently does not execute code that reinstalls the HYP configuration, which means that the kernel cannot run eg KVM properly on such machines. This patch, mirroring cold-boot behaviour, executes position independent code that reinstalls HYP configuration and drops to SVC mode safely on warmboot, so that deep idle states can be enabled in kernel running as hosts on platforms with power management HW. Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Dave Martin <dave.martin@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Nicolas Pitre <nico@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> --- cherry-pick from 0e0779da2233f2dfc85e9c3a6ea142476d326811 Change-Id: Iafed877cc49e799d7c31f1cb265a0b38be708c88 Reviewed-on: http://git.am.freescale.net:8181/21909 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi:Kconfig:Add DSPI in LS1021 supportChao Fu
DSPI also is a module in LS1021. Add the dependence SOC_LS1021 for DSPI. Signed-off-by: Chao Fu <B44548@freescale.com> Change-Id: Id48cc01c7756f9b3a977f4f5478fa018897952f8 Reviewed-on: http://git.am.freescale.net:8181/21907 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm:dtsi:ls1021a:Add the DSPI transfer mode property in DSPI nodeChao Fu
DSPI new driver can select transfer mode(tcfq/eoq) to work. The property will be read from dtsi node. Add the property tcfq-mode for LS1021a. Signed-off-by: Chao Fu <B44548@freescale.com> Change-Id: Ib659338777a4a8a5fdef7914c556c3ca8b4c483d Reviewed-on: http://git.am.freescale.net:8181/21908 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ASFIPSEC: Porting ASF to LS1.Nikhil Agarwal
Adding PDB endianness independent. Signed-off-by: Nikhil Agarwal <Nikhil.Agarwal@freescale.com> Change-Id: I44bfc921ba1460dd2785c21252898b55953d8385 Reviewed-on: http://git.am.freescale.net:8181/17497 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Sandeep Malik <Sandeep.Malik@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com> (cherry picked from commit 16e2ab4fab053e020d4857f14fe8bd35616ad304) Reviewed-on: http://git.am.freescale.net:8181/21354
2014-12-11audio: dts: Add dts nodes on LS1021AQDS/TWRAlison Wang
This patch adds dts nodes for audio support on LS1021AQDS/TWR. Signed-off-by: Alison Wang <alison.wang@freescale.com> Change-Id: I5e98a2377a7230598401ad932c4016951435b240 Reviewed-on: http://git.am.freescale.net:8181/21061 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11cpufreq: qoriq: Make the driver usable on all QorIQ platformsTang Yuantian
Freescale introduced new ARM core-based SoCs which support dynamic frequency switch feature. DFS on new SoCs are compatible with current PowerPC CoreNet platforms. In order to support those new platforms, this driver needs to be slightly adjusted. The main changes include: 1. Changed the names of driver and functions in driver. 2. Added two new functions get_cpu_physical_id() and get_bus_freq(). 3. Used a new way to get all the CPUs which sharing clock wire. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> --- http://patchwork.ozlabs.org/patch/400406/ Change-Id: I29fc5fefd0860db5ee531844d1218a6b70098dfe Reviewed-on: http://git.am.freescale.net:8181/21874 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11clock: redefine variable clocks_per_pll as a struct memberTang Yuantian
redefine variable clocks_per_pll as a struct member If there are multiple PLL clock nodes, this variable will get overwritten. Redefined it as a struct member can avoid this. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Change-Id: I892993ffaf046f333c564170a5cac7c845ef9ba8 Reviewed-on: http://git.am.freescale.net:8181/21873 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11dts: ls1021a: updated the soc nodeTang Yuantian
Added device_type property to soc node to facilitate its use. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Change-Id: I4c50770215608f8ca718e78072a28f69afdf1bc2 Reviewed-on: http://git.am.freescale.net:8181/21690 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11dts: ls1021a: updated the clockgen nodeTang Yuantian
Fixed some error in clockgen node. This patch also added clock source to CPU nodes to support CPU frequency switch dynamically. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Change-Id: I2d40c3bc9c766d62d9cb8a3c00b9d5e1c2e65f41 Reviewed-on: http://git.am.freescale.net:8181/21689 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11qe-tdm: modify qe-tdm for both arm and powerpcZhao Qiang
ls1021 support qe ip block and it is arm, so modify qe-tdm code to adapt both arm and powerpc Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: Ie64cef1dc6cd915388c089d1359c681da67c6fba Reviewed-on: http://git.am.freescale.net:8181/21869 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ls1021aqds: add qe node to ls1021aqds dtsZhao Qiang
add qe node(qe-tdm and qe-uart) into ls1021a-qds.dts Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I1ab52c2330246e807fd4c96103d2c063b6d8d8ba Reviewed-on: http://git.am.freescale.net:8181/21868 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ls102xa: audio: Workaround for SAI data transfer endian issueAlison Wang
Transmit Data Register(TDR) used as the destination address of EDMA transaction is in big-endian mode. The audio data in memory and EDMA transaction are in little-endian mode. For S16_LE format data, a workaround is to swap the original 16-bit data, and then write into the higher 16 bit of TDR. Signed-off-by: Alison Wang <alison.wang@freescale.com> Change-Id: Ib15832743e9a4c69792f2dad4cb00fbbc1d2daaa Reviewed-on: http://git.am.freescale.net:8181/21063 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: Add support for non RX-FIFO mode and conditional ERRATA ↵Bhupesh Sharma
ERR005829 handling This patch adds support for non RX-FIFO (legacy) mode and conditional ERRATA ERR005829 handling in flexcan driver. Both these features are now selectable via Kconfig entries and hence can be turned-on/off as per a SoC feature set availability. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: I2a5a4970b7e5b18a45fb421f1c0d008ad5a3b0f8 Reviewed-on: http://git.am.freescale.net:8181/21856 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ls1021a/dts: Add device nodes for FlexCAN IP instancesBhupesh Sharma
This patch adds the device nodes for 4 FlexCAN IP instances available on LS1021A SoC in the ls1021a.dtsi file and enables only the first two instances which are supported on the QDS board in ls1021a-qds.dts file. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> --- Previous version of this patch under review upstream: http://patchwork.ozlabs.org/patch/363588/ Will re-spin the patch with the DTS Change-Id: I592e5f8562ad173801a53433aec9a91b00ba8bb0 Reviewed-on: http://git.am.freescale.net:8181/21855 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11net: can: Remodel FlexCAN register read/write APIs for BE instancesBhupesh Sharma
The FlexCAN IP on certain SoCs like (Freescale's LS1021A) is modelled in a big-endian fashion, i.e. the registers and the message buffers are organized in a BE way. More details about the LS1021A SoC can be seen here: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=LS1021A&nodeId=018rH325E4017B# This patch ensures that the register read/write APIs are remodelled to address such cases, while ensuring that existing platforms (where the FlexCAN IP was modelled in LE way) do not break. Tested on LS1021A-QDS board. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: Ibaa6b1816670537466b227b5032be73338435c03 Reviewed-on: http://git.am.freescale.net:8181/21854 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: Add ls1021a flexcan device entryBhupesh Sharma
This patch adds ls1021a flexcan device entry to the flexcan driver code. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> --- Previous version of this patch under review upstream: http://patchwork.ozlabs.org/patch/363588/ Change-Id: Ie01ec4583e1dc4efd90eb05e69ed45ae351d9d4e Reviewed-on: http://git.am.freescale.net:8181/21853 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11[fsl-only] can: flexcan: Remove can_change_mtu calls as this is not ↵Bhupesh Sharma
supported in 3.12 kernel Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: I731e457b0b29a794c752116921b119c37514758a Reviewed-on: http://git.am.freescale.net:8181/21852 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: increase FLEXCAN_MCR_MAXMB() macro to 7 bitsMarc Kleine-Budde
This patch increases the mask in the FLEXCAN_MCR_MAXMB() to 7 bits as in the newer flexcan cores the MAXMB field is 7 bits wide. Reported-by: David Jander <david@protonic.nl> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: 4c728d804c4b9d1ae7f76e8f32c419bc21a6e540 Change-Id: If7f3817dced00e4864da29579ff377788e9ee4ad Reviewed-on: http://git.am.freescale.net:8181/21851 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: put TX mailbox into TX_INACTIVE mode after tx-completeMarc Kleine-Budde
After sending a RTR frame the TX mailbox becomes a RX_EMPTY mailbox. To avoid side effects when the RX-FIFO is full, this patch puts the TX mailbox into TX_INACTIVE mode in the transmission complete interrupt handler. This, of course, leaves a race window between the actual completion of the transmission and the handling of tx-complete interrupt. However this is the best we can do without busy polling the tx complete interrupt. Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: de5944883ebbedbf5adc8497659772f5da7b7d72 Change-Id: Icfa9443f03246feee26868b9ad17147b2352c9fd Reviewed-on: http://git.am.freescale.net:8181/21850 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: implement workaround for errata ERR005829David Jander
This patch implements the workaround mentioned in ERR005829: ERR005829: FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process. Workaround: The workaround consists of two extra steps after setting up a message for transmission: Step 8: Reserve the first valid mailbox as an inactive mailbox (CODE=0b1000). If RX FIFO is disabled, this mailbox must be message buffer 0. Otherwise, the first valid mailbox can be found using the "RX FIFO filters" table in the FlexCAN chapter of the chip reference manual. Step 9: Write twice INACTIVE code (0b1000) into the first valid mailbox. Signed-off-by: David Jander <david@protonic.nl> Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: 25e924450fcb23c11c07c95ea8964dd9f174652e Change-Id: I504198f3b5aaba2c0277b596e925ce3bb17a2258 Reviewed-on: http://git.am.freescale.net:8181/21849 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: correctly initialize mailboxesBhupesh Sharma
Apparently mailboxes may contain random data at startup, causing some of them being prepared for message reception. This causes overruns being missed or even confusing the IRQ check for trasmitted messages, increasing the transmit counter instead of the error counter. This patch initializes all mailboxes after the FIFO as RX_INACTIVE. Signed-off-by: David Jander <david@protonic.nl> Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: fc05b884a31dbf259cc73cc856e634ec3acbebb6 Change-Id: I0757258cb27cb2dec26e8afa219b512bba80be4b Reviewed-on: http://git.am.freescale.net:8181/21848 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: mark TX mailbox as TX_INACTIVEMarc Kleine-Budde
This patch fixes the initialization of the TX mailbox. It is now correctly initialized as TX_INACTIVE not RX_EMPTY. Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: c32fe4ad3e4861b2bfa1f44114c564935a123dda Change-Id: I3058828c8f0786726589a8fc05a5cc8467644e1b Reviewed-on: http://git.am.freescale.net:8181/21847 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: avoid calling usleep_range from interrupt contextDavid Jander
Apparently can_restart() runs from a (timer-) interrupt and can call flexcan_chip_[en|dis]able(), so avoid using usleep_range() Signed-off-by: David Jander <david@protonic.nl> Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: 8badd65e48c90d66587359d5329c2813088c0f50 Change-Id: I44fef82e8b413d6751a23fcb05d4a9f39ecb385a Reviewed-on: http://git.am.freescale.net:8181/21846 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
generated by cgit v0.10.2 at 2024-11-17 03:19:01 (GMT)