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Change raw read/write accessors to ioread/writebe32 for big endian registers
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Change-Id: I75e181fc235f40aba7aa0d9db8f18c0783b04f82
Reviewed-on: http://git.am.freescale.net:8181/21818
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Set USB_EN bit to select ULPI phy for USB controller version 2.5
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Change-Id: I22fd6921d264d64f59d795d81f82ea89214862d9
Reviewed-on: http://git.am.freescale.net:8181/21817
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Set DMA_MASK of usb platform device
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Change-Id: I7d6387f3b95b6ec7c1999e14801dc4cfec7b016d
Reviewed-on: http://git.am.freescale.net:8181/21816
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Change Power architecture specific APIs such as in_be32/out_be32
for registers read/write. Instead using ioread/writebe32 which are
defined for power as well as arm architecture
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Change-Id: Ic5ecf4cb048dc4a6bae81bc0789b9bdb7d5c6ded
Reviewed-on: http://git.am.freescale.net:8181/21815
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Remove compilation error from USB driver while compiling for
architectures other than PPC
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Change-Id: Icc9d648f08ec5affb7b58374faef2c6e3b539182
Reviewed-on: http://git.am.freescale.net:8181/21814
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Remove USB errata checking code from driver. Applicability of erratum
is retreived by reading corresponding property in device tree.
This property is written during device tree fixup.
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Change-Id: I78a8b51a4b647d43f942666800bae4d515b15e70
Reviewed-on: http://git.am.freescale.net:8181/21813
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Change-Id: I501144de5deaecb1bbbe913fc1ef82e8102d84a3
Reviewed-on: http://git.am.freescale.net:8181/21811
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Change-Id: Ib16b8e2466757d782ec4bb5e8549f2dcb9208e32
Reviewed-on: http://git.am.freescale.net:8181/21801
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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LS1021a-qds has the same controller as GPIO on
powerpc platform(MPC8XXX), so remove
GPIO_MXC and add the one for GPIO_MPC8XXX
Enable gpio as default
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Change-Id: I13531087c312ef9fa3bb607b5202592d13b29727
Reviewed-on: http://git.am.freescale.net:8181/21800
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch adds support for GPIOs found on
Freescale's Layerscape architectures
It also makes mutual exclusion with ARCH_MXC,
since the GPIO controller on LayerArch
is different than MXC
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Change-Id: I5601038b2fbca3e7eb7f5226d02db4a2a7098bf8
Reviewed-on: http://git.am.freescale.net:8181/21799
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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LS1021a-qds has the same ip block/controller as
GPIO on powerpc platform(MPC8XXX).
So use portable i/o accessors, as in_be32/out_be32
accessors are Power architecture specific whereas
ioread/writebe32 are available in other architectures.
GPIO controller's registers are big endian, the
accessors ioread32be/iowrite32be matches this one
and portable on powerpc as well on ARM.
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Change-Id: I2d68fbbfb7478f2cdb9ec4e334ad81f82d3bfb89
Reviewed-on: http://git.am.freescale.net:8181/21798
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Correct qspi flash information on ls1021a-qds board.
And remove flash partion in node, it is not useful.
Signed-off-by: Chao Fu <B44548@freescale.com>
Change-Id: I8b2dc47446c5d54ce12e3d7d138fa9d9a3b9ba6c
Reviewed-on: http://git.am.freescale.net:8181/21364
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Correct qspi flash information on ls1021a-qds board.
And remove flash partion in node, it is not useful.
Signed-off-by: Chao Fu <B44548@freescale.com>
Change-Id: Ib9b3964127984457032f73be53bbfc847cf438bf
Reviewed-on: http://git.am.freescale.net:8181/21360
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The new QSPI driver add DDR read mode,
so add qspi-memory map for QSPI access in DDR mode in dts node.
Modify qspi node compatible for LS1 paltform.
Signed-off-by: Chao Fu <b44548@freescale.com>
Change-Id: Ia92dda63bf857b845767ae62f2c7eb9a84371aa1
Reviewed-on: http://git.am.freescale.net:8181/21356
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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CAAM.
CAAM's memory is broken into following address blocks:
Block Included Registers
7 QI registers
Size of the above stated block varies in various platforms. The block size can be 4K or 64K.
The block size can be dynamically determined by reading CTPR register in CAAM.
This patch fixes the issues related to the dynamic initialization of the QI block
address based on the value read from this register.
Signed-off-by: Nitesh Narayan Lal <b44382@freescale.com>
Change-Id: I11d6cb2814ee4eb1c966773636bf6bd0ff986811
Reviewed-on: http://git.am.freescale.net:8181/20999
Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Change-Id: I3958f741a54691a882323a95b56bc7d8cb1311c4
Reviewed-on: http://git.am.freescale.net:8181/21179
Reviewed-by: Sandeep Malik <Sandeep.Malik@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
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Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: Ie34306997587de53d71a44d643989a3808644a4c
Reviewed-on: http://git.am.freescale.net:8181/21178
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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With tx snooping enabled the eTSEC Tx DMA stops in mid-traffic
at this point. Remove the Tx snooping support from gianfar for
now.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: I89018d6cd044e86c49c64b5343c6435ab38fcbf2
Reviewed-on: http://git.am.freescale.net:8181/21177
Reviewed-by: Sandeep Malik <Sandeep.Malik@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Use of_property_read*() to get arch endian consistent
property values. Do some refactoring in the process.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: I9ff10b73854a82333cfc830fed4b921a73519806
Reviewed-on: http://git.am.freescale.net:8181/21176
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Use conversion macros to correctly access the BE
fields of the Rx and Tx Frame Control Block on LE CPUs.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: Ieb5b1d44449f6acbfcc39ba2a0d8cd23669b5d4c
Reviewed-on: http://git.am.freescale.net:8181/21175
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Use conversion macros to correctly access the BE
fields of the Rx and Tx Buffer Descriptors on LE CPUs.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: If8674c721fb8a9cec22b6921d08680c6afb531e2
Reviewed-on: http://git.am.freescale.net:8181/21174
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add PM support for DCU driver using callback function suspend
and resume in .driver.pm of platform_driver.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
--
The first DRM version will be send out to the community
before 15 Dec 2014.
Change-Id: I959eec05d100f212d5d61faaf114fe99618fae19
Reviewed-on: http://git.am.freescale.net:8181/21572
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add PM support for FTM pwm driver using callback function suspend
and resume in .driver.pm of platform_driver.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
upstream link: http://patchwork.ozlabs.org/patch/399748/
it is under discussion.
Change-Id: I0c558dffdb9c40d66e4a55d5ce3e8685fe4f1ecf
Reviewed-on: http://git.am.freescale.net:8181/21350
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch is to prepare for adding PM support for FTM pwm driver
using callback function suspend and resume in .driver.pm of
platform_driver.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
upstream link: http://patchwork.ozlabs.org/patch/399752/
it is under discussion.
Change-Id: I517f27b696b6eeeae880e3bd71b122995194127f
Reviewed-on: http://git.am.freescale.net:8181/21349
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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A given application may not use all the peripherals on the device.
In this case, it may be desirable to disable unused peripherals.
DCFG provides a mechanism for gating clocks to IP blocks that are
not used when running an application.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
This patch has been sent out to the community and under discussion:
URL:http://www.spinics.net/lists/arm-kernel/msg370133.html
Change-Id: Iedf07d12955b3fa011a0bef27236f73405cefb44
Reviewed-on: http://git.am.freescale.net:8181/21604
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Since the Freescale SAI, ESAI and SPDIF are using the regmap-mmio,
there needs a select of REGMAP_MMIO in the Kconfig to ensure that
regmap-mmio is actually enabled.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
---
This patch is pulled back from upstream with few backport changes:
commit 7d150c60f1a29c62e115e0ee2a5678400e724873
Change-Id: I61f6b089ff036b249976c1081afaa04974caca5e
Reviewed-on: http://git.am.freescale.net:8181/21478
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Chao Fu <B44548@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The regmap framework has one feature of register cache, which
will be more easy to add big endian mode and PM support.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
--
The first DRM version will be send out to the community
before 15 Dec 2014.
Change-Id: I3aa3c30f4ab42b64b80669b483b45a62ae31d6bb
Reviewed-on: http://git.am.freescale.net:8181/21571
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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No matter what times the FTM pwm is enabled, the use_count will
always be one.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
upstream link: http://patchwork.ozlabs.org/patch/399746/
it is under discussion.
Change-Id: I6f139f1b3fd5dd8f3a4fda729c348aaab9bf66bd
Reviewed-on: http://git.am.freescale.net:8181/21348
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add power management operations(suspend and resume) as part of
dev_pm_ops for IMX2 watchdog driver.
If PM will be supported, please make sure that the wdev->clk
could disable the watchdog's counter input clock source or can
mask watchdog's reset request to the core.
If watchdog is still used by consumers and resumes from deep
sleep state, we need to restart the watchdog again without
enabling the timer.
If watchdog been has started --> stopped by the consumers and
resumes from non-deep sleep state, then start the timer again.
If watchdog has been started --> stopped by the consumers and
resumes from deep sleep state, will do nothing. The watchdog
will be restarted by consumers next time to be used.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
This patch has been sent out to community under discussing.
The mails URL: https://lkml.org/lkml/2014/9/23/410
Change-Id: I507825f3e063e7f8b67496d9cb4894b607eb2535
Reviewed-on: http://git.am.freescale.net:8181/21409
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This watchdog driver will be working on IMX2+, Vybrid, LS1, LS2+
platforms, and will be in different endianness mode in those SoCs:
SoCs WDT endian mode
------------------------------------
IMX2+ LE
Vybird LE
LS1 BE
LS2 LE
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
---
This patch is pulled back from upstream:
commit f728f4bfc495a588abda4661c09595112677be25
Change-Id: Ibc1ae6c45d60fb947b26ff8ea7d5bf220b4c6b10
Reviewed-on: http://git.am.freescale.net:8181/21408
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Convert the imx2_wdt driver to the new watchdog core api.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Cc: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
---
This patch is pulled back from upstream:
commit faad5de0b10484d3dc2ed2a803b2b82f6b1b81ee
Change-Id: Ib102c904235a6771797a1d97622a7a9715a89962
Reviewed-on: http://git.am.freescale.net:8181/21407
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
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I just can't find any value in MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR)
and MODULE_ALIAS_MISCDEV(TEMP_MINOR) statements.
Either the device is enumerated and the driver already has a module
alias (e.g. PCI, USB etc.) that will get the right driver loaded
automatically.
Or the device is not enumerated and loading its driver will lead to
more or less intrusive hardware poking. Such hardware poking should be
limited to a bare minimum, so the user should really decide which
drivers should be tried and in what order. Trying them all in
arbitrary order can't do any good.
On top of that, loading that many drivers at once bloats the kernel
log. Also many drivers will stay loaded afterward, bloating the output
of "lsmod" and wasting memory. Some modules (cs5535_mfgpt which gets
loaded as a dependency) can't even be unloaded!
If defining char-major-10-130 is needed then it should happen in
user-space.
Signed-off-by: Jean Delvare <jdelvare@suse.de>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Mike Frysinger <vapier.adi@gmail.com>
Cc: Wan ZongShun <mcuos.com@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Zwane Mwaikambo <zwane@arm.linux.org.uk>
Cc: Jim Cromie <jim.cromie@gmail.com>
---
This patch is pulled back from upstream:
commit 487722cf2d66126338217896642bd5eec832c34b
Change-Id: I41ef1836903d85ee832a2486ee75d5cd7eecb369
Reviewed-on: http://git.am.freescale.net:8181/21406
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Enable auto loading by udev when imx2_wdt is compiled as a module.
Signed-off-by: Niels de Vos <ndevos@redhat.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
---
This patch is pulled back from upstream:
commit 813296a1a209baaf1471c360591946edd795bcbe
Change-Id: Ice56b9bbe3a893c92a61aa66e1f23f81cf730850
Reviewed-on: http://git.am.freescale.net:8181/21405
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Revert this to prepare for pulling many other open source patches.
This reverts commit 74b86665568cc09a0a2ba37dba11ec7f71295424.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Change-Id: Icd4b64a9e263b9aee317efe626d3853865fccf71
Reviewed-on: http://git.am.freescale.net:8181/21404
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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IFC registers can be of type Little Endian
or big Endian depending upon Freescale SoC.
Here SoC defines the register type of
IFC IP.So update accessors functions with
common IFC accessors functions to take
care both type of endianness.
IFC IO accressor are set at run time based
on IFC IP registers endianness.IFC node in
DTS file contains information about
endianness.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
---
This patch is under reviewing at url - https://www.mail-archive.com/linux-kernel%40vger.kernel.org/msg741449.html
Change-Id: Ib6d4669a94afa50e71ce522a008232fa21b0bc19
Reviewed-on: http://git.am.freescale.net:8181/20971
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Freescale IFC controller has been used for mpc8xxx.
It will be used for ARM-based SoC as well. This patch
moves the driver to driver/memory and fix the header
file includes.
Also remove module_platform_driver() and instead call
platform_driver_register() from subsys_initcall()
to make sure this module has been loaded before
MTD partition parsing starts.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
---
Cherry-picked from:d2ae2e20fbdde5a65f3a5a153044ab1e5c53f7cc
Change-Id: I3cc83c716adf27a4988b818d57706980dbbefdea
Reviewed-on: http://git.am.freescale.net:8181/20970
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
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Allocation of Buffer Descriptors to SRAM is not supported
by the ARM based LS1 platform. The CACHE_SRAM feature is
PPC specific (mpc85xx SoC family more exactly). The mpc85xx
CACHE_SRAM driver lies in the PPC architecture folders, so
the API calls in gianfar must be excluded from non-PPC builds,
otherwise obviously there will be compile errors on ARM (LS1).
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: I5594ec8fd104794d183426b973d35309d44b64e2
Reviewed-on: http://git.am.freescale.net:8181/21173
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Replace PPC specific eieio() with arch independent wmb()
for other architectures, i.e. ARM.
The eieio() macro is not defined on ARM and generates
build error.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
Cherry-picked from commit: d55398ba81139bc826a8c2417a01280e99f08cf3
---
Change-Id: I6cd072cf6e28fc81a686afab8bc42921da2e5020
Reviewed-on: http://git.am.freescale.net:8181/21172
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Use arch independent code to replace the powerpc dependent
spin_event_timeout() from gfar_halt_nodisable().
Added GRS/GTS read accessors to clean-up the implementation
of gfar_halt_nodisable().
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
Cherry-picked from commit: a4feee89ce4590c7a4aead49ca5a4853dc6ea5dc
---
Change-Id: Ie83fed01fbf4fac1593a7e5de62f90cbdad0b50f
Reviewed-on: http://git.am.freescale.net:8181/21171
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Fix the 32-bit memory access that is not endian safe,
i.e. not giving the desired byte layout for a LE CPU:
tempval = *((u32 *) (tmpbuf + 4)), where 'char tmpbuf[]'.
Get rid of rendundant local vars (tmpbuf[] and idx) and
forced casts. Cleanup comments.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
Cherry-picked from commit: 83bfc3c4765c35ef0dfff8a3d6dedab88f3f50ea
---
Change-Id: Id53e47096164a4829c87559a77be32fc2496e3a6
Reviewed-on: http://git.am.freescale.net:8181/21170
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This excludes the PPC specific instructions for PPC based SoC
(MPC85xx family) version identification from ARM builds.
The PPC specific macro mfspr() from asm/reg.h is not defined
by the ARM architecture.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
Cherry-picked from commit: d6ef0bcce386531f250a8abee3c3595214ea1629
---
Change-Id: Ib61a944298c0b30c77b77089d0d960a82510a856
Reviewed-on: http://git.am.freescale.net:8181/21169
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Include linux/of_address.h for of_iomap() and linux/of_irq.h
for irq_of_parse_and_map().
This wasn't an issue for PPC, because these were implicitly
included from asm/prom.h (via linux/of.h) for PPC builds only.
ARM builds need these includes explicitly.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
Cherry-picked from commit: fd31a9528800b52c7a56a9cfa0af30b44dcfb0c9
Change-Id: I171a0f7025d262bc96bd6cd4fedec96a43b63b4e
Reviewed-on: http://git.am.freescale.net:8181/21168
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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spin_event_timeout() is PPC dependent, use an arch independent
equivalent instead.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
---
Cherry-picked from commit: e4b081f543030fc0b23d2cd7d1f6e3ac69d7f47f
---
Change-Id: I0eee676e14600fbea105f888dfecb00f32309dad
Reviewed-on: http://git.am.freescale.net:8181/21167
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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in_be32()/out_be32() are not defined by ARM.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
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Cherry-picked from commit: f5bbd262e70ff2355ce4284b0ad9eaf93fb5e374
---
Change-Id: I0da4e74026f112181299880744dc1ccef474a9dc
Reviewed-on: http://git.am.freescale.net:8181/21166
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
The first DRM version will be send out to the community
before 30 November 2014.
Change-Id: Ia5538da4db87431fd80ffaacc07c201d20a8bc2b
Reviewed-on: http://git.am.freescale.net:8181/19651
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Jason Chen <b02280@freescale.com>
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
The maintainer or many other people all have strong opinions to
add HDMI driver based the DRM framework.
The mails URL:
https://lkml.org/lkml/2014/9/5/37
The first DRM version of HDMI will be send out to the community
before 30 November 2014.
Change-Id: I2cce28cb70dd0be6e8bc09c2ab7f5cabbe98dbdf
Reviewed-on: http://git.am.freescale.net:8181/19650
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch adds DCU node in SoC level DTS for Freescale LS1021A-TWR.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
The first DRM version will be send out to the community
before 30 November 2014.
Change-Id: I74671a92d530699be6868f7f1591eadbd40a6879
Reviewed-on: http://git.am.freescale.net:8181/19649
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
---
The first DRM version will be send out to the community
before 30 November 2014.
Change-Id: I6a20f9f5c1b8b8c596e635b25aa37055e23f82a7
Reviewed-on: http://git.am.freescale.net:8181/19648
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The Display Controller Unit (DCU) module is a system master that
fetches graphics stored in internal or external memory and displays
them on a TFT LCD panel. A wide range of panel sizes is supported
and the timing of the interface signals is highly configurable.
Graphics are read directly from memory and then blended in real-time,
which allows for dynamic content creation with minimal CPU intervention.
The features:
(1) Full RGB888 output to TFT LCD panel.
(2) For the current LCD panel, WQVGA "480x272" is supported.
(3) Blending of each pixel using up to 4 source layers dependent on
size of panel.
(4) Each graphic layer can be placed with one pixel resolution in
either axis.
(5) Each graphic layer support RGB565 and RGB888 direct colors without
alpha channel and BGRA8888 direct colors with an alpha channel.
(6) Each graphic layer support alpha blending with 8-bit resolution.
Signed-off-by: Alison Wang <b18965@freescale.com>
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
The maintainer and many other people all have strong opinions to
add DCU driver based the DRM framework.
The mails URL:
http://lists.infradead.org/pipermail/linux-arm-kernel/2013-September/197863.html
The first DRM version of DCU will be send out to the community
before 30 November 2014.
Change-Id: I9feb7c9b975431a1bb3906eb955dcf6ae09654eb
Reviewed-on: http://git.am.freescale.net:8181/19647
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Chao Fu <B44548@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Ls1021a-qds has the same ip block as esdhc on powerpc platform.
But they have diferent endian mode and different IO entry.
So we change the IO entry to generic IO to support working on
different architecture with different endian mode. Also add some
properties to support esdhc on ls1021a-qds.
Signed-off-by: Qiu WeiJie <B49553@freescale.com>
Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
---
This patch has sent to linux-mmc maillist.
URL: https://patchwork.kernel.org/patch/3976141/
Change-Id: I4959b07bf9e38a442316f0f45425018fa7d6f579
Reviewed-on: http://git.am.freescale.net:8181/14824
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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