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2015-11-04dev-exporting dev functions to support ceetmHemant Agrawal
Exporting functions to be used by CEETM for tcp termination handling. TCP packets may come with GSO options. Signed-off-by: Sahil Malhotra <sahilmalhotra@freescale.com>
2015-11-03crypto: caam - enable LARGE_BURST for enhancing DMA transactions sizeHoria Geantă
Increasing CAAM DMA engine transaction size either -reduces the number of required transactions or -adds the ability to transfer more data with same transaction count Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
2015-11-03crypto: caam - make write transactions bufferable on PPC platformsHoria Geantă
Previous change (see "Fixes" tag) to the MCFGR register clears AWCACHE[0] (which is "1" at POR). For PPC-based platforms, this makes all writes non-bufferable, causing a performance drop. Rework previous change such that MCFGR[AWCACHE] is set to: -4'b0001 (default value at POR) for PPC-based platforms -4'b0011 (default value at POR + AWCACHE[1]) for ARM-based platforms Fixes: bcd586241449 ("crypto: caam - fix snooping for write transactions") Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
2015-11-02fmd: fix locks in ModifyKey functionMandy Lavi
Fixing an issue that occurs when there are two root ccnodes and both of them point to the same miss ccnode Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
2015-11-02fmd: support aging in CCMandy Lavi
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
2015-11-02pci/layerscape: Do not check link statusMinghuan Lian
The PCIe controller should be fully initialized in spite of link status controller and the designware driver will check it before accessing the PCIe device. So we do not need to check link status and the patch removed the related code. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
2015-10-30asf_tcp_nf: Patch to correct typecast in tcp timestamp copy.Alok Makhariya
Earlier tcp timestamp is typecasted using long. But timestamp is of 4 byte. For 64-bit machine, long is 8 byte. This is incorrect So it is typecasted using int. Signed-off-by: Alok Makhariya <B46187@freescale.com>
2015-10-26Revert "gianfar: Add dma transfer endian property support"Claudiu Manoil
This reverts commit 20af0dc3a4003cdfaaac974dfe131e030b857dcd. Revert this non-upstreamable patch (DMACTRL[LE] hack) from SDK1.9, to sync gianfar with following usptream u-boot fix: git.denx.de/?p=u-boot/u-boot-arm.git/ commit: ebe4c1e6469444753bd2ba93fe63e6183cf2905c (“ls102xa: etsec: Use proper settings for BE BDs”). Details about the fix are documented by this uboot commit. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
2015-10-23kconfig-asf : asf_qos disabled with asf by defaultAlok Makhariya
asf_qos feature to be only available for non-dpaa platform asf_qos will not be enabled by enabling ASF. asf_linux_qos may be used for dpaa platforms. Signed-off-by: Alok Makhariya <B46187@freescale.com>
2015-10-23dev-asf-qos - correcting the qos hooks for dpaa linux qosAlok Makhariya
ASF_EGRESS_QOS should be disabled for DPAA platforms. ASF_LINUX_QOS may be enabled for DPAA platforms. the l2blob shall be offloaded from ceetm instead of hook from the dev.c Signed-off-by: Alok Makhariya <B46187@freescale.com>
2015-10-21dpaa_eth: fix bpool seeding for advanced driversMadalin Bucur
On 32 bit kernels using size_t truncated the 40 bit addresses. Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com>
2015-10-21net, gianfar, rt: Update TX_TIMEOUT to 5HZAbhimanyu
Increased TX_TIMEOUT to 5HZ to improve performance in case of Real-Time. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Abhimanyu <abhimanyu@freescale.com>
2015-10-21net, rt: limit net_rx napi calls in threaded ISR contextAbhimanyu
-In a PREEMPT_RT with CONFIG_PREEMPT_RT_FULL configuration enabled, some of Interrupt Handler runs in context of threaded ISR. And if this threaded ISR raises a particular softirq, then that calls __raise_softirq_irqoff() function which mark the softirq ready to be executed while exiting ISR in context of ISR only. -So, net_rx_action() function is called in context of threaded ISR if NET_RX_SOFTIRQ softirq is raised by that particular ISR. -net_rx_action is balancing scheduling among napis by using time-out of 2 jiffies for particular napi. On timeout , it calls __raise_softirq_irqoff(). -In case of RT kernel, __raise_softirq_irqoff() again makes the NET_RX_SOFTIRQ ready. So it is called again and again until the packet ring is emptied.This creats a starvation condition for other threads. -This patch removes calling __raise_softirq_irqoff() again while exiting net_rx_action() Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Abhimanyu <abhimanyu@freescale.com>
2015-10-20powerpc/t1040/dts: Add interrupts for PHYs connected to L2 Switch portsCodrin Ciubotariu
This patch adds "interrupts" property for Ethernet PHYs connected over QSGMII to the L2 Switch ports, for boards T1040rdb, T1040d4rdb and T1040qds. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
2015-10-14fmd: fix policer spelling issuesMandy Lavi
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
2015-10-14fmd: Remove FM_PORT_PcdPrsModifyStartOffset routine - not supportedMandy Lavi
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
2015-10-13fsl_qbman: enable sending cscn to dcp for old qman revisionHaiying Wang
Set CSCN_TARG with correct DCP portal in qman_create_cgr_to_dcp() funciton for the qman revision < qman_3.0 JIRA issue# QLINUX-3814 Signed-off-by: Haiying Wang <Haiying.wang@freescale.com>
2015-10-13t4240dts: correct the ceetm nodeHaiying Wang
The patch e9cacc46fcd4ebd1b2238a2655d08ad42e87f7d2 only added CEETM node qman-ceetm0 in t4240si-post.dts, and defined 8 ceetm channels. It is not correct for T4240 which has QMan 3.x version to support 32 CEETM channels. Besides, T4240 supports 2 CEETMs, so 2 ceetm nodes should be included in this device tree. JIRA issue# QLINUX-3737 Signed-off-by: Haiying Wang <Haiying.wang@freescale.com>
2015-09-24dpaa_eth: Add a configurable dpa_tx callCamelia Groza
Signed-off-by: Camelia Groza <camelia.groza@freescale.com>
2015-09-24mmc: sdhci-of-esdhc: fix compile error on ARM platformYangbo Lu
Fix two compile errors below, error: implicit declaration of function 'of_iomap' error: implicit declaration of function 'out_be32' Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
2015-09-24QorIQ/TMU: add TMU node to device tree for QorIQ T1023/T1024Jia Hongtao
The Thermal Monitoring Unit node for T1023/T1024. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
2015-09-24QorIQ/TMU: add thermal management support based on TMUJia Hongtao
It supports one critical trip point and one passive trip point. The cpufreq is used as the cooling device to throttle CPUs when the passive trip is crossed. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
2015-09-24QorIQ/TMU: add TMU node to device tree for QorIQ T1040/T1042Jia Hongtao
This is Thermal Monitoring Unit for QorIQ platform. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
2015-09-24thermal: fix cpu_cooling max_level behaviorEduardo Valentin
As per Documentation/thermal/sysfs-api.txt, max_level is an index, not a counter. Thus, in case a CPU has 3 valid frequencies, max_level is expected to be 2, for instance. The current code makes max_level == number of valid frequencies, which is bogus. This patch fix the cpu_cooling device by ranging max_level properly. Reported-by: Carlos Hernandez <ceh@ti.com> Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
2015-09-24mmc: sdhci-of-esdhc: add SDR50 mode support for SD/MMC Legacy Adapter CardYangbo Lu
The eSDHC is not compatible with SD spec well, so we need to use eSDHC-specific code to switch to SDR50 mode. 1. IO signal voltage switching, eSDHC uses SDHC_VS to switch io voltage and it's needed to configure a global utilities register SCFG_SDHCIOVSELCR(if it has) and SDHC_VS signal. 2. Before executing tuning procedure, eSDHC should set its own tuning block. static const struct sdhci_ops sdhci_esdhc_ops = { ... .set_tuning_block = esdhc_set_tuning_block, .signal_voltage_switch = esdhc_signal_voltage_switch, }; Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
2015-09-24mmc: esdhc: add eMMC45 Adapter Card HS200 mode supportYangbo Lu
The eSDHC is not compatible with SD spec well, it's needed to add callbacks for signal voltage switching and tuning block setting for eSDHC for eMMC45 Adapter Card HS200 mode support. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
2015-09-23QorIQ/TMU: add TMU node to device tree for LS1021AJia Hongtao
The Thermal Monitoring Unit node for LS1021A. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
2015-09-07Merge branch 'feature/LS1-for-SDK' of ↵jason
ssh://sw-stash.freescale.net/dnnpi/ls1-linux-jason into LS1-SDKV04-SDK1.9
2015-08-21t104xd4rdb: add DS26522 nodes to device treeZhao Qiang
DS26522 is used for tdm, configured by SPI bus. Add nodes under spi node to t104xd4rdb.dtsi. Signed-off-by: Zhao Qiang <qiang.zhao@freescale.com>
2015-07-20Merge branch 'qoriq-sdk' into LS1-SDK-Rev2.0jason
2015-07-14arm: ls1021a: mask interrupts before entering deep sleepChenhui Zhao
Before entering deep sleep, interrupts should be masked. Or, unexpected interrupts may block the process of deep sleep. So, mask interrupts by the following steps: 1. Mask interrupts to RCPM 2. Disable the GIC This will make deep sleep more stable. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: I601062f8406324a308ef44491fed7cf479eaeba9 Reviewed-on: http://git.am.freescale.net:8181/39602 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-07-10arm: dts: ls1021a: Add transfer mode property in DSPI2 nodeHaikun Wang
DSPI new driver can select transfer mode(tcfq/eoq) to work. The property will be read from dtsi node. Add the property tcfq-mode for LS1021a. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Change-Id: I09efa9277364b79d075a1de94bd04111e2434576 Reviewed-on: http://git.am.freescale.net:8181/39515 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-07-10arm: dts: ls1021atwr: Enable DSPI2 dts nodeHaikun Wang
Erratum A-008022 has been fixed on LS1021A Rev2.0. So we can use DSPI2 now, this patch enable DSPI2 in dts for LS1021ATWR. Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Change-Id: I00c76415c155a290eecbde8b37e6148b11ed2c07 Reviewed-on: http://git.am.freescale.net:8181/39514 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-07-09arm: ls1021a: change the order of setting PMC interrupt registersChenhui Zhao
In deep sleep process, set interrupt status and polarity registers before enabling PMC interrupts. It is more stable, especially on ls1021a-twr board. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: I8305e25a76f0bcc636b58178495165c915ac3c1a Reviewed-on: http://git.am.freescale.net:8181/39478 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-07-09crypto: caam - fix SEC ERA readingAlex Porosanu
In order to ensure that the SEC ERA property is properly read from DTS, of_property_read* functions need to be used. Signed-off-by: Alex Porosanu <alexandru.porosanu@freescale.com> Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Change-Id: I3fe958ca9b0ab91c2dbd089d1b2f090042cc3fd0 Reviewed-on: http://git.am.freescale.net:8181/39374 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-07-09crypto: caam - fix snooping for write transactionsHoria Geantă
HW coherency won't work properly for CAAM write transactions if AWCACHE is left to default (POR) value - 4'b0001. It has to be programmed to 4'b0010. For platforms that have HW coherency support: -PPC-based: the update has no effect; CAAM coherency already works due to the IOMMU (PAMU) driver setting the correct memory coherency attributes -ARM-based: the update fixes cache coherency issues, since IOMMU (SMMU) driver is not programmed to behave similar to PAMU Change-Id: I1f91a526c0bdf28b799d19cab9599b115cad55b3 Signed-off-by: Horia Geantă <horia.geanta@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/39256 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-07-03arm/dts: Add node for ina220 on LS1021ATWR-RevYuan Yao
Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Change-Id: Iae6ec5f13ae85e26c2bf50efe55e81d91eba3d8d Reviewed-on: http://git.am.freescale.net:8181/39246 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-07-03arm/defconfig: Add Atheros AT803X PHYs supportYuan Yao
Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Change-Id: Iaba32fdf49bddbd7ee9b8f0f77847f7399c08a3f Reviewed-on: http://git.am.freescale.net:8181/39245 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16QE/HDLC: modify QE-HDLC for both ARM and POWERPCZhao Qiang
ls1021 support QE IP block and it is arm, So modify QE-HDLC code to adapt bothe arm and powerpc Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I9e02e53ae1fafffeec3bf7145309002db19c2dc1 Reviewed-on: http://git.am.freescale.net:8181/38130 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16Test patch: Enable CAN SoC level loopbackBhupesh Sharma
This patch enables the SoC level CAN loopback. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: I5efd40f5d853d11b2476b2bbab0db66c7b1711fa Reviewed-on: http://git.am.freescale.net:8181/38097 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16arm/dts: Add nodes for flexcan devices present on LS1021A-Rev2 SoCBhupesh Sharma
This patch adds the device nodes for flexcan controller(s) present on LS1021A-Rev2 SoC. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com> Change-Id: Ia301d4db49d337e37def2e6667b6e4e1586fd8fc Reviewed-on: http://git.am.freescale.net:8181/38096 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16can: flexcan: Add support for non RX-FIFO modeBhupesh Sharma
This patch adds support for non RX-FIFO (legacy) mode in the flexcan driver. On certain SoCs, the RX-FIFO support might be broken, as a result we need to fall-back on the legacy (non RX-FIFO) mode to receive CAN frames. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com> Change-Id: I8b07e851b68fcca9716d02b14b6712c2da654ad5 Reviewed-on: http://git.am.freescale.net:8181/38095 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16can: flexcan: Remodel FlexCAN register r/w APIs for BE instancesBhupesh Sharma
The FlexCAN IP on certain SoCs like (Freescale's LS1021A) is modelled in a big-endian fashion, i.e. the registers and the message buffers are organized in a BE way. More details about the LS1021A SoC can be seen here: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=LS1021A&nodeId=018rH325E4017B# This patch ensures that the register read/write APIs are remodelled to address such cases, while ensuring that existing platforms (where the FlexCAN IP was modelled in LE way) do not break. Tested on LS1021A-QDS board. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com> Change-Id: I4116956dfc92ae565a2aea96356014c77f506c1c Reviewed-on: http://git.am.freescale.net:8181/38094 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16can: flexcan: Add ls1021a flexcan device entryBhupesh Sharma
This patch adds ls1021a flexcan device entry to the flexcan driver code. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: Iad4f7caf7be878784414d194335f203ea02743e5 Reviewed-on: http://git.am.freescale.net:8181/38093 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16doc/bindings: Add 'endianess' optional-property for FlexCAN controllerBhupesh Sharma
This patch adds 'endianess' as the optional-property for describing the FlexCAN controller present on various FSL platforms. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Sakar Arora <Sakar.Arora@freescale.com> Change-Id: I35f5860a3b900ee6344ad807aa04923f0f82dd55 Reviewed-on: http://git.am.freescale.net:8181/38092 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16Revert 'can: flexcan: Add ls1021a flexcan device entry'Bhupesh Sharma
This reverts commit 61af51e63ff5a3666788b1c5c2d42c3df3a03c34. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: I196e1fbc30a97ae0102b13eddd25bdf9230e02f4 Reviewed-on: http://git.am.freescale.net:8181/38091 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16Revert 'net: can: Remodel FlexCAN register read/write APIs for BE instances'Bhupesh Sharma
This reverts commit 4966cbb525a2acfb7c2782f1994949e97b45f242. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: Ifec4963a1ed01fb60f949575e1c2be4da5c38cf6 Reviewed-on: http://git.am.freescale.net:8181/38090 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16Revert 'can: flexcan: Add support for non RX-FIFO mode and conditional ↵Bhupesh Sharma
ERRATA ERR005829 handling' This reverts commit 0ec580b6a604a4fcfd65c3515459def643c8517a. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: I64fb32407f7083aa433d4d7ec34d7171c2bdc02b Reviewed-on: http://git.am.freescale.net:8181/38089 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-16mmc: sdhci: more efficient interrupt enable register handlingYangbo Lu
Rather than wasting cycles read-modify-writing the interrupt enable registers, cache the value locally instead. This patch is from upstreaming linux, commit id b537f94ce19583de1882f539a5cc49aa99260aca Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Change-Id: I3c1bb4d4b3f7d7dccbaa4748816bfe381edc484c Reviewed-on: http://git.am.freescale.net:8181/37869 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-12pci/layerscape: update MSI code for ls1021 rev2 MSI supportMinghuan Lian
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I68ac4e509f41c249d38579b34cb78d35e9231b0f Reviewed-on: http://git.am.freescale.net:8181/37558 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
generated by cgit v0.10.2 at 2024-09-28 01:39:30 (GMT)