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2014-12-11dts: ls1021a: add the RCPM node and change FPGA's compatibleChenhui Zhao
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: Ib0ecd4424f3d356fe1bcd687d3befd61527be5ab Reviewed-on: http://git.am.freescale.net:8181/21974 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm:dts:ls1021aqds: reduce the frequency for dspi flashChao Fu
Dspi flash is at45db021d on ls1021aqds board. Reduce its frequency to improve the data transfer stability. Signed-off-by: Chao Fu <B44548@freescale.com> Change-Id: If4e4d03d52fc28dea2dca3e6c6872024d3d1229a Reviewed-on: http://git.am.freescale.net:8181/21973 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11PCI: Layerscape: Fix PCIe link stateMinghuan Lian
The SCFG has been set bit-reverse as default, so the value of SCFG_PEXMSCPORTSR does not need do bitrev. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I6827bd2831176e3e0e968240f2d87f84a66e1225 Reviewed-on: http://git.am.freescale.net:8181/21970 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11esdhc: mmc: Add LS1021A SD support.Qiu Wujie
Signed-off-by: Qiu Wujie <B49553@freescale.com> --- This patch will be merged into the previous patch as below. URL: https://patchwork.kernel.org/patch/3976141/ Change-Id: I5c860dd5b58400aa25f9cce444ee8e94b4488cc4 Reviewed-on: http://git.am.freescale.net:8181/21965 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11esdhc: defconfig: Add LS1021A SD support.Qiu Wujie
Signed-off-by: Qiu Wujie <B49553@freescale.com> Change-Id: I30e6c4e9c5f6859aecc586b21d6426a802160699 Reviewed-on: http://git.am.freescale.net:8181/21964 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11tty: of-serial: fixup info uninitialized bugJingchang Lu
The kmalloc space may cause info->clk have random value if the dts node doesn't define clk property, thus cause all if(info->clk) condition wrong. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I309ff5cc881e00dc4475649e050263243027326c Reviewed-on: http://git.am.freescale.net:8181/21934 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11i2c: pca954x: put the mux to disconnected state after resumeJisheng Zhang
pca954x may be power lost during suspend, so after resume we also suffer the issue fixed by commit cd823db8b1161ef0d756514d280715a576d65cc3, "pca954x power-on default is channel 0 connected. If multiple pca954x muxes are connected to the same physical I2C bus, the parent bus will see channel 0 devices behind both muxes by default." What's more, when resume bootloader may also operate the mux, so the the channel connected after that may not be the one driver thought. We fix this problem by putting the mux to disconnected state and clearing last_chan in the resume hook. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Reviewed-by: Jean Delvare <jdelvare@suse.de> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> -- Cherry-pickded from linux.git: f5e596cd9f0ec6c03660fe4196d395bc3da919a4 Change-Id: I43da37cf2f854e023f5ff645d20134b919347142 Reviewed-on: http://git.am.freescale.net:8181/21929 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: pm: add deep sleep support for LS1Chenhui Zhao
LS1 supports deep sleep feature that can switch off most parts of the SoC when it is in deep sleep state. The DDR controller will also be powered off in deep sleep. Therefore, copy the last stage code to enter deep sleep to SRAM and run it with disabling MMU and caches. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> --- Patch Sent Upstream url: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296411.html Change-Id: If96ace364c21786cc88ea4979d7cbb4e177da0a2 Reviewed-on: http://git.am.freescale.net:8181/21920 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11fsl: fsm: use same interface to support T104x and LS1021AChenhui Zhao
T104x is based on PowerPC platform, LS1021A is based on ARM platform. Make T104x and LS1021A use same interface to set/clear EPU registers. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> --- Patch Sent Upstream url: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296410.html Change-Id: I00fdfc0b15e0f7cdc9ebc9970798d6669d7c22aa Reviewed-on: http://git.am.freescale.net:8181/21919 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM:LS1021aQDS: add CPU hotplug platform supportZhang Zhuoyu
This is only a CPU pseudo-hotplug, and incompatible with kexec mechanics. As per the discussion with Russell King in opensource community, CPU hotplug should reset the secondary core to be compatible with kexec. "In the kexec case, when the secondary CPU wakeup, the code it is executing can already been overwritten, which then means that the CPU ends up executing some random code instead." For LS102x platforms, resetting core can be realized, but come across cache coherence problem which is still unresolved, we will submit another patch to implement CPU hotplug by resetting core once cache coherence issue resloved. Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com> --- Patch Sent Upstream url: https://lkml.org/lkml/2014/9/26/422 Change-Id: I36509f99299f874ef0df891a33c907a749649527 Reviewed-on: http://git.am.freescale.net:8181/21918 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: 7861/1: cacheflush: consolidate single-CPU ARMv7 cache disabling codeNicolas Pitre
This code is becoming duplicated in many places. So let's consolidate it into a handy macro that is known to be right and available for reuse. Signed-off-by: Nicolas Pitre <nico@linaro.org> Acked-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> --- cherry-pick from 39792c7cf3111d69dc4aa0923859d8b929e9039f Change-Id: I9e2e9715425bcb8493c32b46ecb41c568d8235c5 Reviewed-on: http://git.am.freescale.net:8181/21917 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: 7885/1: Save/Restore 64-bit TTBR registers on LPAE suspend/resumeMahesh Sivasubramanian
LPAE enabled kernels use the 64-bit version of TTBR0 and TTBR1 registers. If we're running an LPAE kernel, fill the upper half of TTBR0 with 0 because we're setting it to the idmap here (the idmap is guaranteed to be < 4Gb) and fully restore TTBR1 instead of just restoring the lower 32 bits. Failure to do so can cause failures on resume from suspend when these registers are only half restored. Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> --- cherry-pick from f3db3f4389dbd9a8c2b4477f37a6ebddfd670ad8 Change-Id: I7e91a04ac2fda61f9c8a5e60d8d503d00a3cf9c1 Reviewed-on: http://git.am.freescale.net:8181/21910 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: 8053/1: kernel: sleep: restore HYP mode configuration in cpu_resumeLorenzo Pieralisi
On CPUs with virtualization extensions the kernel installs HYP mode configuration on both primary and secondary cpus upon cold boot. On platforms where CPUs are shutdown in idle paths (ie CPU core gating), when a CPU resumes from low-power states it currently does not execute code that reinstalls the HYP configuration, which means that the kernel cannot run eg KVM properly on such machines. This patch, mirroring cold-boot behaviour, executes position independent code that reinstalls HYP configuration and drops to SVC mode safely on warmboot, so that deep idle states can be enabled in kernel running as hosts on platforms with power management HW. Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Dave Martin <dave.martin@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Nicolas Pitre <nico@linaro.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> --- cherry-pick from 0e0779da2233f2dfc85e9c3a6ea142476d326811 Change-Id: Iafed877cc49e799d7c31f1cb265a0b38be708c88 Reviewed-on: http://git.am.freescale.net:8181/21909 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11spi:Kconfig:Add DSPI in LS1021 supportChao Fu
DSPI also is a module in LS1021. Add the dependence SOC_LS1021 for DSPI. Signed-off-by: Chao Fu <B44548@freescale.com> Change-Id: Id48cc01c7756f9b3a977f4f5478fa018897952f8 Reviewed-on: http://git.am.freescale.net:8181/21907 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm:dtsi:ls1021a:Add the DSPI transfer mode property in DSPI nodeChao Fu
DSPI new driver can select transfer mode(tcfq/eoq) to work. The property will be read from dtsi node. Add the property tcfq-mode for LS1021a. Signed-off-by: Chao Fu <B44548@freescale.com> Change-Id: Ib659338777a4a8a5fdef7914c556c3ca8b4c483d Reviewed-on: http://git.am.freescale.net:8181/21908 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ASFIPSEC: Porting ASF to LS1.Nikhil Agarwal
Adding PDB endianness independent. Signed-off-by: Nikhil Agarwal <Nikhil.Agarwal@freescale.com> Change-Id: I44bfc921ba1460dd2785c21252898b55953d8385 Reviewed-on: http://git.am.freescale.net:8181/17497 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Sandeep Malik <Sandeep.Malik@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com> (cherry picked from commit 16e2ab4fab053e020d4857f14fe8bd35616ad304) Reviewed-on: http://git.am.freescale.net:8181/21354
2014-12-11audio: dts: Add dts nodes on LS1021AQDS/TWRAlison Wang
This patch adds dts nodes for audio support on LS1021AQDS/TWR. Signed-off-by: Alison Wang <alison.wang@freescale.com> Change-Id: I5e98a2377a7230598401ad932c4016951435b240 Reviewed-on: http://git.am.freescale.net:8181/21061 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11cpufreq: qoriq: Make the driver usable on all QorIQ platformsTang Yuantian
Freescale introduced new ARM core-based SoCs which support dynamic frequency switch feature. DFS on new SoCs are compatible with current PowerPC CoreNet platforms. In order to support those new platforms, this driver needs to be slightly adjusted. The main changes include: 1. Changed the names of driver and functions in driver. 2. Added two new functions get_cpu_physical_id() and get_bus_freq(). 3. Used a new way to get all the CPUs which sharing clock wire. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> --- http://patchwork.ozlabs.org/patch/400406/ Change-Id: I29fc5fefd0860db5ee531844d1218a6b70098dfe Reviewed-on: http://git.am.freescale.net:8181/21874 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11clock: redefine variable clocks_per_pll as a struct memberTang Yuantian
redefine variable clocks_per_pll as a struct member If there are multiple PLL clock nodes, this variable will get overwritten. Redefined it as a struct member can avoid this. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Change-Id: I892993ffaf046f333c564170a5cac7c845ef9ba8 Reviewed-on: http://git.am.freescale.net:8181/21873 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11dts: ls1021a: updated the soc nodeTang Yuantian
Added device_type property to soc node to facilitate its use. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Change-Id: I4c50770215608f8ca718e78072a28f69afdf1bc2 Reviewed-on: http://git.am.freescale.net:8181/21690 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11dts: ls1021a: updated the clockgen nodeTang Yuantian
Fixed some error in clockgen node. This patch also added clock source to CPU nodes to support CPU frequency switch dynamically. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Change-Id: I2d40c3bc9c766d62d9cb8a3c00b9d5e1c2e65f41 Reviewed-on: http://git.am.freescale.net:8181/21689 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11qe-tdm: modify qe-tdm for both arm and powerpcZhao Qiang
ls1021 support qe ip block and it is arm, so modify qe-tdm code to adapt both arm and powerpc Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: Ie64cef1dc6cd915388c089d1359c681da67c6fba Reviewed-on: http://git.am.freescale.net:8181/21869 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ls1021aqds: add qe node to ls1021aqds dtsZhao Qiang
add qe node(qe-tdm and qe-uart) into ls1021a-qds.dts Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I1ab52c2330246e807fd4c96103d2c063b6d8d8ba Reviewed-on: http://git.am.freescale.net:8181/21868 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ls102xa: audio: Workaround for SAI data transfer endian issueAlison Wang
Transmit Data Register(TDR) used as the destination address of EDMA transaction is in big-endian mode. The audio data in memory and EDMA transaction are in little-endian mode. For S16_LE format data, a workaround is to swap the original 16-bit data, and then write into the higher 16 bit of TDR. Signed-off-by: Alison Wang <alison.wang@freescale.com> Change-Id: Ib15832743e9a4c69792f2dad4cb00fbbc1d2daaa Reviewed-on: http://git.am.freescale.net:8181/21063 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: Add support for non RX-FIFO mode and conditional ERRATA ↵Bhupesh Sharma
ERR005829 handling This patch adds support for non RX-FIFO (legacy) mode and conditional ERRATA ERR005829 handling in flexcan driver. Both these features are now selectable via Kconfig entries and hence can be turned-on/off as per a SoC feature set availability. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: I2a5a4970b7e5b18a45fb421f1c0d008ad5a3b0f8 Reviewed-on: http://git.am.freescale.net:8181/21856 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ls1021a/dts: Add device nodes for FlexCAN IP instancesBhupesh Sharma
This patch adds the device nodes for 4 FlexCAN IP instances available on LS1021A SoC in the ls1021a.dtsi file and enables only the first two instances which are supported on the QDS board in ls1021a-qds.dts file. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> --- Previous version of this patch under review upstream: http://patchwork.ozlabs.org/patch/363588/ Will re-spin the patch with the DTS Change-Id: I592e5f8562ad173801a53433aec9a91b00ba8bb0 Reviewed-on: http://git.am.freescale.net:8181/21855 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11net: can: Remodel FlexCAN register read/write APIs for BE instancesBhupesh Sharma
The FlexCAN IP on certain SoCs like (Freescale's LS1021A) is modelled in a big-endian fashion, i.e. the registers and the message buffers are organized in a BE way. More details about the LS1021A SoC can be seen here: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=LS1021A&nodeId=018rH325E4017B# This patch ensures that the register read/write APIs are remodelled to address such cases, while ensuring that existing platforms (where the FlexCAN IP was modelled in LE way) do not break. Tested on LS1021A-QDS board. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: Ibaa6b1816670537466b227b5032be73338435c03 Reviewed-on: http://git.am.freescale.net:8181/21854 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: Add ls1021a flexcan device entryBhupesh Sharma
This patch adds ls1021a flexcan device entry to the flexcan driver code. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> --- Previous version of this patch under review upstream: http://patchwork.ozlabs.org/patch/363588/ Change-Id: Ie01ec4583e1dc4efd90eb05e69ed45ae351d9d4e Reviewed-on: http://git.am.freescale.net:8181/21853 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11[fsl-only] can: flexcan: Remove can_change_mtu calls as this is not ↵Bhupesh Sharma
supported in 3.12 kernel Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Change-Id: I731e457b0b29a794c752116921b119c37514758a Reviewed-on: http://git.am.freescale.net:8181/21852 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: increase FLEXCAN_MCR_MAXMB() macro to 7 bitsMarc Kleine-Budde
This patch increases the mask in the FLEXCAN_MCR_MAXMB() to 7 bits as in the newer flexcan cores the MAXMB field is 7 bits wide. Reported-by: David Jander <david@protonic.nl> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: 4c728d804c4b9d1ae7f76e8f32c419bc21a6e540 Change-Id: If7f3817dced00e4864da29579ff377788e9ee4ad Reviewed-on: http://git.am.freescale.net:8181/21851 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: put TX mailbox into TX_INACTIVE mode after tx-completeMarc Kleine-Budde
After sending a RTR frame the TX mailbox becomes a RX_EMPTY mailbox. To avoid side effects when the RX-FIFO is full, this patch puts the TX mailbox into TX_INACTIVE mode in the transmission complete interrupt handler. This, of course, leaves a race window between the actual completion of the transmission and the handling of tx-complete interrupt. However this is the best we can do without busy polling the tx complete interrupt. Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: de5944883ebbedbf5adc8497659772f5da7b7d72 Change-Id: Icfa9443f03246feee26868b9ad17147b2352c9fd Reviewed-on: http://git.am.freescale.net:8181/21850 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: implement workaround for errata ERR005829David Jander
This patch implements the workaround mentioned in ERR005829: ERR005829: FlexCAN: FlexCAN does not transmit a message that is enabled to be transmitted in a specific moment during the arbitration process. Workaround: The workaround consists of two extra steps after setting up a message for transmission: Step 8: Reserve the first valid mailbox as an inactive mailbox (CODE=0b1000). If RX FIFO is disabled, this mailbox must be message buffer 0. Otherwise, the first valid mailbox can be found using the "RX FIFO filters" table in the FlexCAN chapter of the chip reference manual. Step 9: Write twice INACTIVE code (0b1000) into the first valid mailbox. Signed-off-by: David Jander <david@protonic.nl> Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: 25e924450fcb23c11c07c95ea8964dd9f174652e Change-Id: I504198f3b5aaba2c0277b596e925ce3bb17a2258 Reviewed-on: http://git.am.freescale.net:8181/21849 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: correctly initialize mailboxesBhupesh Sharma
Apparently mailboxes may contain random data at startup, causing some of them being prepared for message reception. This causes overruns being missed or even confusing the IRQ check for trasmitted messages, increasing the transmit counter instead of the error counter. This patch initializes all mailboxes after the FIFO as RX_INACTIVE. Signed-off-by: David Jander <david@protonic.nl> Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: fc05b884a31dbf259cc73cc856e634ec3acbebb6 Change-Id: I0757258cb27cb2dec26e8afa219b512bba80be4b Reviewed-on: http://git.am.freescale.net:8181/21848 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: mark TX mailbox as TX_INACTIVEMarc Kleine-Budde
This patch fixes the initialization of the TX mailbox. It is now correctly initialized as TX_INACTIVE not RX_EMPTY. Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: c32fe4ad3e4861b2bfa1f44114c564935a123dda Change-Id: I3058828c8f0786726589a8fc05a5cc8467644e1b Reviewed-on: http://git.am.freescale.net:8181/21847 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: avoid calling usleep_range from interrupt contextDavid Jander
Apparently can_restart() runs from a (timer-) interrupt and can call flexcan_chip_[en|dis]able(), so avoid using usleep_range() Signed-off-by: David Jander <david@protonic.nl> Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: 8badd65e48c90d66587359d5329c2813088c0f50 Change-Id: I44fef82e8b413d6751a23fcb05d4a9f39ecb385a Reviewed-on: http://git.am.freescale.net:8181/21846 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: handle state passive -> warning transitionSebastian Andrzej Siewior
Once the CAN-bus is open and a packet is sent, the controller switches into the PASSIVE state. Once the BUS is closed again it goes the back err-warning. The TX error counter goes 0 -> 0x80 -> 0x7f. This patch makes sure that the user learns about this state chang (CAN_STATE_ERROR_WARNING => CAN_STATE_ERROR_PASSIVE) Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Matthias Klein <matthias.klein@optimeas.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: 8ce261d0bb491da957278cdcba207791f329d1da Change-Id: I311a7075033b493ef06818fb1e15f0eb69e96fa2 Reviewed-on: http://git.am.freescale.net:8181/21845 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: Disable error interrupt when bus error reporting is disabledAlexander Stein
In case we don't have FLEXCAN_HAS_BROKEN_ERR_STATE and the user set CAN_CTRLMODE_BERR_REPORTING once it can not be unset again until reboot. So in case neither hardware nor user wants the error interrupt disable the bit. Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: bc03a54139baafcd8fe89ad115411c2c9c8a4905 Change-Id: Ieb52a8f0cc761a37faf4556284bf2c922c6bec79 Reviewed-on: http://git.am.freescale.net:8181/21844 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: add vf610 support for FlexCANStefan Agner
Extend FlexCAN driver to support Vybrid. Vybrids variant of the IP has ECC support which is controlled through the memory error control register (MECR). There is also an errata which leads to false positive error detections (ID e5295). This patch disables the memory error detection completely. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: cdce844865bea6869b34bacc98af3711774f5bb5 Change-Id: I296ab822a5e2ed6e28b98e348d690eab8ec165ac Reviewed-on: http://git.am.freescale.net:8181/21843 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: flexcan_get_berr_counter(): switch on clocks before accessing ↵Stefan Agner
ecr register The funcion flexcan_get_berr_counter() may be called from userspace even if the interface is down, this the clocks are disabled. This patch switches on the clocks before accessing the ecr register. Reported-by: Ashutosh Singh <ashuleapyear@gmail.com> Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: ec56acfef2af184ca485ffeba16adbd56c110c94 Change-Id: I53ead04b0d5ae7c995809c51aef57acaedd3c3f4 Reviewed-on: http://git.am.freescale.net:8181/21842 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: Unify MTU settings for CAN interfacesOliver Hartkopp
CAN interfaces only support MTU values of 16 (CAN 2.0) and 72 (CAN FD). Setting the MTU to other values is pointless but it does not really hurt. With the introduction of the CAN FD support in drivers/net/can a new function to switch the MTU for CAN FD has been introduced. This patch makes use of this can_change_mtu() function to check for correct MTU settings also in legacy CAN (2.0) devices. Signed-off-by: Oliver Hartkopp <socketcan@hartkopp.net> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: c971fa2ae42e73e9ccc2f5e93f268c8742da4c5d Change-Id: I933a13a6c1f0b65fa748ffca352fa061940d8893 Reviewed-on: http://git.am.freescale.net:8181/21841 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: make use of platform_get_device_id()Marc Kleine-Budde
This patch replaces an open coded pdev->id_entry by platform_get_device_id(). Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: d0873e6fc06686cf2dfb9adabb6ca65e9967c60f Change-Id: I4a70c813dd5ce60b0c81cc57aa41a78413a891a0 Reviewed-on: http://git.am.freescale.net:8181/21840 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: Remove #ifdef CONFIG_PM_SLEEPMarc Kleine-Budde
This patch removes #ifdef CONFIG_PM_SLEEP to improve compile coverage. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: 08c6d35154069becb01243176fb72b3bc60ff3cb Change-Id: I062083cf2a38d7b3dfa2c9a3329c843ed6c91cf8 Reviewed-on: http://git.am.freescale.net:8181/21839 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: factor out soft reset into seperate funtionMarc Kleine-Budde
This patch moves the soft reset into a seperate function. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from Linux-next: 4b5b82274a17f0ebbf02378df2ba7f36a3f5af19 Change-Id: I52b4dabb58e6b9af6b5a1825bb20d40d0a8a91a7 Reviewed-on: http://git.am.freescale.net:8181/21838 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11can: flexcan: fix transition from and to freeze mode in chip_{,un}freezeMarc Kleine-Budde
This patch factors out freeze and unfreeze of the CAN core into seperate functions. Experiments have shown that the transition from and to freeze mode may take several microseconds, especially the time entering the freeze mode depends on the current bitrate. This patch adds a while loop which polls the Freeze Mode ACK bit (FRZ_ACK) that indicates a successfull mode change. If the function runs into a timeout a error value is returned. Cc: linux-stable <stable@vger.kernel.org> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> --- Cherry-picked from linux-next: b1aa1c7a2165b44ecce66286a3095cc6c7667d1c Change-Id: I0db4998dab8782d717a99eebb6d3a56ed787bbde Reviewed-on: http://git.am.freescale.net:8181/21837 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11drivers/usb : Remove compilation error for usb EHCI gadgetNikhil Badola
Remove compilation errors from USB EHCI gadget driver Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Change-Id: Ie0ad80495ab16fe8537e544113dde806c790ff05 Reviewed-on: http://git.am.freescale.net:8181/21819 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11drivers/usb : Port USB EHCI Gadget driver for LS102XANikhil Badola
Change raw read/write accessors to ioread/writebe32 for big endian registers Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Change-Id: I75e181fc235f40aba7aa0d9db8f18c0783b04f82 Reviewed-on: http://git.am.freescale.net:8181/21818 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11drivers: usb: fsl: Set USB_EN bit to select ULPI phyNikhil Badola
Set USB_EN bit to select ULPI phy for USB controller version 2.5 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Change-Id: I22fd6921d264d64f59d795d81f82ea89214862d9 Reviewed-on: http://git.am.freescale.net:8181/21817 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11drivers/usb : Set DMA_MASK of usb platform deviceNikhil Badola
Set DMA_MASK of usb platform device Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Change-Id: I7d6387f3b95b6ec7c1999e14801dc4cfec7b016d Reviewed-on: http://git.am.freescale.net:8181/21816 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11drivers/usb : Port USB EHCI host driver for LS102xANikhil Badola
Change Power architecture specific APIs such as in_be32/out_be32 for registers read/write. Instead using ioread/writebe32 which are defined for power as well as arm architecture Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Change-Id: Ic5ecf4cb048dc4a6bae81bc0789b9bdb7d5c6ded Reviewed-on: http://git.am.freescale.net:8181/21815 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11drivers: usb: fsl: Remove compilation error from usb driverNikhil Badola
Remove compilation error from USB driver while compiling for architectures other than PPC Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Change-Id: Icc9d648f08ec5affb7b58374faef2c6e3b539182 Reviewed-on: http://git.am.freescale.net:8181/21814 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
generated by cgit v0.10.2 at 2024-10-01 07:11:56 (GMT)