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2014-03-24powerpc/t4240: Change t4240 USB controller versionNikhil Badola
Change USB controller version to 2.5 in compatible string for T4240 rev2.0 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Change-Id: I92aa23cee236c13547b59bf62ef68f1d6002f2ff Reviewed-on: http://git.am.freescale.net:8181/9638 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Suresh Gupta <suresh.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24powerpc/t2080: Change t2080 USB controller version Nikhil Badola
Change USB controller version to 2.5 in compatible string for T2080 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Change-Id: I4a539e3e0984e418c09a3d64405f9b844f404289 Reviewed-on: http://git.am.freescale.net:8181/7459 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> (cherry picked from commit cd37bcac41666cccb7fdf84e475967630848d257) Change-Id: I4a539e3e0984e418c09a3d64405f9b844f404289 Reviewed-on: http://git.am.freescale.net:8181/9835 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24added support for PKC keygenYashpal Dutta
As a part of PKC support, RSA, DSA DH, ECDH, ECDSA requires key generation. The patch adds support for key generation support for DSA, ECDSA, DH, ECDH. The patch adds DH operation support too Signed-off-by: Yashpal Dutta <yashpal.dutta@freescale.com> Change-Id: I0dc9c144a23e2248bf8974a1615363341dc4886e Reviewed-on: http://git.am.freescale.net:8181/5867 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Geanta Neag Horia Ioan-B05471 <horia.geanta@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9551 Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24caam driver updates for public key cryptographyYashpal Dutta
CAAM driver updates as per public key infrastructure changes in cryptoAPI RSA, DSA, ECDSA are support as part of Public Key Crypto Operations Signed-off-by: Yashpal Dutta <yashpal.dutta@freescale.com> Change-Id: I3a6e4f71866a5ef157b9ea13e618c4d3d209f558 Reviewed-on: http://git.am.freescale.net:8181/5839 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Geanta Neag Horia Ioan-B05471 <horia.geanta@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9546 Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-24Power Management support for CAAMYashpal Dutta
Platform can go in sleep where CAAM will remain power ON while in some cases CAAM will be powered off during deep-sleep. The patch handles graceful recovery of CAAM state in both the power-up and powered-down cases across deep-sleep. Signed-off-by: Yashpal Dutta <yashpal.dutta@freescale.com> Change-Id: Ie27fdfa78fc50c9a05f6316938ad42a70a89a48e Reviewed-on: http://git.am.freescale.net:8181/9771 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/10085
2014-03-24power management support in caam job ring driverYashpal Dutta
Job ring is suspended gracefully and resume afresh. Pending Jobs not yet processed by CAAM are marked with error for producer to either discard Job or retry after resume. UIO based Job Rings are not handled by this patch. Signed-off-by: Yashpal Dutta <yashpal.dutta@freescale.com> Change-Id: I654734c460e0307243884a076350602ccb97a15a Reviewed-on: http://git.am.freescale.net:8181/9772 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9988
2014-03-24gianfar: Fix P1010 config regression (SQ polling)Claudiu Manoil
The P1010 device tree restricts the number of supported interrupt groups to 1, although the eth controller can support 2 interrupt groups and the driver assumes the Multi-Group mode ("fsl,etsec2" model). So, in this case the assumption that the Multi-Group mode (MQ_MG_MODE) devices always support 2 interrupt groups is false. To fix this, a check for the actual number of interrupt groups enabled in the board's device tree has been added in gfar_probe for the "fsl,etsec2" devices. Without this fix, P1010 based boards claim support for 2 Tx queues to the net stack but only one is actually allocated, leading to NULL access in xmit. This issue was introduced by enabling Single-Queue polling for the P1010 devices. Change-Id: I74e2d143557a7e2cebce8928ac42160e79957f0c Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9876 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com> Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
2014-03-21dpa_offload: Add dts files for offloading apps on T2080Aurelian Zanoschi
Added dts files for running the dpa offloading applications on T2080QDS board. Change-Id: Ifa23fc1adbf479e2cc5542db3600ef243b96608e Signed-off-by: Aurelian Zanoschi <Aurelian.Zanoschi@freescale.com> Signed-off-by: Marian Chereji <marian.chereji@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/8821 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21phy: add freescale XFI 10GBASE-KR driverShaohui Xie
To support freescale XFI 10GBASE-KR, the driver comply with IEEE802.3-2008 to do auto-negotiation and link training with link partner(LP) which has capability of 10GBASE-KR. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Change-Id: I1847226078017b4ca74a39f0d611a96f66921d23 Reviewed-on: http://git.am.freescale.net:8181/9918 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Heinz Wrobel <Heinz.Wrobel@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21crypto: caam - Check for CAAM block presence before registering with crypto ↵Ruchika Gupta
layer The layer which registers with the crypto API should check for the presence of the CAAM device it is going to use. If the platform's device tree doesn't have the required CAAM node, the layer should return an error and not register the algorithms with crypto API layer. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Change-Id: Idf361e8ae971929c55abdefaa29f9d7bc8441a72 Reviewed-on: http://git.am.freescale.net:8181/10043 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Horia Ioan Geanta Neag <horia.geanta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21mtd: m25p80: Modify the name of mtd_infoHou Zhiqiang
To specify spi flash layouts by "mtdparts=..." in cmdline, we must give mtd_info a fixed name,because the cmdlinepart's parser will match the name of mtd_info given in cmdline. Now, if use DT, the mtd_info's name will be spi->dev->name. It consists of spi_master->bus_num, and the spi_master->bus_num maybe dynamically fetched. So, in this case, replace the component bus_num with thei physical address of spi master. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Change-Id: I36a6105a43ea408507576a98642cf80c2b2837e4 Reviewed-on: http://git.am.freescale.net:8181/10040 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21cpufreq: powerpc: add cpufreq transition latency for FSL e500mc SocsZhang Zhuoyu
According to the data provided by HW Team, at least 12 internal platform clock cycles are required to stabilize a DFS clock switch on FSL e500mc Socs. This patch replaces the CPUFREQ_ETERNAL with appropriate HW clock transition latency to make DFS governors work normally on Freescale e500mc boards. Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com> Change-Id: Ia86f8c0f49571d697642fe7c4b98e0e9bfe92c03 Reviewed-on: http://git.am.freescale.net:8181/10024 Reviewed-by: Yang Li <LeoLi@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21USB: Gadget: fsl driver pullup fixSuresh Gupta
This fix the fsl usb gadget driver in a way that the usb device will be only "pulled up" on requests only when vbus is powered Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Change-Id: I1ca5d3e7121a12a4e11ab163504180233367eaf6 Reviewed-on: http://git.am.freescale.net:8181/9367 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21USB: Gadget: fsl: Set dma_ops for FSL USB Gadget DeviceSuresh Gupta
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Change-Id: Ia9191415666afc968e6b29259730eafc8d0e0bdb Reviewed-on: http://git.am.freescale.net:8181/9366 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21crypto: caam - Enabled QI Support for SECNitesh Lal
At the time of merging few changes required for enabling QI support were missed. This patch adds those missing changes and hence enables QI support for SEC. Signed-off-by: Nitesh Lal <NiteshNarayanLal@freescale.com> Change-Id: I190ed1452317cb1f70faaf85f8a69be0a0c5a376 Reviewed-on: http://git.am.freescale.net:8181/9922 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21Ensure that the EQCR Cache Enabled Consumed Index is resetRoy Pledge
The QMan block keeps an internal copy of the CI index when stashing is enabled. In order to synchronize this internal copy with the external view the stash threshold must be set to 1 then 0 otherwise the state of the portal can be bad when it is reallocated by a different process Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com> Change-Id: I1b4c0c7f385abb94ae3ff5e988179f0d328e3455 Reviewed-on: http://git.am.freescale.net:8181/9942 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Haiying Wang <Haiying.Wang@freescale.com> Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21powerpc/p1010rdb:update dts for pcie interrupt-mapZhao Qiang
p1010rdb-pb use the irq[4:5] for inta and intb to pcie, it is active-high, so set it. Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I29db41b4a8b5a67c18151099884edda6de4d9d1a Reviewed-on: http://git.am.freescale.net:8181/9915 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21powerpc/p1010rdb:update mtd of nand to adapt to both old andZhao Qiang
new p1010rdb P1010rdb-pa and p1010rdb-pb have different mtd of nand. So update dts to adapt to both p1010rdb-pa and p1010rdb-pb. Move the nand-mtd from p1010rdb.dtsi to p1010rdb-pa.dtsi. Modify p1010rdb-pb's nand-mtd, which can be overwrote from u-boot by set mtdparts. Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I9e5652b9aa3136299bd6f8bbee529a153031240b Reviewed-on: http://git.am.freescale.net:8181/9914 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-21powerpc/mpc85xx: fix a build issue when user use mpc85xx_defconfigWang Dongsheng
if we enable cpufreq feature we will get a build error. drivers/cpufreq/mpc85xx-cpufreq.c: In function 'p1022_set_pll': drivers/cpufreq/mpc85xx-cpufreq.c:145:2: error: implicit declaration of function 'get_hard_smp_processor_id' [-Werror=implicit-function-declaration] It's miss a include <asm/smp.h> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: I805969b909e269fcfeb1abce30b987baf9c60399 Reviewed-on: http://git.am.freescale.net:8181/9453 Reviewed-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> Tested-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-19powerpc/mpc85xx: Add deep sleep support for IFCPrabhakar Kushwaha
Add support of suspend, resume function to support deep sleep. Also make sure of SRAM initialization during resume. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Change-Id: Ia3d484ff272d6c7feebb74a5ad95f74fb91cdd68 Reviewed-on: http://git.am.freescale.net:8181/9444 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> (cherry picked from commit 82a066c3f93441a7e80c1a603ff185ee4d16bf25) Reviewed-on: http://git.am.freescale.net:8181/9928
2014-03-18iommu/fsl: Support for setting up PMAN PAACE entry.Varun Sethi
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I3aeb4ab1c4f91d5a1367fbe8f6ca31fe80357754 Reviewed-on: http://git.am.freescale.net:8181/9620 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18iommu/fsl: Enable OMT cache, before invalidating PAACT and SPAACT cache.Varun Sethi
Enable OMT cache, before invalidating PAACT and SPAACT cache. This is a PAMU hardware errata work around. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: Iecf8dfcbf0ccc535dff4825a046b2badc660ec8b Reviewed-on: http://git.am.freescale.net:8181/9619 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18fsl/qman: Modifications for new stash attribute setup API.Varun Sethi
An additional parameter (window number) is required for API. Add the window number parameter while invoking the API. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I7ff2552bf15bee25a7e41fd5e0a1781a323aceed Reviewed-on: http://git.am.freescale.net:8181/9618 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18iommu/fsl: PAMU driver changes for DSP stasing support.Varun Sethi
Modifications to PAMU driver for supporting DSP stashing. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I1462806c85f0f398a332ac321bb7b67a8cabc1bb Reviewed-on: http://git.am.freescale.net:8181/9617 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18iommu/fsl: Setup operation mapping for FMAN.Varun Sethi
Setup operation mapping for FMAN. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I1803c366979a28fe3f547526ee0e2f23a5dd03b7 Reviewed-on: http://git.am.freescale.net:8181/9616 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18iommu/fsl : Factor out default PAACE setup code andVarun Sethi
enable all LIODNs. Factor out default PAACE entry setup code and enable all LIODNs for handling the autonomous case. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I31b81576e590569be614511b27d09f01cc4fcf86 Reviewed-on: http://git.am.freescale.net:8181/9615 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18e6500/defconfig: Enabled FSL_UIO_DMAVakul Garg
To enable direct access of DMA channels from user space, CONFIG_UIO_FSL_DMA needs to be turned on. User space DMA driver is used by applications using ipc and usdpaa sdk submodules. Signed-off-by: Vakul Garg <vakul@freescale.com> Change-Id: Id874ead3d373281614f7638a52b1dc074a648ebe Reviewed-on: http://git.am.freescale.net:8181/9817 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Naveen Burmi <NaveenBurmi@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-18powerpc/p1010rdb:update dts to adapt to both old and new p1010rdbZhao Qiang
P1010rdb-pa and p1010rdb-pb have different phy interrupts. So update dts to adapt to both p1010rdb-pa and p1010rdb-pb. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I2e80e63576396a8fe726a6306246b16c25744cff Reviewed-on: http://git.am.freescale.net:8181/5607 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Zang Tiefei-R61911 <tie-fei.zang@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/9593 Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17crypto: caam - use NAPI instead of taskletNitesh Lal
This patch updates the current tasklet implementation to NAPI so as the system is more balanced in the terms that the packet submission and the packet forwarding after being processed can be done at the same priority Signed-off-by: Naveen Burmi <naveenburmi@freescale.com> rebased and tuned NAPI_WEIGHT. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> (cherry picked from commit c74e14d7ff270f8d85c7988e9286f64b721f34ee) Change-Id: I3a31db49a1a6060b3ad5cd0fc4ee4044858438bc Reviewed-on: http://git.am.freescale.net:8181/520 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Signed-off-by: Nitesh Lal <NiteshNarayanLal@freescale.com> Change-Id: I685d687d89a53387287912cd2273f8c1d6a6e4e4 Reviewed-on: http://git.am.freescale.net:8181/9753 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Vakul Garg <vakul@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: update fsl_pci_ep.c according to kernel changesMinghuan Lian
1. Now in kernel the dev_attrs field is removed from struct class, and is converted to use dev_groups. So the patch uses pci_ep_groups instead of pci_ep_attrs. 2. The field pci_mem_offset of struct pci_controller has been changed to mem_offset[], so the patch update the related code. 3. Remove is_pcie initialization for this field has been removed from struct pci_dev. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I9a664b79a1528b52728dae60a929afe4b62aa8c2 Reviewed-on: http://git.am.freescale.net:8181/9607 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: fix ATMU window attribute settingMinghuan Lian
If window size is 0, the bits of size will be 0xffffffff, so window attribute will be set a wrong value. The patch fixes this issue. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: Ieac8428eb1b41a245c89637186d4eb27eedcff55 Reviewed-on: http://git.am.freescale.net:8181/9606 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: add MSIX supportMinghuan Lian
1. The patch initializes MSIX trap outbound window, the application can map this window and trigger the MSIX interrupt. 2. The patch initializes MSIX inbound window which is used to store MSIX vector and PBA data. 3. Add sysfs node to display MSIX vector setting for example: # cat /sys/class/pci_ep/pci0-pf0/msix MSIX venctor 0: control:0x0 data:0x0000406c addr:0x00000000fee00000 MSIX venctor 1: control:0x0 data:0x0000407c addr:0x00000000fee00000 MSIX venctor 2: control:0x0 data:0x0000408c addr:0x00000000fee00000 MSIX venctor 3: control:0x0 data:0x0000409c addr:0x00000000fee00000 MSIX venctor 4: control:0x0 data:0x000040ac addr:0x00000000fee00000 MSIX venctor 5: control:0x0 data:0x00000000 addr:0x0000000000000000 MSIX venctor 6: control:0x0 data:0x00000000 addr:0x0000000000000000 MSIX venctor 7: control:0x0 data:0x00000000 addr:0x0000000000000000 Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I18a6f9056b3c630bba91f5f1dfef2eee01995926 Reviewed-on: http://git.am.freescale.net:8181/9605 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: add VF ATMU access supportMinghuan Lian
All VFs of a PF share the common inbound/outbound windows except translation registers of outbound windows. A VF can only change translation registers of outbound windows. A PF can change all ATMU of VF. The patch provides VF ATMU register definition and provides interfaces to access inbound/outbound windows. It also adds PCI_EP_REGION_MEM type to return PF's memory resource. The application can get and reassign the memory resource to VF. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: Iec877a8054ac47b64d9d94abb9bc32dc0450211e Reviewed-on: http://git.am.freescale.net:8181/9604 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: initialize PF and VF ATMUMinghuan Lian
The first PCI controller of T4 has two physical functions(PF). Each physical functions supports 64 virtual functions(VF). There may be multiple functions to share PCI memory resource. The patch first disables all the inbound/outbound windows then, divides the PCI memory resource equally among all functions and enable a PF/VF outbound window to cover assigned memory. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I84f2211438f1dae32a32d22c4ac60f3f53993159 Reviewed-on: http://git.am.freescale.net:8181/9603 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: fix PCI configuration accessMinghuan Lian
PCI controller which supports SR_IOV and works in End Point mode provides a different method to access configuration. It dose not use bus number device number and function number, instead, it uses physical function number and virtual function number. Different PF may use different offset and stride. It is hard to calculate PF VF number by bus and device number. The original calculation is not suitable for all situations. The patch traverse all functions to find the correct PF VF number. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: Id4a475114c24775d1098483e727a6f824ecada05 Reviewed-on: http://git.am.freescale.net:8181/9602 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fsl_pci_ep: fix checking PCI register sizeMinghuan Lian
For T4240, the first PCI controller whose register size is 0x10000, has two physical functions and each physical function register size is 0x2000. But for some older platform PCI controller size is 0x1000 less than 0x2000. The original checking of PCI register size is mistaken. The patch is to fix this issue. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I089adfb5f31f09f57ea1c2ee29572ac3c68992f4 Reviewed-on: http://git.am.freescale.net:8181/9601 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17fman/dts: fix compatible of mdio node for fman v3Shaohui Xie
Mdio node's compatible for each MAC should be "fsl,fman-memac-mdio" instead of "fsl,fman-memac-tbi" in fman v3. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Change-Id: I848527f67b4e5d033fcfbb739d78341de576f6d0 Reviewed-on: http://git.am.freescale.net:8181/9661 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17powerpc/t4240/dts: add XFI PHY device nodes for 10GBASE-KRShaohui Xie
10GBASE-KR use XFI PCS(Physical Coding Sublayer) module. Each PCS is driven by the corresponding MAC's MDIO. 10GBASE-KR will use PCS module to do auto-negotiation and link training. So, add XFI PHY device nodes for each 10G MAC. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Change-Id: I69609ff42eba95dbed978850bf07fe0c360c9ce2 Reviewed-on: http://git.am.freescale.net:8181/9664 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17powerpc/pci: Fix IMMRBAR addressMinghuan Lian
For PEXCSRBAR, bits 3-0 indicate prefetchable and address type. So when getting base address, these bits should be masked, otherwise we may get incorrect base address. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I03ca7c1201cf0de1042173488e9e8dd4c48faf6e Reviewed-on: http://git.am.freescale.net:8181/9818 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Tiefei Zang <tie-fei.zang@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17xfrm_asf: Patch to revert the changes of multi-policy.Sandeep Malik
This patch reverts the changes for multi-policy being merged into master branch as the compilation of ASF will break. Signed-off-by: Sandeep Malik <Sandeep.Malik@freescale.com> Change-Id: Ifb748be84574daef6ba9adcf0a5db58df5b790b9 Reviewed-on: http://git.am.freescale.net:8181/9807 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-17mpc85xx: Expand the size of u-boot Bootloader ImageYing Zhang
Because the size of u-boot Bootloader gets bigger, this patch adjust the size for NAND bootloader to 768KB and adjust the size for SPI bootloader to 1MB. Signed-off-by: Ying Zhang <b40530@freescale.com> Change-Id: Ida21977b15cc25c9e2667138222537b3af7138c7 Reviewed-on: http://git.am.freescale.net:8181/9454 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-13asf_ipsec_linux: Patch to add support for multiple SPD entries mapping to ↵Sandeep Malik
single SA entry. This patch adds the support for multiple SPD entries to map to single SA entry. CQ: ENGR00267797 Signed-off-by: Sandeep Malik <Sandeep.Malik@freescale.com> Change-Id: I2db3620f9b8262d047c1ffc847d4337e73be02f7 Reviewed-on: http://git.am.freescale.net:8181/8828 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Nipun Gupta <Nipun.Gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-13powerpc/t2080rdb: Add T2080RDB board supportShengzhou Liu
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. The board feature overview: Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz DDR Memory: - Single memory controller capable of supporting DDR3 and DDR3-LP devices - 72bit 4GB DDR3-LP SODIMM in slot Ethernet interfaces: - Two 10M/100M/1Gbps RGMII ports on-board - Two 10Gbps SFP+ ports on-board - Two 10Gbps Base-T ports on-board Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes 16 lanes configuration: - SerDes-1 Lane A-B: to two 10G SFP+ (MAC9 & MAC10) - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) - SerDes-1 Lane E-H: to PCIe goldfinger (PCIe1 x4, Gen3) - SerDes-2 Lane A-D: to PCIe connector (PCIe4 x4, Gen3) - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) - SerDes-2 Lane G-H: to SATA1 & SATA2 IFC/Local Bus - NOR: 128MB 16-bit NOR flash - NAND: 1GB 8-bit NAND flash - CPLD: for system controlling with programable header on-board eSPI: - 64MB N25Q512 SPI flash USB: - Two USB2.0 ports with internal PHY (both Type-A) PCIe: - One PCIe x4 gold-finger - One PCIe x4 connector - One PCIe x2 end-point device (C293 crypto co-processor) SATA: - Two SATA 2.0 ports on-board SDHC: - support a TF-card on-board I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports This board can work in two mode: standalone mode and PCIe endpoint mode. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Change-Id: Id30adfba9b78b0707aecae33dbc03a44e4c38b59 Reviewed-on: http://git.am.freescale.net:8181/9459 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-13gianfar: Add skb recyclingClaudiu Manoil
Add global per-CPU skb recycle lists to improve packet forwarding throughput. Having per-interface recycle lists doesn't allow skb recycling when you're e.g. unidirectionally routing from eth0 to eth1, as eth1 will be producing a lot of recycled skbuffs but eth0 won't have any skbuffs to allocate from its recycle list. Reclaiming resp. recycling of skbs is done on the Rx resp. Tx confirmation paths, in softirq context, and the access to the driver's per-CPU skb lists is lockless and preemption safe. The skb recycling support was removed from the mainline kernel (starting with v3.0). Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Change-Id: I40d47d1d4da337f4e9b0b18136848aa807fc24f7 Reviewed-on: http://git.am.freescale.net:8181/9707 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-13Adding a field in net_device struct to storeSandeep Malik
the cii used by ASF for device mapping. Added an extra field cii(Common interface id) in linux struct net_device. This field will be filled with the free cii when ASF try to create the device mapping in asfctrl_create_dev_map(). CQ:ENGR296530 Signed-off-by: Sahil Malhotra <sahilmalhotra@freescale.com> Signed-off-by: Sandeep Malik <Sandeep.Malik@freescale.com> Change-Id: Ifaee2341886e206a5c5d9bf8e847fb5840a267d3 Reviewed-on: http://git.am.freescale.net:8181/8826 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-13spi/fsl-espi: fix the return value judgment of irq_of_parse_and_mapHou Zhiqiang
Signed-off-by: Hou Zhiqiang <b48286@freescale.com> Change-Id: Ieb821f465dd8dd6b63264208c9eaf7d41ffb5cc8 Reviewed-on: http://git.am.freescale.net:8181/9580 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-13spi/fsl-espi: Add Power Management support for eSPI controllerHou Zhiqiang
Add PM support for eSPI controller using callback function suspend and resume in .driver.pm of platform_driver. Signed-off-by: Hou Zhiqiang <b48286@freescale.com> Change-Id: Ibc1dbdbe830f136ffc26a3610f6a4a1581e0e8cb Reviewed-on: http://git.am.freescale.net:8181/9579 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
2014-03-13t2080qds : Add USDPAA device trees for T2080QDSKuldip Giroh
- 42G configuration (4x10G + 2x1G) is selected for USDPAA. - Add USDPAA device tree for shared MAC and macless interfaces also. 10GEC4 is made shared MAC in the tree. Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com> Change-Id: Iff57cc9a722f0cde187f841ab7e5001d9ef2dd28 Reviewed-on: http://git.am.freescale.net:8181/6911 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Vakul Garg <vakul@freescale.com> Reviewed-by: Jose Rivera <German.Rivera@freescale.com> (cherry picked from commit 662f83e43b86d291026251eb080a599c142f0040) Reviewed-on: http://git.am.freescale.net:8181/9652 Reviewed-by: Sandeep Singh <sandeep@freescale.com>
2014-03-12gianfar: Fix multi-queue support checks @probe()Claudiu Manoil
priv is not instantiated at gfar_of_init() time, when parsing the DT for info on supported HW queues. Before the netdev can be allocated, the number of supported queues must be known. Because the number of supported queues depends on device type, move the compatibility checks before netdev allocation. Local vars are used to hold the operation mode info before netdev allocation. This fixes the null accesses for priv->.., in gfar_of_init. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net> Change-Id: I7b3c4c65196bb443d7e1eccf01ef0a2b5cf6f193 Reviewed-on: http://git.am.freescale.net:8181/9706 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
2014-03-12gianfar: Use Single-Queue polling for "fsl,etsec2"Claudiu Manoil
For the "fsl,etsec2" compatible models the driver currently supports 8 Tx and Rx DMA rings (aka HW queues). However, there are only 2 pairs of Rx/Tx interrupt lines, as these controllers are integrated in low power SoCs with 2 CPUs at most. As a result, there are at most 2 NAPI instances that have to service multiple Tx and Rx queues for these devices. This complicates the NAPI polling routine having to iterate over the mutiple Rx/Tx queues hooked to the same interrupt lines. And there's also an overhead at HW level, as the controller needs to service all the 8 Tx rings in a round robin manner. The combined overhead shows up for multi parallel Tx flows transmitted by the kernel stack, when the driver usually starts returning NETDEV_TX_BUSY leading to NETDEV WATCHDOG Tx timeout triggering if the Tx path is congested for too long. As an alternative, this patch makes the driver support only one Tx/Rx DMA ring per NAPI instance (per interrupt group or pair of Tx/Rx interrupt lines) by default. The simplified single queue polling routine (gfar_poll_sq) will be the default napi poll routine for the etsec2 devices too. Some adjustments needed to be made to link the Tx/Rx HW queues with each NAPI instance (2 in this case). The gfar_poll_sq() is already successfully used by older SQ_SG_MODE (single interrupt group) controllers. This patch fixes Tx timeout triggering under heavy Tx traffic load (i.e. iperf -c -P 8) for the "fsl,etsec2" (currently the only MQ_MG_MODE devices). There's also a significant memory footprint reduction by supporting 2 Rx/Tx DMA rings (at most), instead of 8, for these devices. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net> Change-Id: Id9a2f2737ea0d1d0413e68c6401d86d43a7dc237 Reviewed-on: http://git.am.freescale.net:8181/9705 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
generated by cgit v0.10.2 at 2024-08-30 05:19:18 (GMT)