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The tls1.0 decrypt crypto engine descriptor did not handle correctly
the case when the ciphertext contained only the authentication tag and
padding (i.e. pre ICV length is zero).
While here, add a test vector in test manager for this case.
Change-Id: Ic3b12f1f9581b992b49d73f335d2ec991d92f1ad
Signed-off-by: Tudor Ambarus <tudor.ambarus@freescale.com>
Signed-off-by: Horia Geanta <horia.geanta@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/7063
Reviewed-by: Mircea Pop <mircea.pop@freescale.com>
Reviewed-by: Cristian Stoica <cristian.stoica@freescale.com>
Reviewed-by: Thomas Trefny <Tom.Trefny@freescale.com>
Tested-by: Zhenhua Luo <zhenhua.luo@freescale.com>
(cherry picked from commit 5c235b1ce4ad0b53e86fe157b4add7079934f614)
Reviewed-on: http://git.am.freescale.net:8181/10377
Reviewed-by: Alexandru Porosanu <alexandru.porosanu@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Commit 33de5f5c7455aea05b48d46f3024f78ecc83dc4b
(crypto: caam - add support for TLS 1.0 record)
added support for TLS 1.0 offloading, mentioning that the feature is
available for platforms having SEC Era 4 or above.
However, this doesn't stop one to actually run this feature on platforms
not supported (for e.g. P3041DS), leading to errors like:
platform ffe303000.jr: 40002807: DECO: desc idx 40: Invalid LOAD Command
Add a .min_era member for each algorithm registered by the driver,
specifying the lowest (compatible) SEC Era on which the descriptors
can run.
Change-Id: Idf929591361d244a4d7cd8352d0fb8ad7feff830
Signed-off-by: Horia Geanta <horia.geanta@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/7118
Reviewed-by: Mircea Pop <mircea.pop@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Thomas Trefny <Tom.Trefny@freescale.com>
(cherry picked from commit 351d2c869e446187bc78f47dccb0213f0a5e9f17)
Conflicts:
drivers/crypto/caam/caamalg.c
drivers/crypto/caam/ctrl.c
drivers/crypto/caam/intern.h
Change-Id: I615578f0d0693eb46742e65004435821f6eb7de7
Reviewed-on: http://git.am.freescale.net:8181/10374
Reviewed-by: Cristian Stoica <cristian.stoica@freescale.com>
Reviewed-by: Mircea Pop <mircea.pop@freescale.com>
Reviewed-by: Alexandru Porosanu <alexandru.porosanu@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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TLS 1.0 descriptors run on SEC Era 4 or higher.
For now, only tls10(hmac(sha1),cbc(aes)) algorithm
is registered by the driver.
Change-Id: I98a71d8eb61a0e5f2dd65835e99b1c906468bf52
Signed-off-by: Tudor Ambarus <tudor.ambarus@freescale.com>
Signed-off-by: Horia Geanta <horia.geanta@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10376
Reviewed-by: Cristian Stoica <cristian.stoica@freescale.com>
Reviewed-by: Mircea Pop <mircea.pop@freescale.com>
Reviewed-by: Alexandru Porosanu <alexandru.porosanu@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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The test vector for zero plaintext tls encrypt had a typo in it:
the pre ICV len (last two bytes of assoc data) were being set to
"00 10" instead of "00 00".
This caused the result (SHA1 + padding) to be different than expected.
Change-Id: I81ef14f0e1f8660854ad2faaf13bc2a9fdca5755
Signed-off-by: Horia Geanta <horia.geanta@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/7062
Reviewed-by: Mircea Pop <mircea.pop@freescale.com>
Reviewed-by: Cristian Stoica <cristian.stoica@freescale.com>
Reviewed-by: Thomas Trefny <Tom.Trefny@freescale.com>
Tested-by: Zhenhua Luo <zhenhua.luo@freescale.com>
(cherry picked from commit dd23644ca6c56cb3b8ee5b3d6c22e3ee6c17f957)
Reviewed-on: http://git.am.freescale.net:8181/10375
Reviewed-by: Alexandru Porosanu <alexandru.porosanu@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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This patch adds kernel support for encryption/decryption of TLS 1.0
records using block ciphers. Implementation is similar to authenc in the
sense that the base algorithms (AES, SHA1) are combined in a template to
produce TLS encapsulation frames. The composite algorithm will be called
"tls10(hmac(<digest>),cbc(<cipher>))". The cipher and hmac keys are
wrapped in the same format used by authenc.c
Change-Id: If2211062f1e8805ee1fe9e6684e7c0902bf44467
Signed-off-by: Cristian Stoica <cristian.stoica@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/6211
Reviewed-by: Mircea Pop <mircea.pop@freescale.com>
Reviewed-by: Thomas Trefny <Tom.Trefny@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
(cherry picked from commit e2fe61d3fe94949f9fc5766f7b27a1d19c9d4d6e)
Conflicts:
crypto/tcrypt.c
Signed-off-by: Horia Geanta <horia.geanta@freescale.com>
Change-Id: I6ecb63c7cb8c64aef984e71e439dab6000666b29
Reviewed-on: http://git.am.freescale.net:8181/10373
Reviewed-by: Cristian Stoica <cristian.stoica@freescale.com>
Reviewed-by: Mircea Pop <mircea.pop@freescale.com>
Reviewed-by: Alexandru Porosanu <alexandru.porosanu@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com>
Change-Id: I10e8467953cf8524a2848f4b474952ea54ed7868
Reviewed-on: http://git.am.freescale.net:8181/6049
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Thomas Trefny <Tom.Trefny@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10198
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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USB controller version-2.5 requires to enable internal UTMI phy and program PTS field
in PORTSC register before asserting controller reset. This is must for successful
resetting of the controller and subsequent enumeration of usb devices
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Change-Id: Ibebdc44bf75f5da69f2e9b6346bfecb442a784b0
Reviewed-on: http://git.am.freescale.net:8181/10301
Reviewed-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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AT8033 can't work well with auto-negotiation.
Add .config_intr and .ack_interrupt functions for at8033_driver
to config AT8033 to enable interrupt for auto-negotiation.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Change-Id: I47b539cf5fc9da52c6980e95e1bd105621abf102
Reviewed-on: http://git.am.freescale.net:8181/10282
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Historically the offline port driver did not initialize the frame queues that
entered and exited the OH port and relied on software components (Ethernet
driver, USDPAA, other kernel modules) to initialize those queues.
The last major modification in the offline port driver added capabilities to
initialize ingress queues (queues that enter the Offline Port) simplifying
the work for the Ethernet driver, but maintaining the same complexity in USDPAA
and/or other kernel modules.
This patch adds full capability for initializing both ingress and egress
queues, eliminating the dependency on USDPAA and/or other kernel modules. With
it, complex offload architectures that have OH ports can be largely initialized
by the offline port driver.
The additional device tree attributes that this patch adds are optional and do
not interfere with the current code. Therefore, backward compatibility is
maintained.
This patch also simplifies the initialization of the hardware used by the
macless or the newer Ethernet driver, oNIC. Test scenarios (mainly unit tests)
can be created without using USDPAA or Offload Driver.
The device tree format for the new attributes is:
fsl,qman-frame-queues-ingress = <base_id1 count1 ... base_idn countn>;
fsl,qman-frame-queues-egress = <base_id1 count1 ... base_idn countn>;
fsl,qman-channel-ids-egress = <channel_id1 ... channel_idn>;
The above queues are connected only to DC portals. Frame queues connected to SW
portals should be created from another software entity. Also, if a frame queue
uses different initialization parameters it should be created by another
software entity.
Change-Id: I0fffc6116bbf543542c30eb6225b2a76945d3813
Signed-off-by: Marian Rotariu <marian.rotariu@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/9648
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
Reviewed-by: Bogdan Purcareata <bogdan.purcareata@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
(cherry picked from commit 43c88bc759c12472262788d8f39dd3d79c6f5e44)
Reviewed-on: http://git.am.freescale.net:8181/10296
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Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Change-Id: If203b15d0f34b4ace5bd8cb911af1ebf93aa5621
Reviewed-on: http://git.am.freescale.net:8181/10396
Reviewed-by: Igal Liberman <Igal.Liberman@freescale.com>
Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
(cherry picked from commit e8a3fbfddce62f064132632b16682f3dac093e77)
Reviewed-on: http://git.am.freescale.net:8181/10403
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Currently the system wakes up from sleep mode on Magic Packets.
The ports that are configured as Auto Response will not have the
WoL feature enabled. Magic Packets are not yet supported on
those ports.
Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Change-Id: I579494dab0a0e918a2644483129951d370cbccf9
Reviewed-on: http://git.am.freescale.net:8181/9904
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
(cherry picked from commit 0d0575e647c95c988148a107839a1c1f31baa420)
Reviewed-on: http://git.am.freescale.net:8181/10401
Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
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Magic Packets are processed in Fman error interrupt therefore
in order for the error interrupt to be handled while the system
is in sleep mode, we set the IRQF_NO_SUSPEND flag when the
interrupt is being registered.
Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Change-Id: Iff2fec80452a1af42ffc9a639bed555d896a57af
Reviewed-on: http://git.am.freescale.net:8181/9903
Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Tested-by: Jose Rivera <German.Rivera@freescale.com>
(cherry picked from commit 3cc4c999ce457e5a99ae0cac7626106b9a551511)
Reviewed-on: http://git.am.freescale.net:8181/10399
Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
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Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Change-Id: I244de770e6b6e86855c57db19940e58da846f1c6
Reviewed-on: http://git.am.freescale.net:8181/9902
Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Tested-by: Jose Rivera <German.Rivera@freescale.com>
(cherry picked from commit 639b1743204984ab49f6d5a0f57fa94d76dcbf22)
Reviewed-on: http://git.am.freescale.net:8181/10387
Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
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Handle TxFIFO underrun exceptions outside the fast path.
A controller reset is more reliable in this exceptional
case, as opposed to re-enabling on-the-fly the Tx DMA.
As the controller reset is handled outside the fast path
by the reset_gfar() workqueue handler, the locking
scheme on the Tx path is significantly simplified.
Because the Tx processing (xmit queues and tx napi) is
disabled during controller reset, tstat access from xmit
does not require locking. So the scope of the txlock on
the processing path is now reduced to num_txbdfree, which
is shared only between process context (xmit) and softirq
(clean_tx_ring). As a result, the txlock must not guard
against interrupt context, and the spin_lock_irqsave()
from xmit can be relaced by faster spin_lock_bh().
Locking restrictions can be reduced for clean_tx_ring()
as well.
Change-Id: Ib1fb6fe8d0d59fbf0abb7c39cf6b52c112a8a2cb
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/9989
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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In bman_create_affine_slave() function :
- we used put_affine_portal() which should be called along with
get_affine_portal() or get_raw_affine_portal().
- unnecessary call to put_affine_portal() leaves the function in
invalid state and resulted in kernel panic.
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@freescale.com>
Signed-off-by: Priyanka Jain <priyanka.jain@freescale.com>
Change-Id: I52a98c18b20d6f83f86ce462005f43e26fa1bdd9
Reviewed-on: http://git.am.freescale.net:8181/10283
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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T1040RDB don't have the UCC uart port, change UCC uart node to
UCC hdlc node.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Change-Id: I5608746d9e31f1dd74b5574e6dd4f95963f0f8cb
Reviewed-on: http://git.am.freescale.net:8181/10008
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10279
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add qe node into file arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Change-Id: I7de5a4fe3c30130d3b00e3e9dd84a6193b38caf4
Reviewed-on: http://git.am.freescale.net:8181/10278
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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This is a new flavour of DPAA Ethernet Driver designed to be used in offload
scenarios similar to DPAA Offload Driver. It was developed on top of current
macless driver implementation adding 0-copy, CSUM offload and the ability to
manage its own buffer pools.
oNIC communicates with the underlying architecture by using two different O/H
ports, one for Rx and one for Tx.
Change-Id: Ifd59231470a62c272543ff4b0db1b6ab7e1893b1
Signed-off-by: Marian Rotariu <marian.rotariu@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/9023
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
(cherry picked from commit bc625b9f52b9ba0734698cc74187475d333bf160)
Reviewed-on: http://git.am.freescale.net:8181/10258
Tested-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
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This additional parameter (window number) is required based
on the latest update of pamu driver.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: I449919d7d89f3a91b6fe120970911487006fccca
Reviewed-on: http://git.am.freescale.net:8181/10184
Reviewed-by: Varun Sethi <Varun.Sethi@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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This is a temporary workaround:
The fifosize calculation process will be simplified
later as part of the removal of the
CONFIG_FMAN_RESOURCE_ALLOCATION_ALGORITHM
functionality
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Change-Id: I508b0493908804b6a904ab65164b1803f75b7d58
Reviewed-on: http://git.am.freescale.net:8181/10160
Reviewed-by: Igal Liberman <Igal.Liberman@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Tested-by: Jose Rivera <German.Rivera@freescale.com>
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The DMA mapping record was not being removed from a
processes DMA map when dma_mem_destroy() is called. This
made it impossible to remap the same named segment without
restarting the process
Signed-off-by: Roy Pledge <Roy.Pledge@freescale.com>
Change-Id: I2b92a022e6cb7815056567487688c39774a5008f
Reviewed-on: http://git.am.freescale.net:8181/10180
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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To acknowledge a DQRR entry, the portal should be preserved in same mode
as it was when the DQRR entry was created. Function qm_dqrr_init() is
invoked when a raw portal is released back. The raw portal could be
either in one of cci or cci or cdc modes. So while cleaning up a portal
using qm_dqrr_init(), the dqrr consumption mode should be read and
accordingly approriate DQRR consumption routine should be invoked.
Signed-off-by: Vakul Garg <vakul@freescale.com>
Change-Id: I07b412915cd483060147a845cfe935d0bd7f2024
Reviewed-on: http://git.am.freescale.net:8181/9634
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
Reviewed-by: Geoff Thorpe <Geoff.Thorpe@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Multi-Queue polling support is phasing out, as it
imposes unnecessary processing overhead that degenerates
in Tx congestion and even Tx timeout.
Its place is taken by Single-Queue polling and all the
currently supported gianfar devices already work in
Single-Queue polling mode. So the Multi-Queue polling
may be compiled out, for better performance (i.e. icache
utilization).
Change-Id: I1f1ff4edd112606135e6c99780fd54f333cdb0e9
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/9990
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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T1040 FSL SoC has new version of UART controller which
can support 64byte FiFo. Add suuport to enable 64byte FiFO mode
-FCR[EN64] needs to be programmed to 1 to enable it.
-Also, when FCR[EN64]==1, RTL bits to be used as below
to define various Receive Trigger Levels:
-FCR[RTL] = 00 1 byte
-FCR[RTL] = 01 16 bytes
-FCR[RTL] = 10 32 bytes
-FCR[RTL] = 11 56 bytes
-tx_loadsz is set tp 32bytes, As some issues are observed with
64-byte mode which looks to be Si issue.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Change-Id: I0b32f3230bd1c9674a2e85cc4e5a16869dbaa9af
Reviewed-on: http://git.am.freescale.net:8181/10215
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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T1042RDB_PI is Freescale Reference Design Board supporting the T1042
QorIQ Power Architecture™ processor. T1042 is a reduced personality
of T1040 SoC without Integrated 8-port Gigabit. The board is designed
with low power features targeted for Printing Image Market.
T1042RDB_PI is similar to T1040RDB board with few differences like
it has video interface, supports T1042 personality
T1042RDB_PI board Overview
-----------------------
- SERDES Connections, 8 lanes supporting:
- PCI
- SATA 2.0
- DDR Controller
- Supports rates of up to 1600 MHz data-rate
- Supports one DDR3LP UDIMM
-IFC/Local Bus
- NAND flash: 1GB 8-bit NAND flash
- NOR: 128MB 16-bit NOR Flash
- Ethernet
- Two on-board RGMII 10/100/1G ethernet ports.
- PHY #0 remains powered up during deep-sleep
- CPLD
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- SERDES clocks
- Power Supplies
- USB
- Supports two USB 2.0 ports with integrated PHYs
- Two type A ports with 5V@1.5A per port.
- SDHC
- SDHC/SDXC connector
- SPI
- On-board 64MB SPI flash
- I2C
- Device connected: EEPROM, thermal monitor, VID controller, RTC
- Other IO
- Two Serial ports
- ProfiBus port
Add support for T1040 RDB board:
-add device tree
-Add entry corenet_generic.c, as it is similar to other corenet platforms
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Xie Xiaobo <r63061@freescale.com>
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Change-Id: If3b9122a044312ce458739883aafa65c2436e1e1
Reviewed-on: http://git.am.freescale.net:8181/10136
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Qiang Zhao <qiang.zhao@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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T1040RDB is Freescale Reference Design Board supporting
the T1040 QorIQ Power Architecture™ processor.
T1040RDB board Overview
-----------------------
- SERDES Connections, 8 lanes supporting:
- PCI
- SGMII
- QSGMII
- SATA 2.0
- DDR Controller
- Supports rates of up to 1600 MHz data-rate
- Supports one DDR3LP UDIMM
-IFC/Local Bus
- NAND flash: 1GB 8-bit NAND flash
- NOR: 128MB 16-bit NOR Flash
- Ethernet
- Two on-board RGMII 10/100/1G ethernet ports.
- PHY #0 remains powered up during deep-sleep
- CPLD
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- SERDES clocks
- Power Supplies
- USB
- Supports two USB 2.0 ports with integrated PHYs
- Two type A ports with 5V@1.5A per port.
- SDHC
- SDHC/SDXC connector
- SPI
- On-board 64MB SPI flash
- I2C
- Devices connected: EEPROM, thermal monitor, VID controller
- Other IO
- Two Serial ports
- ProfiBus port
Add support for T1040 RDB board:
-add device tree
-add entry in Kconfig to build
-Add entry corenet_generic.c, as it is similar to other corenet platforms
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Stefan Sicleru <stefan.sicleru@freescale.com>
Signed-off-by: Alex MARGINEAN <alexandru.marginean@freescale.com>
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Change-Id: I74d0240522572912995754aecfc3b2d15a48f9fe
Reviewed-on: http://git.am.freescale.net:8181/10135
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Qiang Zhao <qiang.zhao@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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T104xQDS board Overview
-----------------------
- SERDES Connections, 8 lanes supporting:
- PCI Express: supporting Gen 1 and Gen 2
- SGMII
- QSGMII
- SATA 2.0
- DDR Controller
- Supports rates of up to 1600 MHz data-rate
- Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
- IFC/Local Bus
- NAND flash: 8-bit, async, up to 2GB.
- NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- GASIC: Simple (minimal) target within Qixis FPGA
- PromJET rapid memory download support
- Ethernet
- Two on-board RGMII 10/100/1G ethernet ports.
- PHY #0 remains powered up during deep-sleep (T1040 only)
- QIXIS System Logic FPGA
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- SERDES clocks
- Power Supplies
- Video
- DIU supports video at up to 1280x1024x32bpp
- USB
- Supports two USB 2.0 ports with integrated PHYs
- Two type A ports with 5V@1.5A per port.
- Second port can be converted to OTG mini-AB
- SD/MMC Interface
- SDHC port connects directly to an adapter card slot, featuring:
- Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
- Supporting eMMC memory devices
- SPI
- On-board support of 3 different devices and sizes
- TDM
- QE-TDM
- Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports
Add support for T104x QDS board (T1040QDS, T1042QDS):
-add device tree
-add entry is added in corenet_generic.c as it is similar to other corenet
platforms.
-add entry in Kconfig to build
-add t1040_32bit_smp_defconfig, t1040_64bit_smp_defconfig
-T1040 has FMANv3, hence CONFIG_FMAN_T4240 needs to be defined.
-So corenet32_smp_defconfig and corenet64_smp_defconfig cannot be used.
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com>
Signed-off-by: Stefan Sicleru <stefan.sicleru@freescale.com>
Signed-off-by: Alex Marginean <alexandru.marginean@freescale.com>
Signed-off-by: Razvan Stefanescu <razvan.stefanescu@freescale.com>
Signed-off-by: Nikhil Badola <Nikhil.Badola@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Change-Id: Icfd66c050fbbc39a8693e6b00550736fa9313e12
Reviewed-on: http://git.am.freescale.net:8181/10134
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Qiang Zhao <qiang.zhao@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking & telecommunications.
T1042 personality is a reduced personality of T1040 without Integrated 8-port
Gigabit Ethernet switch.
The T1040/T1042 SoC includes the following function and features:
- Four e5500 cores, each with a private 256 KB L2 cache
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion
management
- Cryptography Acceleration (SEC 5.0)
- RegEx Pattern Matching Acceleration (PME 2.2)
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
- Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch (T1040 only)
- Four 1 Gbps Ethernet controllers
- Two RGMII interfaces or one RGMII and one MII interfaces
- High speed peripheral interfaces
- Four PCI Express 2.0 controllers running at up to 5 GHz
- Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
- Upto two QSGMII interface
- Upto six SGMII interface supporting 1000 Mbps
- One SGMII interface supporting upto 2500 Mbps
- Additional peripheral interfaces
- Two USB 2.0 controllers with integrated PHY
- SD/eSDHC/eMMC
- eSPI controller
- Four I2C controllers
- Four UARTs
- Four GPIO controllers
- Integrated flash controller (IFC)
- LCD/ HDMI interface (DIU) with 12 bit dual data rate
- TDM interface: QE, SLIC
- Multicore programmable interrupt controller (PIC)
- Two 8-channel DMA engines
- Single source clocking implementation
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com>
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Stefan Sicleru <stefan.sicleru@freescale.com>
Signed-off-by: Alex Marginean <alexandru.marginean@freescale.com>
Signed-off-by: Razvan Stefanescu <razvan.stefanescu@freescale.com>
Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Signed-off-by: Ganga Negi <ganga.negi@freescale.com>
Signed-off-by: Nikhil Badola <Nikhil.Badola@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
Change-Id: Ib0a9e1a717080fd246b308a049f0f57beb4fe048
Reviewed-on: http://git.am.freescale.net:8181/10133
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Qiang Zhao <qiang.zhao@freescale.com>
Reviewed-by: Yuantian Tang <yuantian.tang@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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The driver add hdlc support for Freescale QUICC Engine.
It support NMSI and TSA mode.
Signed-off-by: Xie Xiaobo <r63061@freescale.com>
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Change-Id: Iece969b4934241f0f1cb574c5014600ef63cfb95
Reviewed-on: http://git.am.freescale.net:8181/10113
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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There is no indication that the proxy interface successfully initialized the
attached MAC device. In this way, the user does not know if the device tree
is misconfigured or the MAC device successfully probed. Other ways to check
the MAC initialization exists, like MAC mem mapped registers, but a simple
message in the bootlog seems way more user-friendly.
Signed-off-by: Marian Rotariu <marian.rotariu@freescale.com>
Change-Id: I79b38719e6b49d8a4557b885a2b13854961f9b32
Reviewed-on: http://git.am.freescale.net:8181/9258
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
(cherry picked from commit f217d812c07a1be0563dffe40f4736442b5f99ee)
Reviewed-on: http://git.am.freescale.net:8181/9263
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Currently, if macless or shared Ethernet drivers have several buffer pools only
the first buffer pool will be initialized with a seeding procedure. With this
patch all configured buffer pools will have a seeding procedure.
Also, this patch removes unnecessary BUG_ON() from the bp initialization
function and fixes the release of bp structures.
Change-Id: Ie1fe6689867e921ccc75afbf50dfd5560c9216e9
Signed-off-by: Marian Rotariu <marian.rotariu@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/9873
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
Reviewed-by: Ruxandra Ioana Radulescu <ruxandra.radulescu@freescale.com>
(cherry picked from commit fda11c93afa1bdb71e34d07509305ff0df4a62a0)
Reviewed-on: http://git.am.freescale.net:8181/10176
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we use mtdparts way to setup the partitions of flash devices
instead of putting partitions info in dts.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Change-Id: I74abccf2c32f5f4da8cccf4aec3a85814d4718af
Reviewed-on: http://git.am.freescale.net:8181/10014
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Add suspend and resume function to qe-tdm.
Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com>
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Change-Id: I81cac61575196957d28071ebf3f77be848494ff7
Reviewed-on: http://git.am.freescale.net:8181/9216
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10111
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Signed-off-by: Jiucheng Xu <Jiucheng.Xu@freescale.com>
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Change-Id: I3841888a780f6d4d3d38589c5de4cdd3916921ef
Reviewed-on: http://git.am.freescale.net:8181/9214
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10110
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There is QE on platform T104x, add support.
Call funcs qe_ic_init and qe_init if CONFIG_QUICC_ENGINE is defined.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Change-Id: I7d33f4237aabadfc63d4e55d96ebdb64fb396736
Reviewed-on: http://git.am.freescale.net:8181/10099
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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micro QE is a kind of cutted QE, it has only 2 UCCs while
normal QE has up to 8 UCCs.
micro QE doesn't have par_io, it doesn't need to init par_io
for micro QE.
Split function mpc85xx_qe_init() into mpc85xx_qe_init()
and mpc85xx_qe_par_io_init().
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Change-Id: I267d044d6b0c6ff1c4bba984566d430e6b3dc682
Reviewed-on: http://git.am.freescale.net:8181/10098
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Define a QE init function in common file, and avoid
the same codes being duplicated in board files.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Change-Id: I394c2eac02ef40fb923b5ee5f74e919065f8a4ac
Reviewed-on: http://git.am.freescale.net:8181/10106
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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There is an "if condition" uncorrect, modify it.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Change-Id: I5c3931a34e41c0eec34aead95254a37e919c45bb
Reviewed-on: http://git.am.freescale.net:8181/10097
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Support added for USB controller version-2.5 used in
T4240 rev2.0, T1023, B3421, T1040, T2080
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Change-Id: Ib45b486a23d177ef3570ee234fe9a5af06f36b43
Reviewed-on: http://git.am.freescale.net:8181/9643
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Suresh Gupta <suresh.gupta@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Change USB controller version to 2.5 in compatible string for T4240 rev2.0
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Change-Id: I92aa23cee236c13547b59bf62ef68f1d6002f2ff
Reviewed-on: http://git.am.freescale.net:8181/9638
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Suresh Gupta <suresh.gupta@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Change USB controller version to 2.5 in compatible string for T2080
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Change-Id: I4a539e3e0984e418c09a3d64405f9b844f404289
Reviewed-on: http://git.am.freescale.net:8181/7459
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
(cherry picked from commit cd37bcac41666cccb7fdf84e475967630848d257)
Change-Id: I4a539e3e0984e418c09a3d64405f9b844f404289
Reviewed-on: http://git.am.freescale.net:8181/9835
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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As a part of PKC support, RSA, DSA DH, ECDH, ECDSA requires key
generation. The patch adds support for key generation support
for DSA, ECDSA, DH, ECDH.
The patch adds DH operation support too
Signed-off-by: Yashpal Dutta <yashpal.dutta@freescale.com>
Change-Id: I0dc9c144a23e2248bf8974a1615363341dc4886e
Reviewed-on: http://git.am.freescale.net:8181/5867
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Geanta Neag Horia Ioan-B05471 <horia.geanta@freescale.com>
Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/9551
Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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CAAM driver updates as per public key infrastructure changes in cryptoAPI
RSA, DSA, ECDSA are support as part of Public Key Crypto Operations
Signed-off-by: Yashpal Dutta <yashpal.dutta@freescale.com>
Change-Id: I3a6e4f71866a5ef157b9ea13e618c4d3d209f558
Reviewed-on: http://git.am.freescale.net:8181/5839
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Geanta Neag Horia Ioan-B05471 <horia.geanta@freescale.com>
Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/9546
Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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Platform can go in sleep where CAAM will remain power ON while in some
cases CAAM will be powered off during deep-sleep. The patch handles
graceful recovery of CAAM state in both the power-up and powered-down
cases across deep-sleep.
Signed-off-by: Yashpal Dutta <yashpal.dutta@freescale.com>
Change-Id: Ie27fdfa78fc50c9a05f6316938ad42a70a89a48e
Reviewed-on: http://git.am.freescale.net:8181/9771
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/10085
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Job ring is suspended gracefully and resume afresh.
Pending Jobs not yet processed by CAAM are marked with error for
producer to either discard Job or retry after resume.
UIO based Job Rings are not handled by this patch.
Signed-off-by: Yashpal Dutta <yashpal.dutta@freescale.com>
Change-Id: I654734c460e0307243884a076350602ccb97a15a
Reviewed-on: http://git.am.freescale.net:8181/9772
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/9988
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The P1010 device tree restricts the number of
supported interrupt groups to 1, although the eth
controller can support 2 interrupt groups and the
driver assumes the Multi-Group mode ("fsl,etsec2" model).
So, in this case the assumption that the Multi-Group
mode (MQ_MG_MODE) devices always support 2 interrupt
groups is false. To fix this, a check for the actual
number of interrupt groups enabled in the board's
device tree has been added in gfar_probe for the
"fsl,etsec2" devices.
Without this fix, P1010 based boards claim support for
2 Tx queues to the net stack but only one is actually
allocated, leading to NULL access in xmit. This issue
was introduced by enabling Single-Queue polling for
the P1010 devices.
Change-Id: I74e2d143557a7e2cebce8928ac42160e79957f0c
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/9876
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Rajan Gupta <rajan.gupta@freescale.com>
Reviewed-by: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
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Added dts files for running the dpa offloading applications on T2080QDS
board.
Change-Id: Ifa23fc1adbf479e2cc5542db3600ef243b96608e
Signed-off-by: Aurelian Zanoschi <Aurelian.Zanoschi@freescale.com>
Signed-off-by: Marian Chereji <marian.chereji@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/8821
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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To support freescale XFI 10GBASE-KR, the driver comply with
IEEE802.3-2008 to do auto-negotiation and link training with link
partner(LP) which has capability of 10GBASE-KR.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Change-Id: I1847226078017b4ca74a39f0d611a96f66921d23
Reviewed-on: http://git.am.freescale.net:8181/9918
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Heinz Wrobel <Heinz.Wrobel@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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layer
The layer which registers with the crypto API should check for the presence of
the CAAM device it is going to use. If the platform's device tree doesn't have
the required CAAM node, the layer should return an error and not register the
algorithms with crypto API layer.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Change-Id: Idf361e8ae971929c55abdefaa29f9d7bc8441a72
Reviewed-on: http://git.am.freescale.net:8181/10043
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Horia Ioan Geanta Neag <horia.geanta@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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To specify spi flash layouts by "mtdparts=..." in cmdline, we must
give mtd_info a fixed name,because the cmdlinepart's parser will
match the name of mtd_info given in cmdline.
Now, if use DT, the mtd_info's name will be spi->dev->name. It
consists of spi_master->bus_num, and the spi_master->bus_num maybe
dynamically fetched. So, in this case, replace the component bus_num
with thei physical address of spi master.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Change-Id: I36a6105a43ea408507576a98642cf80c2b2837e4
Reviewed-on: http://git.am.freescale.net:8181/10040
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: Jose Rivera <German.Rivera@freescale.com>
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