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2013-04-09Merge tag 'tegra-for-3.10-dt' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt2 From Stephen Warren <swarren@wwwdotorg.org>: ARM: tegra: device tree changes This branch contains the majority of the device tree changes for Tegra. Highlights include: * Many changes for Tegra114, and the Dalmore board, to enable pinctrl, SDHCI/MMC, PWM, DMA, I2C, KBC, SPI, battery, regulators. * Adding or enabling suspend wakeup sources on many boards, and adding suspend timing parameters, to support the system suspend patches. * Adding clocks to the audio-related nodes, so that in 3.11, the audio driver can pull these clocks from device tree rather than hard-coding clock names. * Some small DT fixes/cleanup. This branch is based on the previous clk pull request. * tag 'tegra-for-3.10-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (25 commits) clk: tegra: Fix cdev1 and cdev2 IDs ARM: dts: tegra: add the PM configurations of PMC ARM: tegra: add non-removable and keep-power-in-suspend property for MMC ARM: tegra: whistler: add wakeup source for KBC ARM: tegra: add power gpio keys to DT ARM: tegra: keep power on to SD slot on Dalmore ARM: tegra: add clocks property to AC'97 sound nodes ARM: tegra: add clocks property to sound nodes ARM: tegra: dalmore: add fixed regulator node ARM: tegra: dalmore: add TPS65090 node ARM: tegra: dalmore: add cpu regulator node ARM: tegra: Add sbs-battery node to Dalmore ARM: tegra: add DT binding for i2c-tegra ARM: tegra: add SPI nodes to Tegra114 DT ARM: tegra: add KBC nodes to Tegra114 DT ARM: tegra: add aliases and DMA requestor for serial nodes of Tegra114 ARM: tegra: add I2C nodes to Tegra114 DT ARM: tegra: add APB DMA nodes to Tegra114 DT ARM: tegra: add PWM nodes to Tegra114 DT ARM: tegra: fix the status of PWM DT nodes ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-09Merge branch 'tegra/clk' into next/dt2Arnd Bergmann
This is a dependency for the tegra/dt branch. Conflicts: drivers/clocksource/tegra20_timer.c Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-04-04clk: tegra: Fix cdev1 and cdev2 IDsPrashant Gaikwad
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: split into separate driver and device-tree patches] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04ARM: tegra: fix the status of PWM DT nodesAndrew Chew
We should be defining the PWM nodes with status as "disabled" in the chip-specific dtsi file, since we don't know whether specific boards will use the PWM or not. This patch fixes the PWM node status for Tegra20 and Tegra30. Also fixed the one user of PWM, which is the Tegra20 medcom-wide board, so that PWM is set to "okay" in the board-specific dts file. Signed-off-by: Andrew Chew <achew@nvidia.com> [swarren: in medcom-wide: fixed node sort order, removed duplicate pwm: label, fixed syntax error] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04ARM: tegra: fix sort order of USB PHY nodesStephen Warren
The USB PHY nodes are all grouped together rather than being sorted based on reg address like all other nodes fix this. I apologize for the churn; I should have noticed this during review of the patches that caused this. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04ARM: tegra: device tree whitespace cleanupStephen Warren
Remove white-space from empty line; triggers checkpatch. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-04-04Merge branch 'for-3.10/soc' into for-3.10/clkStephen Warren
2013-04-03ARM: tegra: add clock source of PMC to device treesJoseph Lo
Adding the bindings of the clock source of PMC in DT. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-22ARM: tegra: fix register address of slink controllerLaxman Dewangan
Fix typo on register address of slink3 controller where register address is wrongly set as 0x7000d480 but it is 0x7000d800. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: <stable@vger.kernel.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-03-11clocksource: tegra: move to of_clk_getPeter De Schrijver
The new clockframework introduced DT IDs for each clock. To be able to remove the device registrations, this driver needs to be updated to use the DT IDs. Note that the actual removal of the clk_register_clkdev() calls will be done in a later series. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-05ARM: Tegra: Add clock entry for smp_twd clockPrashant Gaikwad
As DT support for clocks and smp_twd is enabled, add clock entry for smp_twd clock to DT. This fixes the following error while booting the kernel: smp_twd: clock not found -2 Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: include kernel log spew that this fixes] Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-02-13ARM: tegra: remove clock-frequency properties from serial nodesStephen Warren
Currently, the serial nodes define both a clock-frequency and a clocks property. We should not provide both, since they might conflict. In practice, this also causes problems since the of_serial driver uses the clock-frequency property in preference to the clocks property, and hence doesn't clk_prepare_enable() the clock, which may then leave it with no known users, and hence the common clock framework will disable it, thus breaking the port, which is usually the console. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-29ARM: dt: tegra20: Rename "gart" to "iommu"Hiroshi Doyu
Use functional name for DT entry instead of h/w name. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsiLucas Stach
No Tegra20 Platform is running PLL_P at another rate than 216MHz, nor is any using any other PLL as UART source clock. Move attribute into SoC level dtsi file to slim down board DT files. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: add DT entry for KBC controllerLaxman Dewangan
NVIDIA's Tegra SoCs have the matrix keyboard controller which supports 16x8 type of matrix. The number of rows and columns are configurable. Add DT entry for KBC controller. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: added clocks property] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: swap cache-/interrupt-ctrlr nodes in DTStephen Warren
This ensures nodes are sorted in order of reg address. This makes it easier to compare against e.g. the U-Boot device trees, and is simply consistent and clean. While we're at it, remove the unit address from the cache-controller node name, since it's unique without it. Reported-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ASoC: tegra: add ac97 host controller to device treeLucas Stach
Add default entry for the AC97 host controller. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: dts: add aliases and DMA requestor for serial controllerLaxman Dewangan
Add APB DMA requestor and serial aliases for serial controller. There will be two serial driver i.e. 8250 based simple serial driver and APB DMA based serial driver for higher baudrate and performace. The simple serial driver get enabled with compatible nvidia,tegra20-uart and APB DMA based driver will get enabled with compatible nvidia,tegra20-hsuart. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28Merge branch 'for-3.9/scu-base-rework' into for-3.9/soc-t114Stephen Warren
Conflicts: arch/arm/mach-tegra/platsmp.c
2013-01-28ARM: tegra: add clocks properties to USB PHY nodesStephen Warren
The patch to add USB PHY nodes to device tree was written before Tegra supported the clocks property in device tree. Now that it does, add the required clocks properties to these nodes. This will allow all clk_get_sys() calls in tegra_usb_phy.c to be replaced by clk_get(phy->dev, clock_name), as part of converting the PHY driver to a platform driver. Acked-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: add DT nodes for Tegra USB PHYVenu Byravarasu
Add DT nodes for Tegra USB PHY along with related documentation. Also added a phandle property to controller DT node, for referring to connected PHY instance. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: Add new DT property to USB node.Venu Byravarasu
As Tegra USB host driver is using instance number for resetting PORT0 twice, adding a new DT property for handling this. Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: add clock properties to Tegra20 DTPrashant Gaikwad
Add clock information to device nodes. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: define Tegra20 CAR bindingStephen Warren
The Tegra20 CAR (Clock And Reset) Controller controls most aspects of most clocks within Tegra20. The device tree binding models this as a single monolithic clock provider, which exports many clocks. This reduces the number of nodes needed in device tree to represent these clocks. This binding is only useful for Tegra20; the set of clocks that exists on Tegra30 is sufficiently different to merit its own binding. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> [pgaikwad: Added mux clk ids and sorted CAR node] Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-01-28ARM: tegra: Add CPU nodes to Tegra20 device treeHiroshi Doyu
Add CPU node for Tegra20. Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16ARM: tegra: add TWD to device treeStephen Warren
This will allow timer.c to use twd_local_timer_of_register(), and hence not need to hard-code the TWD address or IRQ. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16ARM: tegra: define DT bindings for and instantiate RTCStephen Warren
The Tegra RTC maintains seconds and milliseconds counters, and five alarm registers. The alarms and other interrupts may wake the system from low-power state. Define a DT binding for this HW module, and add the module into the Tegra device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-16ARM: tegra: define DT bindings for and instantiate timerStephen Warren
The Tegra timer provides a number of 29-bit timer channels, a single 32-bit free running counter, and in the Tegra30 variant, 5 watchdog modules. The first two channels may also trigger a legacy watchdog reset. Define a DT binding for this HW module, and add the module into the Tegra device tree files. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-15ARM: tegra: Add Tegra20 host1x supportThierry Reding
Add the host1x node along with its children to the Tegra20 DTSI. Board- specific DTS files are expected to enable the available outputs and complement the device tree with data specific to the hardware. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-15ARM: tegra: dts: add sflash controller dt entryLaxman Dewangan
Nvidia's Tegra20 have the SPI (SFLASH) controller to interface with spi flash device which is used for system boot. Add DT entry for this controller. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> [swarren: move sflash node to keep file sorted] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-15ARM: tegra: dts: add slink controller dt entryLaxman Dewangan
Add slink controller details in the dts file of Tegra20 and Tegra30. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-05ARM: tegra: dt: add L2 cache controllerJoseph Lo
Add L2 cache controller binding into DT for Tegra. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-10-07ARM: tegra: fix invalid unit-address in tegra*.dtsiStephen Warren
Unit addresses, whilst written in hex, don't contain a 0x prefix. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Olof Johansson <olof@lixom.net>
2012-09-20ARM: tegra: dts: Add pwm labelThierry Reding
PWM devices can be referenced in the DT by phandle and per-chip index. In order for this to work properly, the PWM controller needs to have a label attached to it. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-07-30Merge branch 'for-3.6' of git://gitorious.org/linux-pwm/linux-pwmLinus Torvalds
Pull PWM subsystem from Thierry Reding: "The new PWM subsystem aims at collecting all implementations of the legacy PWM API and to eventually replace it completely. The subsystem has been in development for over half a year now and many drivers have already been converted. It has been in linux-next for a couple of weeks and there have been no major issues so I think it is ready for inclusion in your tree." Arnd Bergmann <arnd@arndb.de>: "Very much Ack on the new subsystem. It uses the interface declarations as the previously separate pwm drivers, so nothing changes for now in the drivers using it, although it enables us to change those more easily in the future if we want to. This work is also one of the missing pieces that are required to eventually build ARM kernels for multiple platforms, which is currently prohibited (amongs other things) by the fact that you cannot have more than one driver exporting the pwm functions." Tested-and-acked-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: Philip, Avinash <avinashphilip@ti.com> # TI's AM33xx platforms Acked-By: Alexandre Pereira da Silva <aletes.xgr@gmail.com> # LPC32XX Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Sachin Kamat <sachin.kamat@linaro.org> Fix up trivial conflicts with other cleanups and DT updates. * 'for-3.6' of git://gitorious.org/linux-pwm/linux-pwm: (36 commits) pwm: pwm-tiehrpwm: PWM driver support for EHRPWM pwm: pwm-tiecap: PWM driver support for ECAP APWM pwm: fix used-uninitialized warning in pwm_get() pwm: add lpc32xx PWM support pwm_backlight: pass correct brightness to callback pwm: Use pr_* functions in pwm-samsung.c file pwm: Convert pwm-samsung to use devm_* APIs pwm: Convert pwm-tegra to use devm_clk_get() pwm: pwm-mxs: Return proper error if pwmchip_remove() fails pwm: pwm-bfin: Return proper error if pwmchip_remove() fails pwm: pxa: Propagate pwmchip_remove() error pwm: Convert pwm-pxa to use devm_* APIs pwm: Convert pwm-vt8500 to use devm_* APIs pwm: Convert pwm-imx to use devm_* APIs pwm: Conflict with legacy PWM API pwm: pwm-mxs: add pinctrl support pwm: pwm-mxs: use devm_* managed functions pwm: pwm-mxs: use global reset function stmp_reset_block pwm: pwm-mxs: encode soc name in compatible string pwm: Take over maintainership of the PWM subsystem ...
2012-07-02pwm: tegra: Add device tree supportThierry Reding
Add auxdata to instantiate the PWFM controller from a device tree, include the corresponding nodes in the dtsi files for Tegra 20 and Tegra 30 and add binding documentation. Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
2012-06-20ARM: tegra: Fix dts files w/ status property: "disable" -> "disabled"Roland Stigge
This patches fixes some status = "disable" strings to "disabled", the correct way of disabling nodes in the devicetree. Just the tegra part here. Everything else goes via other patches and trees. Signed-off-by: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-11ARM: dt: tegra20: Rename "emc" to "memory-controller"hdoyu@nvidia.com
Use a more plain english name. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> [swarren: also rename the node in tegra-seaboard.dts] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-06-11ARM: dt: tegra{20,30}.dtsi: Rename "mc" to "memory-controller"hdoyu@nvidia.com
Use a more plain english name. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> [swarren: remove redundant unit address from tegra30.dtsi change] Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-14ARM: dt: tegra: invert status=disable vs status=okayStephen Warren
In tegra*.dtsi, set status="disable" for all HW modules that the board design may choose not to use. Update all boards to specifically enable any of those modules that are useful by setting status="okay". This makes board files say which features they do use, rather than which they don't, which feels more logical. It also makes the .dts files slightly smaller, at least for existing content. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-14ARM: dt: tegra: consistent basic property orderingStephen Warren
Put properties in order compatible, reg, interrupts, then anything else the node has. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-14ARM: dt: tegra: sort nodes based on bus orderStephen Warren
Sort the nodes according to the following rules: * First, any overrides for properties or nodes created by included files, in the order they appeared in the include file. * Second, any nodes with a reg property, in numerical order. * Third, any nodes without a reg property, in alphabetical order of node name. The second sorting rule at least will probably help if/when we need to explicitly insert nodes for the various busses in Tegra; that will just be an indentation change rather than also a node re-ordering. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-14ARM: dt: tegra: consistenly use lower-case for hex constantsStephen Warren
Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-14ARM: dt: tegra: format regs properties consistentlyStephen Warren
Place each reg "entry" on its own line, and wrap the whole list in <> rather than each individual entry. The convention chosen here is slightly arbitrary, but is not consistent throughout all Tegra files. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-14ARM: dt: tegra: remove unnecessary unit addressesStephen Warren
DT node names only need to include the unit address if it's required to make the node name unique. Remove the unnecessary unit addresses. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-14ARM: dt: tegra: whitespace cleanupStephen Warren
Consistently don't place a space after < or before >. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Olof Johansson <olof@lixom.net>
2012-05-14ARM: dt: tegra20.dtsi: Add GART nodehdoyu@nvidia.com
Add a node for the Tegra20 GART Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-14ARM: dt: tegra20.dtsi: Add Memory Controller(MC) nodeshdoyu@nvidia.com
Add Tegra MC(Memory Controller) nodes for tegra20.dtsi. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-05-14ARM: dt: tegra: Add device tree support for AHBHiroshi DOYU
Add AHB entry for tegra20/30. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-03-28Merge tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds
Pull "ARM: More device tree support updates" from Olof Johansson: "This branch contains a number of updates for device tree support on several ARM platforms, in particular: * AT91 continues the device tree conversion adding support for a number of on-chip drivers and other functionality * ux500 adds probing of some of the core SoC blocks through device tree * Initial device tree support for ST SPEAr600 platforms * kirkwood continues the conversion to device-tree probing" Manually merge arch/arm/mach-ux500/Kconfig due to MACH_U8500 rename, and drivers/usb/gadget/at91_udc.c due to header file include cleanups. Also do an "evil merge" for the MACH_U8500 config option rename that the affected RMI4 touchscreen driver in staging. It's called MACH_MOP500 now, and it was missed during previous merges. * tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits) ARM: SPEAr600: Add device-tree support to SPEAr600 boards ARM: ux500: Provide local timer support for Device Tree ARM: ux500: Enable PL022 SSP Controller in Device Tree ARM: ux500: Enable PL310 Level 2 Cache Controller in Device Tree ARM: ux500: Enable PL011 AMBA UART Controller for Device Tree ARM: ux500: Enable Cortex-A9 GIC (Generic Interrupt Controller) in Device Tree ARM: ux500: db8500: list most devices in the snowball device tree ARM: ux500: split dts file for snowball into generic part ARM: ux500: combine the board init functions for DT boot ARM: ux500: Initial Device Tree support for Snowball ARM: ux500: CONFIG: Enable Device Tree support for future endeavours ARM: kirkwood: use devicetree for rtc-mv ARM: kirkwood: rtc-mv devicetree bindings ARM: kirkwood: fdt: define uart[01] as disabled, enable uart0 ARM: kirkwood: fdt: facilitate new boards during fdt migration ARM: kirkwood: fdt: absorb kirkwood_init() ARM: kirkwood: fdt: use mrvl ticker symbol ARM: orion: wdt: use resource vice direct access ARM: Kirkwood: Remove tclk from kirkwood_asoc_platform_data. ARM: orion: spi: remove enable_clock_fix which is not used ...