linux-fsl-qoriq - Freescale linux tree with Scalys patches

Age	Commit message (Collapse)	Author
2010-02-04	davinci: clock: let clk->set_rate function sleep	Sekhar Nori
	When supporting I2C/SPI based on-board PLLs like CDCE949, it is essential that clk->set_rate be able to sleep. Currently, this is not possible because clk->set_rate is called from within spin-lock in clk_set_rate This patch brings clk->set_rate outside of the spin-lock and lets the individual set_rate implementations achieve serialization through appropiate means. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
2010-02-04	davinci: add support for CDCE949 clock synthesizer	Nageswari Srinivasan
	This patch adds support for TI's CDCE949 - a clock synthesizer with 4 PLLs and 9 outputs. It is used on DM6467 EVM. On the EVM, it generates clocks required for VPIF, TSIF and Audio modules. This patch adds it as part of the DaVinci clock framework. Testing: The various frequency outputs on Y1 have been tested using a out-of-tree VPIF video driver supporting HD video. The register values for Y5 frequency outputs have been derived from TSIF driver sources in MontaVista LSP kernel, but actual output has not been tested for lack of TSIF driver which actually works on the latest kernel. Signed-off-by: Nageswari Srinivasan <nageswari@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>