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2015-07-14arm: ls1021a: mask interrupts before entering deep sleepChenhui Zhao
Before entering deep sleep, interrupts should be masked. Or, unexpected interrupts may block the process of deep sleep. So, mask interrupts by the following steps: 1. Mask interrupts to RCPM 2. Disable the GIC This will make deep sleep more stable. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: I601062f8406324a308ef44491fed7cf479eaeba9 Reviewed-on: http://git.am.freescale.net:8181/39602 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-07-09arm: ls1021a: change the order of setting PMC interrupt registersChenhui Zhao
In deep sleep process, set interrupt status and polarity registers before enabling PMC interrupts. It is more stable, especially on ls1021a-twr board. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: I8305e25a76f0bcc636b58178495165c915ac3c1a Reviewed-on: http://git.am.freescale.net:8181/39478 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-06-04arm: ls1021a: enable sleep and deep sleep for rev 2.0 siliconChenhui Zhao
On the rev 2.0 silicon of LS1021A, set the WFIL2EN bit in the SCFG_CLUSTERPMCR register to enable sleep and deep sleep. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: I0ec6933dc1805749d7e4a815f9049301dfcfb63e Reviewed-on: http://git.am.freescale.net:8181/37396 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-05-25arm: ls1021a: add deep sleep support on TWR-LS1021A-PBChenhui Zhao
Add deep sleep support on TWR-LS1021A-PB, which has CPLD on board instead of FPGA. Enable the ftm0 node in .dts to enable wake-on-Flextimer feature. Change-Id: I0b1234cdd80d852140964240234576705764cd89 Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/36250 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-05-19arm: ls1021a: add platform notifier for dma-coherent requirementAlison Wang
This patch adds platform notifier for dma-coherent requirement. Structure arm_coherent_dma_ops is used instead of arm_dma_ops. Signed-off-by: Alison Wang <alison.wang@freescale.com> Change-Id: I55e755b5ead1cb50ff9ca2e6838588a04e5ea9e7 Reviewed-on: http://git.am.freescale.net:8181/36291 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Claudiu Manoil <claudiu.manoil@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-03-19Merge branch 'qoriq-sdk' into LS1-SDKJason Jin
2015-03-09arm: ls1021a: enable WoL by enabling error interrupts of eTSEC1Chenhui Zhao
In deep sleep case, when enabling Wake-on-LAN feature, receiving a magic packet will trigger an error interrupt on eTSEC1. Therefore, enable these interrupts in setting PMC interrupt registers for deep sleep. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: I3a2ca3e98e261d1c5c2f422203943959b871d7bd Reviewed-on: http://git.am.freescale.net:8181/32216 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yuantian Tang <yuantian.tang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-03-05arm: ls1021a: OCRAM1 does not power down in deep sleepChenhui Zhao
In the case of SD boot, system can't wake from deep sleep if OCRAM1 is powered down. Therefore, keep it on when doing deep sleep. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: Ib5f6b1c46f7c66e83595fc4fbe17789e557adee9 Reviewed-on: http://git.am.freescale.net:8181/31996 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yuantian Tang <yuantian.tang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-02-13Merge branch 'rtmerge'Scott Wood
Signed-off-by: Scott Wood <scottwood@freescale.com> Conflicts: arch/arm/kvm/mmu.c arch/arm/mm/proc-v7-3level.S arch/powerpc/kernel/vdso32/getcpu.S drivers/crypto/caam/error.c drivers/crypto/caam/sg_sw_sec4.h drivers/usb/host/ehci-fsl.c
2015-02-13Reset to 3.12.37Scott Wood
2015-02-10arm: ls1021a: utilizing hrtimer based broadcastJingchang Lu
This add utilization on hrtimer based broadcast instead the periodic tick broadcast to provide high resolution clock in SMP. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I391bf06fa4b238ab49bced26e3be8c2b6c677c32 Reviewed-on: http://git.am.freescale.net:8181/30436 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-02-05arm: ls1021a: no need to reset the registers after core resetChenhui Zhao
These registers has been reset in the bootloader after power-up. No need to reset them in kernel. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: I300f1763bafce3291c371b05d7bce3c363dc760b Reviewed-on: http://git.am.freescale.net:8181/29620 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-02-05arm: ls1021a: set wakeup devices dynamically for sleep/deep sleepChenhui Zhao
If a device works as a wakeup source, it will keep working in the peroid of sleep/deep sleep. This patch sets the wakeup devices according to the wakeup attribute of device. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: If49a8ad282115ac415fb03d0197964c5ae10c86d Reviewed-on: http://git.am.freescale.net:8181/29152 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2015-02-05arm: ls1: add error handling caseZhuoyu Zhang
* Add iomap() error handling case and initialize rcpm_base when system booting up. * Only fill secondary_pre_boot_entry with value of SCRATCHRW1 register when system boot up, do not need to fill it each time doing cpu-hotplug. Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> Change-Id: If672bd18074eea6db75c9273a7656aff983ffd9a Reviewed-on: http://git.am.freescale.net:8181/28866 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: ls1: only call ls1_pm_iomap() when doing deep sleepChenhui Zhao
ls1_pm_iomap() maps some register spaces for deep sleep, so do not call ls1_pm_iomap() when doing sleep. This patch also fixes a kernel BUG which happens when doing sleep on LS1021ATWR board. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: I1e06222f6ee2f6c44f763d48d959680838db0551 Reviewed-on: http://git.am.freescale.net:8181/25476 Reviewed-by: Yang Li <LeoLi@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
2014-12-11arm: ls1: make the workaround more stableChenhui Zhao
Increase the delay time to 15ms, which is more stable. The delay is added in the commit: commit cd20fed09d426bcc38348e8d1dd32ad828239170 Author: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com> Date: Wed Nov 19 15:49:53 2014 +0800 arm: ls1: provide a workaround for core soft reset Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: Ic7c57346bedab74d5161c36435373af7bc41fb48 Reviewed-on: http://git.am.freescale.net:8181/25423 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
2014-12-11arm: ls1: provide a workaround for core soft resetZhang Zhuoyu
Due to an erratum, after core soft reset, core state machine registers need to force release manually to avoid cache coherence issue. Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com> ---- Fix previous known issue http://git.am.freescale.net:8181/21918 Change-Id: I44a7cf8a315bafe7dc413f73d2af2579da246fbb Reviewed-on: http://git.am.freescale.net:8181/23520 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
2014-12-11arm: ls1: implement ls1 cpu-hotplug by reset coreZhang Zhuoyu
CPU hotplug should always reset core and boots up the same path as a cold boot to be compatible with kexec. Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com> ---- Fix previous known issue http://git.am.freescale.net:8181/21918 Patch Sent Upstream http://patchwork.ozlabs.org/patch/393683/ Change-Id: I668b59b4250ef62395a6fd8c22ea64f64af9d106 Reviewed-on: http://git.am.freescale.net:8181/23519 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yuantian Tang <yuantian.tang@freescale.com> Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
2014-12-11Merge remote-tracking branch 'ls1/LS1-SDK'Matthew Weigel
2014-12-11pm: ls1021: fix deep sleep issue when compiling kernel with THUMB2 instuctionChenhui Zhao
* set the bit 0 of the target address of long jump to 1 for THUMB mode * compile the resume entry code in arm instruction set Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: I01a96158ac39e14dcaebc7305b03eb277712011b Reviewed-on: http://git.am.freescale.net:8181/23209 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11deepsleep/qe: revert the patch 9d7acdbef272002ec11e1aaad4ad16155187a9d0Zhao Qiang
Remove the workaround which disables qe for deepsleep. qe blocked deepsleep, so the workaround was added, Now the qe can work with deepsleep, so remove it. Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I0f1ef2ec45b2ee8129c6ab958162f432d8a76c5d Reviewed-on: http://git.am.freescale.net:8181/23143 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
2014-12-11cpufreq: enable cpu frequency switch on ls102xTang Yuantian
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> --- upstream link of the patch: http://patchwork.ozlabs.org/patch/400406/ Change-Id: I55e42d2515bcd35d0bc5198cb13d5ed91850b50e Reviewed-on: http://git.am.freescale.net:8181/22796 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11pm: ls1: diable QE device to make deep sleep workChenhui Zhao
The temporary workaround will disable the QE device before entering deep sleep. It makes deep sleep work, and should be removed after resolving the problem. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Change-Id: Ib8c079ef67773eb3e058cf03331a0ed9c7707113 Reviewed-on: http://git.am.freescale.net:8181/21981 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: pm: add deep sleep support for LS1Chenhui Zhao
LS1 supports deep sleep feature that can switch off most parts of the SoC when it is in deep sleep state. The DDR controller will also be powered off in deep sleep. Therefore, copy the last stage code to enter deep sleep to SRAM and run it with disabling MMU and caches. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> --- Patch Sent Upstream url: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-October/296411.html Change-Id: If96ace364c21786cc88ea4979d7cbb4e177da0a2 Reviewed-on: http://git.am.freescale.net:8181/21920 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM:LS1021aQDS: add CPU hotplug platform supportZhang Zhuoyu
This is only a CPU pseudo-hotplug, and incompatible with kexec mechanics. As per the discussion with Russell King in opensource community, CPU hotplug should reset the secondary core to be compatible with kexec. "In the kexec case, when the secondary CPU wakeup, the code it is executing can already been overwritten, which then means that the CPU ends up executing some random code instead." For LS102x platforms, resetting core can be realized, but come across cache coherence problem which is still unresolved, we will submit another patch to implement CPU hotplug by resetting core once cache coherence issue resloved. Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com> --- Patch Sent Upstream url: https://lkml.org/lkml/2014/9/26/422 Change-Id: I36509f99299f874ef0df891a33c907a749649527 Reviewed-on: http://git.am.freescale.net:8181/21918 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Yang Li <LeoLi@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: ls1021a: add gating clocks to IP blocks.Xiubo Li
A given application may not use all the peripherals on the device. In this case, it may be desirable to disable unused peripherals. DCFG provides a mechanism for gating clocks to IP blocks that are not used when running an application. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> --- This patch has been sent out to the community and under discussion： URL：http://www.spinics.net/lists/arm-kernel/msg370133.html Change-Id: Iedf07d12955b3fa011a0bef27236f73405cefb44 Reviewed-on: http://git.am.freescale.net:8181/21604 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11Revert "arm: ls1021a: remove the FSL_SOC config added by SOC_LS1021A"Jingchang Lu
This reverts commit 14bbc976701a2ebc62343d3122e5ff772060a35f. LS1021A shares IPs with sophisticated PowerPC platform, many PowerPC drivers have depends on FSL_SOC defination, so to consistent with this, FSL_SOC is introduced. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: Ie5a69b78d317d09f9fee54dde3f1cd4bffdb9588 Reviewed-on: http://git.am.freescale.net:8181/19915 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: ls1021a: remove dma_zone_size definationJingchang Lu
CONFIG_ZONE_DMA is enough to claim the dma limitation, and no need for limitation smaller than 4GB, so remove the dma_zone_size defination. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- the upstream include this change in patchwork is: https://patchwork.kernel.org/patch/4946151/ Change-Id: Ia2ed1fd18519e1e2553e2aa8ce1c1729657a6ed3 Reviewed-on: http://git.am.freescale.net:8181/19874 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: ls1021a: remove the FSL_SOC config added by SOC_LS1021AJingchang Lu
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I2deac22e04a04c2523c7839d5974a41288e5bb2b Reviewed-on: http://git.am.freescale.net:8181/17837 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: imx: Add Freescale LS1021A SMP supportJingchang Lu
Freescale LS1021A SoC deploys two cortex-A7 processors, this adds bring-up support for the secondary core. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464481/
2014-12-11ARM: imx: Add initial support for Freescale LS1021AJingchang Lu
The LS1021A SoC is a dual-core Cortex-A7 based processor, this add the initial support for it. Signed-off-by: Jingchang Lu <b35083@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464451/
2013-12-04ARM: i.MX6q: fix the wrong parent of can_root clockJiada Wang
commit 9b3d423707c3b1f6633be1be7e959623e10c596b upstream. instead of pll3_usb_otg the parent of can_root clock should be pll3_60m. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Cc: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-09-20Merge tag 'pm+acpi-3.12-rc2' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm Pull ACPI and power management fixes from Rafael Wysocki: 1) Four fixes for cpufreq regressions introduced by the changes that removed Device Tree parsing for CPU device nodes from cpufreq drivers from Sudeep KarkadaNagesha. 2) Two fixes for recent cpufreq regressions introduced by changes related to the preservation of sysfs attributes over system suspend/resume cycles from Viresh Kumar. 3) Fix for ACPI-based wakeup signaling in the PCI subsystem that fails to stop PME polling for devices put into the D3cold power state from Rafael J Wysocki. 4) Fix for bad interactions between cpufreq and udev on systems supporting intel_pstate where acpi-cpufreq is available as well from Yinghai Lu. * tag 'pm+acpi-3.12-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: cpufreq: return EEXIST instead of EBUSY for second registering PCI / ACPI / PM: Clear pme_poll for devices in D3cold on wakeup ARM: shmobile: change dev_id to cpu0 while registering cpu clock ARM: i.MX: change dev_id to cpu0 while registering cpu clock cpufreq: imx6q-cpufreq: assign cpu_dev correctly to cpu0 device cpufreq: cpufreq-cpu0: assign cpu_dev correctly to cpu0 device cpufreq: unlock correct rwsem while updating policy->cpu cpufreq: Clear policy->cpus bits in __cpufreq_remove_dev_finish()
2013-09-19ARM: i.MX: change dev_id to cpu0 while registering cpu clockSudeep KarkadaNagesha
Currently all clkdev registration use "cpufreq-cpu0.0" as dev_id for cpu clock which refers to virtual platform device. It needs to be "cpu0" instead which is actual cpu0 device id. This patch changes the dev_id from "cpufreq-cpu0.0" to "cpu0". Reported-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-09-19cpufreq: imx6q-cpufreq: assign cpu_dev correctly to cpu0 deviceSudeep KarkadaNagesha
Commit cdc58d602d2e657602a90c190cbf745886c95977 "cpufreq: imx6q-cpufreq: remove device tree parsing for cpu nodes" assumed the pdev->dev is set to cpu0 device in the platform code. But it actually points to the virtual cpufreq-cpu0 platform device which is not present in the device tree. Most of the information needed by cpufreq is stored in cpu0 DT node. So cpu_dev must point to cpu0 device. This patch fixes the wrong assignment to cpu_dev. Reported-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-09-17ARM: imx: i.mx6d/q: disable the double linefill feature of PL310Jason Liu
The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 But according to ARM PL310 errata: 752271 ID: 752271: Double linefill feature can cause data corruption Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 Workaround: The only workaround to this erratum is to disable the double linefill feature. This is the default behavior. without this patch, you will meet the following error when run the memtester application at: http://pyropus.ca/software/memtester/ FAILURE: 0x00100000 != 0x00200000 at offset 0x01365664. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365668. FAILURE: 0x00100000 != 0x00200000 at offset 0x0136566c. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365670. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365674. FAILURE: 0x00100000 != 0x00200000 at offset 0x01365678. Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-09-17ARM: mach-imx: clk-imx51-imx53: Fix 'spdif1_pred' clock registrationFabio Estevam
Since commit beb2d1c1ba (ARM i.MX5: Add S/PDIF clocks), the following clock error appears on mx51: TrustZone Interrupt Controller (TZIC) initialized i.MX51 clk 180: register failed with -17 i.MX5 clk 180: register failed with -17 sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms CPU identified as i.MX51, silicon rev 3.0 ... Clock 180 corresponds to 'spdif1_podf' and this clock is getting registered twice. Fix it, by properly registering the 'spdif1_pred' clock, which should not reference 'spdif1_podf'. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-09-17ARM: imx: initialize clk_init_data.flags for clk-fixup-muxShawn Guo
The clk_init_data.flags of clk-fixup-mux is left there without initialization. It may hold some random data and cause clock framework interpret the clock in an unexpected way. At least on imx6sl, the following division by zero error with sched_clock is seen because of it. Division by zero in kernel. CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.11.0-rc3+ #19 Backtrace: [<80011af0>] (dump_backtrace+0x0/0x10c) from [<80011c90>] (show_stack+0x18/0x1c) r6:3b9aca00 r5:00000020 r4:00000000 r3:00000000 [<80011c78>] (show_stack+0x0/0x1c) from [<8055e02c>] (dump_stack+0x78/0x94) [<8055dfb4>] (dump_stack+0x0/0x94) from [<80011924>] (__div0+0x18/0x20) r4:00000000 r3:00000000 [<8001190c>] (__div0+0x0/0x20) from [<8026c408>] (Ldiv0_64+0x8/0x18) [<8006330c>] (clocks_calc_mult_shift+0x0/0xf8) from [<8072f604>] (setup_sched_clock+0x88/0x1f0) [<8072f57c>] (setup_sched_clock+0x0/0x1f0) from [<8071ad48>] (mxc_timer_init+0xe8/0x17c) [<8071ac60>] (mxc_timer_init+0x0/0x17c) from [<807290b0>] (imx6sl_clocks_init+0x1db8/0x1dc0) r8:807a9ca4 r7:00000000 r6:80777564 r5:8100c1f4 r4:c0820000 [<807272f8>] (imx6sl_clocks_init+0x0/0x1dc0) from [<807420ac>] (of_clk_init+0x40/0x6c) [<8074206c>] (of_clk_init+0x0/0x6c) from [<807290cc>] (imx6sl_timer_init+0x14/0x18) r5:807a8e80 r4:ffffffff [<807290b8>] (imx6sl_timer_init+0x0/0x18) from [<80716e1c>] (time_init+0x24/0x34) [<80716df8>] (time_init+0x0/0x34) from [<80713738>] (start_kernel+0x1b0/0x310) [<80713588>] (start_kernel+0x0/0x310) from [<80008074>] (0x80008074) r7:80770b08 r6:80754cd4 r5:8076c8c4 r4:10c53c7d sched_clock: 32 bits at 0 Hz, resolution 0ns, wraps every 0ms Fix the bug by initializing init.flags as zero. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-09-10Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds
Pull slave-dmaengine updates from Vinod Koul: "This pull brings: - Andy's DW driver updates - Guennadi's sh driver updates - Pl08x driver fixes from Tomasz & Alban - Improvements to mmp_pdma by Daniel - TI EDMA fixes by Joel - New drivers: - Hisilicon k3dma driver - Renesas rcar dma driver - New API for publishing slave driver capablities - Various fixes across the subsystem by Andy, Jingoo, Sachin etc..." * 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (94 commits) dma: edma: Remove limits on number of slots dma: edma: Leave linked to Null slot instead of DUMMY slot dma: edma: Find missed events and issue them ARM: edma: Add function to manually trigger an EDMA channel dma: edma: Write out and handle MAX_NR_SG at a given time dma: edma: Setup parameters to DMA MAX_NR_SG at a time dmaengine: pl330: use dma_set_max_seg_size to set the sg limit dmaengine: dma_slave_caps: remove sg entries dma: replace devm_request_and_ioremap by devm_ioremap_resource dma: ste_dma40: Fix potential null pointer dereference dma: ste_dma40: Remove duplicate const dma: imx-dma: Remove redundant NULL check dma: dmagengine: fix function names in comments dma: add driver for R-Car HPB-DMAC dma: k3dma: use devm_ioremap_resource() instead of devm_request_and_ioremap() dma: imx-sdma: Staticize sdma_driver_data structures pch_dma: Add MODULE_DEVICE_TABLE dmaengine: PL08x: Add cyclic transfer support dmaengine: PL08x: Fix reading the byte count in cctl dmaengine: PL08x: Add support for different maximum transfer size ...
2013-09-09Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linuxLinus Torvalds
Pull clock framework changes from Michael Turquette: "The common clk framework changes for 3.12 are dominated by clock driver patches, both new drivers and fixes to existing. A high percentage of these are for Samsung platforms like Exynos. Core framework fixes and some new features like automagical clock re-parenting round out the patches" * tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux: (102 commits) clk: only call get_parent if there is one clk: samsung: exynos5250: Simplify registration of PLL rate tables clk: samsung: exynos4: Register PLL rate tables for Exynos4x12 clk: samsung: exynos4: Register PLL rate tables for Exynos4210 clk: samsung: exynos4: Reorder registration of mout_vpllsrc clk: samsung: pll: Add support for rate configuration of PLL46xx clk: samsung: pll: Use new registration method for PLL46xx clk: samsung: pll: Add support for rate configuration of PLL45xx clk: samsung: pll: Use new registration method for PLL45xx clk: samsung: exynos4: Rename exynos4_plls to exynos4x12_plls clk: samsung: exynos4: Remove checks for DT node clk: samsung: exynos4: Remove unused static clkdev aliases clk: samsung: Modify _get_rate() helper to use __clk_lookup() clk: samsung: exynos4: Use separate aliases for cpufreq related clocks clocksource: samsung_pwm_timer: Get clock from device tree ARM: dts: exynos4: Specify PWM clocks in PWM node pwm: samsung: Update DT bindings documentation to cover clocks clk: Move symbol export to proper location clk: fix new_parent dereference before null check clk: wm831x: Initialise wm831x pointer on init ...
2013-09-06Merge tag 'soc-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Olof Johansson: "This branch contains mostly additions and changes to platform enablement and SoC-level drivers. Since there's sometimes a dependency on device-tree changes, there's also a fair amount of those in this branch. Pieces worth mentioning are: - Mbus driver for Marvell platforms, allowing kernel configuration and resource allocation of on-chip peripherals. - Enablement of the mbus infrastructure from Marvell PCI-e drivers. - Preparation of MSI support for Marvell platforms. - Addition of new PCI-e host controller driver for Tegra platforms - Some churn caused by sharing of macro names between i.MX 6Q and 6DL platforms in the device tree sources and header files. - Various suspend/PM updates for Tegra, including LP1 support. - Versatile Express support for MCPM, part of big little support. - Allwinner platform support for A20 and A31 SoCs (dual and quad Cortex-A7) - OMAP2+ support for DRA7, a new Cortex-A15-based SoC. The code that touches other architectures are patches moving MSI arch-specific functions over to weak symbols and removal of ARCH_SUPPORTS_MSI, acked by PCI maintainers" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (266 commits) tegra-cpuidle: provide stub when !CONFIG_CPU_IDLE PCI: tegra: replace devm_request_and_ioremap by devm_ioremap_resource ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort list ARM: dts: vf610-twr: enable i2c0 device ARM: dts: i.MX51: Add one more I2C2 pinmux entry ARM: dts: i.MX51: Move pins configuration under "iomuxc" label ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX ARM: dts: i.MX27: Disable AUDMUX in the template ARM: dts: wandboard: Add support for SDIO bcm4329 ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template ARM: dts: imx53-qsb: Make USBH1 functional ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module ARM: dts: imx6qdl-sabresd: Add touchscreen support ARM: imx: add ocram clock for imx53 ARM: dts: imx: ocram size is different between imx6q and imx6dl ARM: dts: imx27-phytec-phycore-som: Fix regulator settings ARM: dts: i.MX27: Remove clock name from CPU node ...
2013-09-06Merge tag 'cleanup-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Olof Johansson: "This branch contains code cleanups, moves and removals for 3.12. There's a large number of various cleanups, and a nice net removal of 13500 lines of code. Highlights worth mentioning are: - A series of patches from Stephen Boyd removing the ARM local timer API. - Move of Qualcomm MSM IOMMU code to drivers/iommu. - Samsung PWM driver cleanups from Tomasz Figa, removing legacy PWM driver and switching over to the drivers/pwm one. - Removal of some unusued auto-generated headers for OMAP2+ (PRM/CM). There's also a move of a header file out of include/linux/i2c/ to platform_data, where it really belongs. It touches mostly ARM platform code for include changes so we took it through our tree" * tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits) ARM: OMAP2+: Add back the define for AM33XX_RST_GLOBAL_WARM_SW_MASK gpio: (gpio-pca953x) move header to linux/platform_data/ arm: zynq: hotplug: Remove unreachable code ARM: SAMSUNG: Remove unnecessary exynos4_default_sdhci*() tegra: simplify use of devm_ioremap_resource ARM: SAMSUNG: Remove plat/regs-timer.h header ARM: SAMSUNG: Remove remaining uses of plat/regs-timer.h header ARM: SAMSUNG: Remove pwm-clock infrastructure ARM: SAMSUNG: Remove old PWM timer platform devices pwm: Remove superseded pwm-samsung-legacy driver ARM: SAMSUNG: Modify board files to use new PWM platform device ARM: SAMSUNG: Rework private data handling in dev-backlight pwm: Add new pwm-samsung driver ARM: mach-mvebu: remove redundant DT parsing and validation ARM: msm: Only compile io.c on platforms that use it iommu/msm: Move mach includes to iommu directory ARM: msm: Remove devices-iommu.c ARM: msm: Move mach/board.h contents to common.h ARM: msm: Migrate msm_timer to CLOCKSOURCE_OF_DECLARE ARM: msm: Remove TMR and TMR0 static mappings ...
2013-08-29gpio: (gpio-pca953x) move header to linux/platform_data/Vivien Didelot
This patch moves the pca953x.h header from include/linux/i2c to include/linux/platform_data and updates existing support accordingly. Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2013-08-26ARM: i.MX: remove sdma script address arrays from platform dataSascha Hauer
Now that the sdma driver holds the address tables for i.MX25/5 they are no longer needed in platform_data. Remove them. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2013-08-22ARM: imx: add ocram clock for imx53Shawn Guo
Add missing ocram gate clock for imx53 and also represent it in device tree ocram node. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: imx6q: remove board specific CLKO setupShawn Guo
The CLKO is widely used by imx6q board designs to clock audio codec. Since most codecs accept 24 MHz frequency, let's initially set up CLKO with OSC24M (cko <-- cko2 <-- osc). Then those board specific CLKO setup for audio codec can be removed. The board dts files also need an update on cko reference in codec node. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22phy: micrel: Add definitions for common Micrel PHY registersDinh Nguyen
Add defines for common Micrel PHY setups so that other platforms can use them. Update imx61 and sama5 hardware to use the micrel_phy.h PHY defines. Also add support for the KSZ9021RLRN PHY. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: David S. Miller <davem@davemloft.net> CC: Andrew Victor <linux@maxim.org.za> CC: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com> Cc: netdev@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: imx: Move anatop related from board file to anatop driverPeter Chen
Move anatop related (For USB) from board file to anatop driver Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: mx53: Allow suspend/resumeFabio Estevam
Current imx53_pm_init() implementation is incomplete as it lacks calling suspend_set_ops(). Use a single imx5_pm_init() function to handle both mx51 and mx53. This allows mx53 to enter in low-power mode. Tested on a mx53qsb: root@freescale /$ echo mem > /sys/power/state PM: Syncing filesystems ... done. mmc0: card e624 removed Freezing user space processes ... (elapsed 0.001 seconds) done. Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. Suspending console(s) (use no_console_suspend to debug) ... (Press Power button) PM: suspend of devices complete after 17.067 msecs PM: suspend devices took 0.020 seconds PM: late suspend of devices complete after 0.954 msecs PM: noirq suspend of devices complete after 1.288 msecs Disabling non-boot CPUs ... PM: noirq resume of devices complete after 0.680 msecs PM: early resume of devices complete after 0.914 msecs PM: resume of devices complete after 44.955 msecs PM: resume devices took 0.050 seconds Restarting tasks ... done. mmc0: host does not support reading read-only switch. assuming write-enable. mmc0: new SDHC card at address e624 mmcblk0: mmc0:e624 SU04G 3.69 GiB mmcblk0: p1 p2 p3 libphy: 63fec000.etherne:00 - Link is Down libphy: 63fec000.etherne:00 - Link is Up - 100/Full root@freescale /$ Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2013-08-22ARM: mach-imx: Select ARM_CPU_SUSPEND at ARCH_MXC levelFabio Estevam
Instead of selecting ARM_CPU_SUSPEND only for mx6, we can select it for all SoCs from the ARCH_MXC family. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
generated by cgit v0.10.2 at 2024-09-28 11:33:51 (GMT)