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Fix the sh73a0 external IRQ pin code to properly support
CONFIG_SPARSE_IRQ=y by allocating IRQ descriptors for the
cascaded IRQs associated with external IRQ pins.
Without this fix it is impossible to request IRQ0->IRQ31
on the Kota2 board when sparse IRQs are enabled.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Support PINT on sh73a0 and AG5EVM using INTC PINT macros.
With this patch applied the AG5EVM ethernet is handled
through one of the chained sh73a0 PINT interrupt controllers.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Improve IRQ triggering support by making use of the macro
INTC_IRQ_PINS_32() for INTCA on sh73a0. Unfortunately it
is not as easy as just using the macro as-is, we need to
do mask and unmaks in the GIC but configure other bits
and ack in INTCA. Update GPIO IRQ mappings while at it.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Initialize ->irq_set_wake() in gic_arch_extn to unbreak wake
up from the KEYSC device on AG5EVM in case of Suspend-to-RAM.
Without this patch "echo mem > /sys/power/state" and a key
press results in the following message on resume:
WARNING: at kernel/irq/manage.c:507 irq_set_irq_wake+0x7c/0xd8()
Unbalanced IRQ 103 wake disable
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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The latest rmobile-latest doesn't run on ag5evm because of a
small mistake on initialization.
Though, I don't have any idea to write them smart.
anyway,
On sh73a0, GIC cpu_base is 0xf0000100 but 0xf0001000.
Signed-off-by: Takashi YOSHII <takashi.yoshii.zj@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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This fixes up the SMP support to use the refactored GIC APIs.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Add INTCS support for the sh73a0 processor.
The interrupts on the sh73a0 processor are managed
through controllers such as GIC, INTCS and INTCA.
The ARM cores use the GIC as primary interrupt
controller and the INTCS and INTCA are hanging off
the GIC as cascaded interrupt controllers.
Peripherals connected both to the GIC and the INTC
controllers should if possible only use the GIC.
If no GIC connection is available then INTCS and
INTCA may be used instead.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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