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path: root/arch/mips/include/asm/mmu_context.h
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2013-05-16Revert "MIPS: Allow ASID size to be determined at boot time."David Daney
This reverts commit d532f3d26716a39dfd4b88d687bd344fbe77e390. The original commit has several problems: 1) Doesn't work with 64-bit kernels. 2) Calls TLBMISS_HANDLER_SETUP() before the code is generated. 3) Calls TLBMISS_HANDLER_SETUP() twice in per_cpu_trap_init() when only one call is needed. [ralf@linux-mips.org: Also revert the bits of the ASID patch which were hidden in the KVM merge.] Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: "Steven J. Hill" <Steven.Hill@imgtec.com> Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/5242/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-09Merge branch 'mti-next' of ↵Ralf Baechle
git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next
2013-05-09Merge branch 'next/kvm' into mips-for-linux-nextRalf Baechle
2013-05-08MIPS: Allow ASID size to be determined at boot time.Steven J. Hill
Original patch by Ralf Baechle and removed by Harold Koerfgen with commit f67e4ffc79905482c3b9b8c8dd65197bac7eb508. This allows for more generic kernels since the size of the ASID and corresponding masks can be determined at run-time. This patch is also required for the new Aptiv cores and has been tested on Malta and Malta Aptiv platforms. [ralf@linux-mips.org: Added relevant part of fix https://patchwork.linux-mips.org/patch/5213/] Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-08MIPS: If KVM is enabled then use the KVM specific routine to flush the TLBs ↵Sanjay Lal
on a ASID wrap. Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> Cc: kvm@vger.kernel.org Cc: linux-mips@linux-mips.org Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-05-07Merge branch 'mips-next-3.10' of ↵Ralf Baechle
git://git.linux-mips.org/pub/scm/john/linux-john into mips-for-linux-next
2013-05-07MIPS: Init new mmu_context for each possible CPU to avoid memory corruptionHuacai Chen
Currently, init_new_context() only for each online CPU, this may cause memory corruption when CPU hotplug and fork() happens at the same time. To avoid this, we make init_new_context() cover each possible CPU. Scenario: 1, CPU#1 is being offline; 2, On CPU#0, do_fork() call dup_mm() and copy a mm_struct to the child; 3, On CPU#0, dup_mm() call init_new_context(), since CPU#1 is offline and init_new_context() only covers the online CPUs, child has the same asid as its parent on CPU#1 (however, child's asid should be 0); 4, CPU#1 is being online; 5, Now, if both parent and child run on CPU#1, memory corruption (e.g. segfault, bus error, etc.) will occur. Signed-off-by: Huacai Chen <chenhc@lemote.com> Acked-by: David Daney <david.daney@cavium.com> Patchwork: http://patchwork.linux-mips.org/patch/4995/ Acked-by: John Crispin <blogic@openwrt.org>
2013-04-11MIPS: Make declarations and definitions of tlbmiss_handler_setup_pgd match.Ralf Baechle
tlbmiss_handler_setup_pgd is run-time generated code and it was convenient to pretend the symbol was an array in the generator but a function for the users. LTO gcc won't tolerate this kind of lie anymore so solve the problem through a cast and function pointer instead. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-01MIPS: Whitespace cleanup.Ralf Baechle
Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-12-13MIPS: PMC-Sierra Yosemite: Remove support.Ralf Baechle
Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-04-27MIPS: Remove get_current_pgd().David Daney
It is unused in the tree. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3557/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2011-01-18MIPS: Use C0_KScratch (if present) to hold PGD pointer.David Daney
Decide at runtime to use either Context or KScratch to hold the PGD pointer. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/1876/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2010-04-12MIPS: Preliminary VDSODavid Daney
This is a preliminary patch to add a vdso to all user processes. Still missing are ELF headers and .eh_frame information. But it is enough to allow us to move signal trampolines off of the stack. Note that emulation of branch delay slots in the FPU emulator still requires the stack. We allocate a single page (the vdso) and write all possible signal trampolines into it. The stack is moved down by one page and the vdso is mapped into this space. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/975/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-12-17MIPS: Put PGD in C0_CONTEXT for 64-bit R2 processors.David Daney
Processors that support the mips64r2 ISA can in four instructions convert a shifted PGD pointer stored in the upper bits of c0_context into a usable pointer. By doing this we save a memory load and associated potential cache miss in the TLB exception handlers. Since the upper bits of c0_context were holding the CPU number, we move this to the upper bits of c0_xcontext which doesn't have enough bits to hold the PGD pointer, but has plenty for the CPU number. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Avoid potential hazard on Context registerRalf Baechle
set_saved_sp reads Context register. Avoid reading stale value from earlier incomplete write. Issue found and fixed for head.S by Chris Dearman <chris@mips.com>. Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-11-02MIPS: Don't write ones to reserved entryhi bits.Ralf Baechle
We've silently been relying on the hardware chopping off excess, reserved ASID bits for no better reason that it saving an instruction. Because we already have: #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) in <asm/mmu_context.h>. We can use a cleanup to avoid writing non-zero bits into the reserved entryhi bits. This avoid triggering some debugging assertion in the Cavium simulator. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-24cpumask: use mm_cpumask() wrapper: mipsRusty Russell
Makes code futureproof against the impending change to mm->cpu_vm_mask. It's also a chance to use the new cpumask_ ops which take a pointer (the older ones are deprecated, but there's no hurry for arch code). Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
2009-06-24MIPS: Build fix - include <linux/smp.h> into all smp_processor_id() users.Ralf Baechle
Some of the were relying into smp.h being dragged in by another header which of course is fragile. <asm/cpu-info.h> uses smp_processor_id() only in macros and including smp.h there leads to an include loop, so don't change cpu-info.h. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-11MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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