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2013-10-24of/irq: Use irq_of_parse_and_map()Thierry Reding
Replace some instances of of_irq_map_one()/irq_create_of_mapping() and of_irq_to_resource() by the simpler equivalent irq_of_parse_and_map(). Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Rob Herring <rob.herring@calxeda.com> [grant.likely: resolved conflicts with core code renames] Signed-off-by: Grant Likely <grant.likely@linaro.org>
2013-10-24of/irq: Replace of_irq with of_phandle_argsGrant Likely
struct of_irq and struct of_phandle_args are exactly the same structure. This patch makes the kernel use of_phandle_args everywhere. This in itself isn't a big deal, but it makes some follow-on patches simpler. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-10-24of/irq: Rename of_irq_map_* functions to of_irq_parse_*Grant Likely
The OF irq handling code has been overloading the term 'map' to refer to both parsing the data in the device tree and mapping it to the internal linux irq system. This is probably because the device tree does have the concept of an 'interrupt-map' function for translating interrupt references from one node to another, but 'map' is still confusing when the primary purpose of some of the functions are to parse the DT data. This patch renames all the of_irq_map_* functions to of_irq_parse_* which makes it clear that there is a difference between the parsing phase and the mapping phase. Kernel code can make use of just the parsing or just the mapping support as needed by the subsystem. The patch was generated mechanically with a handful of sed commands. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Michal Simek <monstr@monstr.eu> Acked-by: Tony Lindgren <tony@atomide.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-10-11powerpc/scom: Use "devspec" rather than "path" in debugfs entriesBenjamin Herrenschmidt
This is the traditional name for device-tree path, used in sysfs, do the same for the XSCOM debugfs files. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-10-11powerpc/scom: CONFIG_SCOM_DEBUGFS should depend on CONFIG_DEBUG_FSBenjamin Herrenschmidt
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-10-11powerpc/scom: Create debugfs files using ibm,chip-id if availableBenjamin Herrenschmidt
When creating the debugfs scom files, use "ibm,chip-id" as the scom%d index rather than a simple made up number when possible. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-10-11powerpc/scom: Add support for "reg" propertyBenjamin Herrenschmidt
When devices are direct children of a scom controller node, they should be able to use the normal "reg" property instead of "scom-reg". In that case, they also use #address-cells rather than #scom-cells to indicate the size of an entry. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-10-11powerpc/scom: Change scom_read() and scom_write() to return errorsBenjamin Herrenschmidt
scom_read() now returns the read value via a pointer argument and both functions return an int error code Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-10-11powerpc/mpic: Disable preemption when calling mpic_processor_id()Scott Wood
Otherwise, we get a debug traceback due to the use of smp_processor_id() (or get_paca()) inside hard_smp_processor_id(). mpic_host_map() is just looking for a default CPU, so it doesn't matter if we migrate after getting the CPU ID. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-10-11powerpc/powernv: Fix endian issues in OPAL ICS backendBenjamin Herrenschmidt
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-10-10powerpc: add explicit OF includesRob Herring
When removing prom.h include by of.h, several OF headers will no longer be implicitly included. Add explicit includes of of_*.h as needed. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Grant Likely <grant.likely@linaro.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Anatolij Gustschin <agust@denx.de> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Olof Johansson <olof@lixom.net> Cc: linuxppc-dev@lists.ozlabs.org
2013-09-30powerpc/fsl-pci: Use the quirk function of fsl_pci.c instead of quirk ↵Chunhe Lan
function of quirks.c In the fsl_pci.c, it has the quirk function: DECLARE_PCI_FIXUP_HEADER and quirk_fsl_pcie_header. But for fixing the following notice information: pci 0000:00:00.0: ignoring class 0x0b2000 (doesn't match header type 01) We use the DECLARE_PCI_FIXUP_EARLY and quirk_fsl_pcie_early instead of DECLARE_PCI_FIXUP_HEADER and quirk_fsl_pcie_header. This patch reverts commit 586c2c9eb2bc5da79d8e093b2b7dd98b5050e094: Remove the DECLARE_PCI_FIXUP_EARLY and quirk_freescale_class function in the quirks.c, because they have the same function as DECLARE_PCI_FIXUP_EARLY and quirk_fsl_pcie_early function in the fsl_pci.c. At the same time, in the fsl_pci.c quirk_fsl_pcie_early function can handle both of the RC devices and EP devices. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Change-Id: Iee569a14eeedd9a09d4511494a59d07b03f63f95 Reviewed-on: http://git.am.freescale.net:8181/4898 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zang Tiefei-R61911 <tie-fei.zang@freescale.com> Reviewed-by: Rivera Jose-B46482 <German.Rivera@freescale.com>
2013-09-23powerpc/pci: Use pci_is_pcie() to simplify codeYijing Wang
Use pci_is_pcie() to simplify code. Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Reviewed-by: Gavin Shan <shangw@linux.vnet.ibm.com> Cc: Gavin Shan <shangw@linux.vnet.ibm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org>
2013-09-12Merge tag 'iommu-updates-v3.12' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu Pull IOMMU Updates from Joerg Roedel: "This round the updates contain: - A new driver for the Freescale PAMU IOMMU from Varun Sethi. This driver has cooked for a while and required changes to the IOMMU-API and infrastructure that were already merged before. - Updates for the ARM-SMMU driver from Will Deacon - Various fixes, the most important one is probably a fix from Alex Williamson for a memory leak in the VT-d page-table freeing code In summary not all that much. The biggest part in the diffstat is the new PAMU driver" * tag 'iommu-updates-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: intel-iommu: Fix leaks in pagetable freeing iommu/amd: Fix resource leak in iommu_init_device() iommu/amd: Clean up unnecessary MSI/MSI-X capability find iommu/arm-smmu: Simplify VMID and ASID allocation iommu/arm-smmu: Don't use VMIDs for stage-1 translations iommu/arm-smmu: Tighten up global fault reporting iommu/arm-smmu: Remove broken big-endian check iommu/fsl: Remove unnecessary 'fsl-pamu' prefixes iommu/fsl: Fix whitespace problems noticed by git-am iommu/fsl: Freescale PAMU driver and iommu implementation. iommu/fsl: Add additional iommu attributes required by the PAMU driver. powerpc: Add iommu domain pointer to device archdata iommu/exynos: Remove dead code (set_prefbuf)
2013-09-06Merge branch 'next' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc Pull powerpc updates from Ben Herrenschmidt: "Here's the powerpc batch for this merge window. Some of the highlights are: - A bunch of endian fixes ! We don't have full LE support yet in that release but this contains a lot of fixes all over arch/powerpc to use the proper accessors, call the firmware with the right endian mode, etc... - A few updates to our "powernv" platform (non-virtualized, the one to run KVM on), among other, support for bridging the P8 LPC bus for UARTs, support and some EEH fixes. - Some mpc51xx clock API cleanups in preparation for a clock API overhaul - A pile of cleanups of our old math emulation code, including better support for using it to emulate optional FP instructions on embedded chips that otherwise have a HW FPU. - Some infrastructure in selftest, for powerpc now, but could be generalized, initially used by some tests for our perf instruction counting code. - A pile of fixes for hotplug on pseries (that was seriously bitrotting) - The usual slew of freescale embedded updates, new boards, 64-bit hiberation support, e6500 core PMU support, etc..." * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (146 commits) powerpc: Correct FSCR bit definitions powerpc/xmon: Fix printing of set of CPUs in xmon powerpc/pseries: Move lparcfg.c to platforms/pseries powerpc/powernv: Return secondary CPUs to firmware on kexec powerpc/btext: Fix CONFIG_PPC_EARLY_DEBUG_BOOTX on ppc32 powerpc: Cleanup handling of the DSCR bit in the FSCR register powerpc/pseries: Child nodes are not detached by dlpar_detach_node powerpc/pseries: Add mising of_node_put in delete_dt_node powerpc/pseries: Make dlpar_configure_connector parent node aware powerpc/pseries: Do all node initialization in dlpar_parse_cc_node powerpc/pseries: Fix parsing of initial node path in update_dt_node powerpc/pseries: Pack update_props_workarea to map correctly to rtas buffer header powerpc/pseries: Fix over writing of rtas return code in update_dt_node powerpc/pseries: Fix creation of loop in device node property list powerpc: Skip emulating & leave interrupts off for kernel program checks powerpc: Add more exception trampolines for hypervisor exceptions powerpc: Fix location and rename exception trampolines powerpc: Add more trap names to xmon powerpc/pseries: Add a warning in the case of cross-cpu VPA registration powerpc: Update the 00-Index in Documentation/powerpc ...
2013-08-14iommu/fsl: Freescale PAMU driver and iommu implementation.Varun Sethi
Following is a brief description of the PAMU hardware: PAMU determines what action to take and whether to authorize the action on the basis of the memory address, a Logical IO Device Number (LIODN), and PAACT table (logically) indexed by LIODN and address. Hardware devices which need to access memory must provide an LIODN in addition to the memory address. Peripheral Access Authorization and Control Tables (PAACTs) are the primary data structures used by PAMU. A PAACT is a table of peripheral access authorization and control entries (PAACE).Each PAACE defines the range of I/O bus address space that is accessible by the LIOD and the associated access capabilities. There are two types of PAACTs: primary PAACT (PPAACT) and secondary PAACT (SPAACT).A given physical I/O device may be able to act as one or more independent logical I/O devices (LIODs). Each such logical I/O device is assigned an identifier called logical I/O device number (LIODN). A LIODN is allocated a contiguous portion of the I/O bus address space called the DSA window for performing DSA operations. The DSA window may optionally be divided into multiple sub-windows, each of which may be used to map to a region in system storage space. The first sub-window is referred to as the primary sub-window and the remaining are called secondary sub-windows. This patch provides the PAMU driver (fsl_pamu.c) and the corresponding IOMMU API implementation (fsl_pamu_domain.c). The PAMU hardware driver (fsl_pamu.c) has been derived from the work done by Ashish Kalra and Timur Tabi. [For iommu group support] Acked-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Timur Tabi <timur@tabi.org> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
2013-08-14powerpc: Fix some endian issues in xics codeAnton Blanchard
Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-08-14powerpc: Add some endian annotations to time and xics codeAnton Blanchard
Fix a couple of sparse warnings. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-08-07powerpc/pci: fix PCI-e check link issueYuanquan Chen
For Freescale powerpc platform, the PCI-e bus number uses the reassign mode by default. It means the second PCI-e controller's hose->first_busno is the first controller's last bus number adding 1. For some hotpluged device(or controlled by FPGA), the device is linked to PCI-e slot at linux runtime. It needs rescan for the system to add it and driver it to work. It successes to rescan the device linked to the first PCI-e controller's slot, but fails to rescan the device linked to the second PCI-e controller's slot. The cause is that the bus->number is reset to 0, which isn't equal to the hose->first_busno for the second controller checking PCI-e link. So it doesn't really check the PCI-e link status, the link status is always no_link. The device won't be really rescaned. Reset the bus->number to hose->first_busno in the function fsl_pcie_check_link(), it will do the real checking PCI-e link status for the second controller, the device will be rescaned. Signed-off-by: Yuanquan Chen <Yuanquan.Chen@freescale.com> Tested-by: Rojhalat Ibrahim <imr@rtschenk.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-08-07powerpc/fsl-pci: enable SWIOTLB in function setup_pci_atmuKevin Hao
This function contains all the stuff we need to check if SWIOTLB should be enabled or not. So it is more convenient to enable the SWIOTLB here than later. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-08-07powerpc/fsl-pci: fix the unreachable warning messageKevin Hao
The (1ull << mem_log) is never greater than mem unless mem_log++; Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-08-07powerpc/fsl_msi: add MSIIR1 support for MPIC v4.3Minghuan Lian
The original MPIC MSI bank contains 8 registers, MPIC v4.3 MSI bank contains 16 registers, and this patch adds NR_MSI_REG_MAX and NR_MSI_IRQS_MAX to describe the maximum capability of MSI bank. MPIC v4.3 provides MSIIR1 to index these 16 MSI registers. MSIIR1 uses different bits definition than MSIIR. This patch adds ibs_shift and srs_shift to indicate the bits definition of the MSIIR and MSIIR1, so the same code can handle the MSIIR and MSIIR1 simultaneously. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> [scottwood@freescale.com: reinstated static on all_avail] Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-07-30powerpc/fsl_msi: fix error return code in fsl_of_msi_probe()Wei Yongjun
Fix to return a negative error code in the MSI bitmap alloc error handling case instead of 0, as done elsewhere in this function. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-07-30powerpc/85xx: Add machine check handler to fix PCIe erratum on mpc85xxHongtao Jia
A PCIe erratum of mpc85xx may causes a core hang when a link of PCIe goes down. when the link goes down, Non-posted transactions issued via the ATMU requiring completion result in an instruction stall. At the same time a machine-check exception is generated to the core to allow further processing by the handler. We implements the handler which skips the instruction caused the stall. This patch depends on patch: powerpc/85xx: Add platform_device declaration to fsl_pci.h Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Liu Shuo <soniccat.liu@gmail.com> Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-07-23rio: Make svr non-staticAndy Fleming
Being static made it fail to build Change-Id: I0d33f585fe92e63494ec3c78aae89629e0cab35c Signed-off-by: Andy Fleming <afleming@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/3483 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-07-22Update mpc85xx soc models listHaijun Zhang
Remove some useless functions. Add some new soc list. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Change-Id: I664c1f0b9fc0544ec1fed7304bae2fc562266676 Reviewed-on: http://git.am.freescale.net:8181/2316 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-07-15PTR_RET is now PTR_ERR_OR_ZERO(): Replace most.Rusty Russell
Sweep of the simple cases. Cc: netdev@vger.kernel.org Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-arm-kernel@lists.infradead.org Cc: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Acked-by: David S. Miller <davem@davemloft.net> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-07-02Merge remote-tracking branch 'scott/next' into nextBenjamin Herrenschmidt
Merge Freescale updates
2013-07-01powerpc/fsl: add MPIC timer wakeup supportDongsheng.wang@freescale.com
The driver provides a way to wake up the system by the MPIC timer. For example, echo 5 > /sys/devices/system/mpic/timer_wakeup echo standby > /sys/power/state After 5 seconds the MPIC timer will generate an interrupt to wake up the system. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com>
2013-07-01powerpc/mpic: create mpic subsystem objectDongsheng.wang@freescale.com
Register a mpic subsystem at /sys/devices/system/ Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-07-01powerpc/mpic: add global timer supportDongsheng.wang@freescale.com
The MPIC global timer is a hardware timer inside the Freescale PIC complying with OpenPIC standard. When the specified interval times out, the hardware timer generates an interrupt. The driver currently is only tested on fsl chip, but it can potentially support other global timers complying to OpenPIC standard. The two independent groups of global timer on fsl chip, group A and group B, are identical in their functionality, except that they appear at different locations within the PIC register map. The hardware timer can be cascaded to create timers larger than the default 31-bit global timers. Timer cascade fields allow configuration of up to two 63-bit timers. But These two groups of timers cannot be cascaded together. It can be used as a wakeup source for low power modes. It also could be used as periodical timer for protocols, drivers and etc. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-07-01powerpc/mpic: add irq_set_wake supportDongsheng.wang@freescale.com
Add irq_set_wake support. Just add IRQF_NO_SUSPEND to desc->action->flag. So the wake up interrupt will not be disable in suspend_device_irqs. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-07-01powerpc/mpic: Add get_version API both for internal and external useHongtao Jia
MPIC version is useful information for both mpic_alloc() and mpic_init(). The patch provide an API to get MPIC version for reusing the code. Also, some other IP block may need MPIC version for their own use. The API for external use is also provided. Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-07-01Merge tag 'v3.10' into nextBenjamin Herrenschmidt
Merge 3.10 in order to get some of the last minute powerpc changes, resolve conflicts and add additional fixes on top of them.
2013-06-24powerpc/pci: Fix boot panic on mpc83xx (regression)Rojhalat Ibrahim
The following commit caused a fatal oops when booting on mpc83xx with a non-express PCI bus (regardless of whether a PCI device is present): commit 50d8f87d2b39313dae9d0a2d9b23d377328f2f7b Author: Rojhalat Ibrahim <imr@rtschenk.de> Date: Mon Apr 8 10:15:28 2013 +0200 powerpc/fsl-pci Make PCIe hotplug work with Freescale PCIe controllers Up to now the PCIe link status on Freescale PCIe controllers was only checked once at boot time. So hotplug did not work. With this patch the link status is checked on every config read. PCIe devices not present at boot time are found after doing 'echo 1 >/sys/bus/pci/rescan'. Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> This patch fixes the issue by calling setup_indirect_pci for all device types. fsl_indirect_read_config is now only used for booke/86xx PCIe controllers. Reported-by: Michael Guntsche <mike@it-loops.com> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Rojhalat Ibrahim <imr@rtschenk.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
2013-06-20powerpc: Mark low level irq handlers NO_THREADThomas Gleixner
These low level handlers cannot be threaded. Mark them NO_THREAD Reported-by: leroy christophe <christophe.leroy@c-s.fr> Tested-by: leroy christophe <christophe.leroy@c-s.fr> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-05-31powerpc/mpic: Fix irq distribution problem when MPIC_SINGLE_DEST_CPUchenhui zhao
For the mpic with a flag MPIC_SINGLE_DEST_CPU, only one bit should be set in interrupt destination registers. The code is applicable to 64-bit platforms as well as 32-bit. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-05-31powerpc/85xx: l2sram - Add compatible string for BSC9132 platformHarninder Rai
Signed-off-by: Harninder Rai <harninder.rai@freescale.com> Change-Id: Ia55010a7b82b67058e49677f2cac3030e3b3cdf1 Reviewed-on: http://git.am.freescale.net:8181/2814 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Burmi Naveen-B16502 <NaveenBurmi@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-26powerpc/fsl-msi: use a different locklcass for the cascade interruptSebastian Andrzej Siewior
lockdep thinks that it might deadlock because it grabs a lock of the same class while calling the generic_irq_handler(). This annotation will inform lockdep that it will not. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
2013-05-26powerpc: Mark low level irq handlers NO_THREADThomas Gleixner
These low level handlers cannot be threaded. Mark them NO_THREAD Reported-by: leroy christophe <christophe.leroy@c-s.fr> Tested-by: leroy christophe <christophe.leroy@c-s.fr> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-05-22powerpc/mpic: fix interrupts distribution problem on 64-bit platformsZhao Chenhui
For the mpic with a flag MPIC_SINGLE_DEST_CPU, only one bit should be set in interrupt destination registers. This change is applicable to 32-bit and 64-bit platforms. Change-Id: If573a1911eca4465f253f427fa141e42fdceabae Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/2504 Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-17powerpc/pci: fix PCI-e check link issueYuanquan Chen
For freescale powerpc platform, the PCI-e bus number uses the reassign mode by default. It means the second PCI-e controller's hose->first_busno is the first controller's last bus number adding 1. For some hotpluged device(or controlled by FPGA), the device is linked to PCI-e slot at linux runtime. It needs rescan for the system to add it and driver it to work. It successes to rescan the device linked to the first PCI-e controller's slot, but fails to rescan the device linked to the second PCI-e controller's slot. The cause is that the bus->number is reset to 0, which isn't equal to the hose->first_busno for the second controller checking PCI-e link. So it doesn't really check the PCI-e link status, the link status is always no_link. The device won't be really rescaned. Reset the bus->number to hose->first_busno in the function fsl_pcie_check_link(), it will do the real checking PCI-e link status for the second controller, the device will be rescaned. Signed-off-by: Yuanquan Chen <Yuanquan.Chen@freescale.com> Change-Id: I404ec37966f14980e7ae07d0bd9abaa3624ea33b Reviewed-on: http://git.am.freescale.net:8181/2098 Reviewed-by: Zang Tiefei-R61911 <tie-fei.zang@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-17powerpc/85xx: handle the eLBC error interrupt if it exist in dtsWang Dongsheng
On P3041, P1020, P1021, P1022, P1023 eLBC event interrupts are routed to Int9(P3041) & Int3(P102x) while ELBC error interrupts are routed to Int0, we need to call request_irq for each. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Change-Id: I0855f322c8c7d8e3ad94747aa212b37f38f5c161 Reviewed-on: http://git.am.freescale.net:8181/2466 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-14powerpc/85xx: Add PCIe controller support for bsc9132qdsHarninder Rai
1. Use machine_arch_initcall to hook mpc85xx_common_publish_devices This can ensure before pcibios_init() is called, pci controllers have been probed and added to the hose_list. 2. Add a workaround for errata A-005434 For the BSC9132, PEX_PEXIWARn[TRGT] for all windows defaults to 0xF, which is mapped to CCSRBAR. However, for other products, 0xF is mapped to the local memory. Therefore, for the BSC9132, any default PCI Express access to the local memory (DDR) will now access the CCSRBAR. This patch changes the mapping of targets of inbound windows PEX_PEXIWARn[TRGT] to the Local address space – 0x0 (from 0xF). Signed-off-by: Harninder Rai <harninder.rai@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: Iebb3d0e057d64d5b96263c130495e5d04caf7948 Reviewed-on: http://git.am.freescale.net:8181/2455 Reviewed-by: Zang Tiefei-R61911 <tie-fei.zang@freescale.com> Reviewed-by: Kushwaha Prabhakar-B32579 <prabhakar@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-14powerpc: Fix irq_set_affinity() return valuesAlexander Gordeev
Signed-off-by: Alexander Gordeev <agordeev@redhat.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-05-13powerpc/pm: fix the return value of .enter()Zhao Chenhui
Change-Id: If7505a718c9a76b26eb8ea80c82bb0f4d2742192 Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/2456 Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-10Put the qemu_e500_pci check under CONFIG_PPC_QEMU_E500 check.Varun Sethi
Check for qemu_e500_pci flag only if QEMU E500 platform has been enabled. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I7eacf87bccbd9442c76c851eb185f9b352b00905 Reviewed-on: http://git.am.freescale.net:8181/2439 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-07Check of qemu emulated PCI controller.Varun Sethi
While implementing direct device assignment for linux guest using identity mapped memory (1:1 guest to host physical mapping), we hit a case where guest end of memory is not a power of two and thus is not completely mapped by the PCI controller inbound window. For a similar condition if the PCI controller supports PCI express capability the fsl_pci driver allows for over commit of inbound memory window. In this patch we introduce a check to see if the PCI controller is a qemu emulated controller. If it's an emulated controller we allow the inbound memory over commit in the fsl_pci driver. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Change-Id: I6dd7e5fb960a2ec068dd4f01c51906a7a1dea1f7 Reviewed-on: http://git.am.freescale.net:8181/2357 Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-05-07powerpc: Add an in memory udbg consoleAlistair Popple
This patch adds a new udbg early debug console which utilises statically defined input and output buffers stored within the kernel BSS. It is primarily designed to assist with bring up of new hardware which may not have a working console but which has a method of reading/writing kernel memory. This version incorporates comments made by Ben H (thanks!). Changes from v1: - Add memory barriers. - Ensure updating of read/write positions is atomic. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2013-05-06powerpc/pci: Support per-aperture memory offsetBenjamin Herrenschmidt
The PCI core supports an offset per aperture nowadays but our arch code still has a single offset per host bridge representing the difference betwen CPU memory addresses and PCI MMIO addresses. This is a problem as new machines and hypervisor versions are coming out where the 64-bit windows will have a different offset (basically mapped 1:1) from the 32-bit windows. This fixes it by using separate offsets. In the long run, we probably want to get rid of that intermediary struct pci_controller and have those directly stored into the pci_host_bridge as they are parsed but this will be a more invasive change. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>