Age | Commit message (Collapse) | Author |
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Wrap the test for pagefault_disabled() into a helper, this allows us
to remove the need for current->pagefault_disabled on !-rt kernels.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/n/tip-3yy517m8zsi9fpsf14xfaqkw@git.kernel.org
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Necessary for decoupling pagefault disable from preempt count.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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This more or less reverts commit 6391f697d4892a6f233501beea553e13f7745a23.
Instead of adding an unneeded 'default', mark the variable to prevent
the false positive 'uninitialized var'. The other change (fixing the
printout) needs revert, too. We want to know WHICH critical irq failed,
not which level it had.
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Cc: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Cc: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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Patch a8b2280cbcd16b7935032c72fcc49dadcd2f263c will cause Magic packet
cannot wake up system so we need to revert this patch.
This reverts commit a8b2280cbcd16b7935032c72fcc49dadcd2f263c.
Change-Id: I57f24b544e40ae75f2c28ed8f589405032069ec1
Reviewed-on: http://git.am.freescale.net:8181/25703
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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Change-Id: Ib01669212bd4b4b7abf6eb5ede61247ecdf39cb7
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/25513
Reviewed-by: Zhenhua Luo <zhenhua.luo@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Igal Liberman <Igal.Liberman@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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Change-Id: I1ddb4cd74ca1f453fb9ca7e7ec75fce2bc58b1b0
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/25447
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Igal Liberman <Igal.Liberman@freescale.com>
Reviewed-by: Nir Erez <nir.erez@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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These were missed by commit 745ecda7aa7e "powerpc/fsl-soc: Disable CPC
sole-data mode if KVM enabled".
Signed-off-by: Scott Wood <scottwood@freescale.com>
Fixes: 745ecda7aa7e "powerpc/fsl-soc: Disable CPC sole-data mode if KVM enabled"
Change-Id: I0b00cfbdf9846ba52fa8c58411b5df8002d7c67e
Reviewed-on: http://git.am.freescale.net:8181/25338
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mihai Caraman <mihai.caraman@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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Set undocumented bit to disable CPC sole data mode, making it safe to
use the LRAT with KVM guests, which could otherwise hang the host
(under certain usage patterns) by accessing memory with the M bit
unset. The guest still needs to set the M bit to operate properly, but
this removes a DoS vector.
Only do so if CONFIG_KVM is enabled as supposedly disabling this
affects performance, though I wasn't able to detect a difference
in the workloads I ran.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Change-Id: I5e69f03150f93556f3548ed4f8b3df65cfe6d802
Reviewed-on: http://git.am.freescale.net:8181/24843
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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In CoreNet systems it is not allowed to mix M and non-M mappings to the
same memory, and coherent DMA accesses are considered to be M mappings
for this purpose. Ignoring this has been observed to cause hard
lockups in non-SMP kernels on e6500.
Furthermore, e6500 implements the LRAT (logical to real address table)
which allows KVM guests to control the WIMGE bits. This means that
KVM cannot force the M bit on the way it usually does, so the guest had
better set it itself.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Change-Id: I083bdc9dd7990d475b8ae48680a8e63012998e93
Reviewed-on: http://git.am.freescale.net:8181/24841
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mihai Caraman <mihai.caraman@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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C29xPCIe has NAND flash present on IFC CS1.
So update "ranges" field for NAND flash on CS1.
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Change-Id: Id3bcf527929b9caeda9a81a1712b030e364ed64c
Reviewed-on: http://git.am.freescale.net:8181/24113
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Commit 5957374238 "KVM: PPC: e500: Fix tlbilx_all emulation for HTW"
removed the clearing of MAS5 from inval_ea_on_host() while moving it
between files. As a result, KVM causes MAS5 to be set for guest
mappings even when normal host Linux code is running, which renders
host invalidations-by-page ineffective. This caused corruption in the
host.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Change-Id: I0401e85dcd6a50961ce4657110bfaf66d90c87d4
Reviewed-on: http://git.am.freescale.net:8181/24460
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Stuart Yoder <stuart.yoder@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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RTC interrupt uses IRQ11 on T2080QDS.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Change-Id: I5f4c3f89d007c48009ad3368a1f6ed5e31f4e464
Reviewed-on: http://git.am.freescale.net:8181/24195
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Core reset may cause issue if using the proxy mode of MPIC.
Use the mixed mode of MPIC if enabling CPU hotplug.
Change-Id: I0e6b9dbd2126f0fb0af917d25c948266417bb71f
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/24102
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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fsl_set_power_except() checks only for fman node. For
all other ips, it doesn't program rcpm register, and
goes to err handling code. Hence, a check for usb is
put so that fman code only runs for fman ip
Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Change-Id: Ia8b2280cbcd16b7935032c72fcc49dadcd2f263c
Reviewed-on: http://git.am.freescale.net:8181/23989
Reviewed-by: Nikhil Badola <nikhil.badola@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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Add asm/smp.h, and only compile the cluster related code
when CPU hotplug is enabled.
Change-Id: I264ff297ca1ee29bf8c477b09bce98eeb27140ee
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/23752
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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Default rx frame queue id should match with usdpaa xml policy
file. Policy file is used to set FMAN configuration.
Signed-off-by: Sandeep Singh <sandeep@freescale.com>
Change-Id: I696d604c0811a8aa0b1ccf4ca6a67a0384eb558d
Reviewed-on: http://git.am.freescale.net:8181/23859
Reviewed-by: Vakul Garg <vakul@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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When CPU SMT feature disabled on e6500, cluster can't enter PCL10.
This patch fix it.
Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com>
Change-Id: I362be661ceefd78e5d8b1d6f36331add4e9ef0af
Reviewed-on: http://git.am.freescale.net:8181/23341
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Hongtao Jia <hongtao.jia@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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If all cores of a cluster are disabled in u-boot, the cluster mask
we calculate through cpu dts node is unreliable, this patch use
hard cored threads number per cluster to fix it.
Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com>
Change-Id: I8c76b4c592bebdacf55dc6c9d50bd65ea0fce89f
Reviewed-on: http://git.am.freescale.net:8181/23340
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yuantian Tang <yuantian.tang@freescale.com>
Reviewed-by: Hongtao Jia <hongtao.jia@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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In order to use the SPI nor framework to detect NOR flash.
Signed-off-by: Mingkai.Hu <Mingkai.Hu@freescale.com>
Change-Id: I5f7b42316cefb618278d739c212bd7cbd4833e9c
Reviewed-on: http://git.am.freescale.net:8181/23450
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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- enable CONFIG_RTC_DRV_DS1307 to support DS1339 RTC for T1024RDB.
- enable CONFIG_I2C_MUX and CONFIG_I2C_MUX_PCA954x for T102x/T104x QDS/RDB.
- enable CONFIG_MTD_SPI_NOR_BASE and update compatible to "micron,n25q512ax3"
for SPI flash on T102xRDB and T104xRDB.
- fix typo for CONFIG_SENSORS_LM90.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Change-Id: I3506779d51192d2bfaa28a3f863c019b612b6f96
Reviewed-on: http://git.am.freescale.net:8181/23525
Reviewed-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
Change-Id: I2f9c391df5ddca31a49a0a3ac0cba380722b7cf0
Reviewed-on: http://git.am.freescale.net:8181/23440
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
Change-Id: Ifc1ab666fe1ad16c4f01cbf74b088d8df4663e49
Reviewed-on: http://git.am.freescale.net:8181/23439
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yuantian Tang <yuantian.tang@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Change-Id: I5c7000288297384a04f33906e668f520bafc00d8
Reviewed-on: http://git.am.freescale.net:8181/23308
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com>
Reviewed-by: Roy Pledge <roy.pledge@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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- add CONFIG_FMAN_V3L by default for FMan_V3L platform.
- t1024 officially supports 6 portals of QMan/BMan instead of 10
- remove CONFIG_ALTIVEC as e5500 core has no ALTIVEC.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Change-Id: I71a5426ad441ef034c66e2d794a86b366092530d
Reviewed-on: http://git.am.freescale.net:8181/23188
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Kernel could not get cluster information from device tree on PowerPC.
The previous way of cluster calculation could be wrong if all cores of
some clusters are disabled. For now PCL10 is only supported on e6500
cores. We hard coded the threads number of each cluster to ensure the
cluster calculation is right.
Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
Change-Id: Ia329e48bac1a838828146df9b2caa7f527e329eb
Reviewed-on: http://git.am.freescale.net:8181/23177
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yuantian Tang <yuantian.tang@freescale.com>
Reviewed-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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LAW and MP information need to be backed up, or they will
lost when deep sleep wake up.
Previously, this is done by uboot. Now moved it to kernel
because entry point to kernel when resume is pretty early
in uboot.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Change-Id: I4542ddc77bd8d3461cf2e8bf02abeb74fa89e741
Reviewed-on: http://git.am.freescale.net:8181/23147
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
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Including: P3041DS P5020DS P5040DS B4QDS
The kernel config for this device is CONFIG_SENSORS_INA2XX.
Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
(cherry picked from commit bb192142c33657ec9f2e667878766031514829db)
Signed-off-by: Matthew Weigel <Matthew.Weigel@freescale.com>
Conflicts:
arch/powerpc/boot/dts/b4qds.dtsi
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Including: T1040RDB T1042RDB T208xQDS T208xRDB B4QDS T4240QDS
For T208xRDB and T4240QDS, ADT7481 is used. But kernel now only supports
ADT7461. So for now ADT7481 is treated as ADT7461.
The kernel config for thermal monitor is CONFIG_SENSORS_LM90.
Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com>
Change-Id: Ifae889c238fd53e0abc3b75516e484f1ccf6e659
Reviewed-on: http://git.am.freescale.net:8181/23080
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Yuantian Tang <yuantian.tang@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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CONFIG_MEMORY is required for IFC
Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Change-Id: I6605a908a4ee2bd0e8ef5b4f81456ee697138c63
Reviewed-on: http://git.am.freescale.net:8181/22565
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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which has 8KB CCSR memory space instead of 4KB on QMan rev1.
Change back 4KB CCSR memory space for QMan rev1 and rev2, then
update soc *-post device trees for those SoCs which have QMan v3.
Change-Id: I5878c1b87430c5f7f6f098399d7d55202109adcf
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/22072
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Now when the main kvm code relying on these defines has been moved to
the x86 specific part of the world, we can get rid of these.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Gleb Natapov <gleb@redhat.com>
(cherry picked from commit 2c5350e934501f1af8010c608d8dbf72ad25fdc6)
Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com>
Change-Id: Ia80e905cb81e7c88e82b5efd64f5f81eb3f4aa83
Reviewed-on: http://git.am.freescale.net:8181/22046
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Change-Id: I0a4d3aff82f65a11f47f41573e054a8a490bc984
Signed-off-by: Vakul Garg <vakul@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/20888
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Merge remote-tracking branch 't1024-linux/master'
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- Add usdpaa device tree for t1024qds and t1024rdb.
- Add default capwap dts for t1024qds and t1024rdb.
Signed-off-by: Vakul Garg <vakul@freescale.com>
Signed-off-by: Pan Jiafei <Jiafei.Pan@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Change-Id: Ic9da808112675f0c1db67307c96461b0b69f7260
Reviewed-on: http://git.am.freescale.net:8181/21427
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
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- enable mixed mode of MPIC for deep sleep
- add deep sleep support for t1024
- add SDXC support for T1024QDS
- add TDM node in dts for Maxim DS26522 Riser card.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Zhao Qiang <B45475@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Change-Id: I9cb45b4a02814a4f4cd0a320510361c424545d44
Reviewed-on: http://git.am.freescale.net:8181/21426
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
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The same hang issue was observed on T1024 as well.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Change-Id: Ifad3fff1b430be90b6cc9548a959365ecd28236d
Reviewed-on: http://git.am.freescale.net:8181/21425
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
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use the common compatible "fsl,deepsleep-cpld" for deepsleep on multiple boards.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Change-Id: I7efc5292421376d4ca62a4f1489ce7fb9258097d
Reviewed-on: http://git.am.freescale.net:8181/21424
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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This patch add the DIU platform support for T1024QDS board.
The hdmi port is verified on the board.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Change-Id: Iaf3c9d7a65a7abb7f96a0be863587aecc5ec4279
Reviewed-on: http://git.am.freescale.net:8181/21423
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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T1024RDB is a Freescale Reference Design Board that hosts the T1024 SoC.
T1024RDB board Overview
-----------------------
- Processor: T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- DDR: 64-bit 4GB DDR3L UDIMM with ECC and interleaving support
- Ethernet: two 10M/100M/1Gbps RGMII ports and one 10Gbps Base-T port on-board
- Accelerator: DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- SerDes: 4 lanes up to 10.3125GHz
- IFC: 128MB NOR Flash, 1GB NAND Flash and CPLD system controlling
- PCIe: one PCIe slot and two Mini-PCIe connectors on-board
- USB: two Type-A USB2.0 ports with internal PHY
- eSDHC: one SDHC/MMC/eMMC connector
- eSPI: one 64MB N25Q512 SPI flash
- QE-TDM: support TDM Riser card
- 32-bit RISC controller for flexible support of the communications peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
- I2C: four I2C controllers
- UART: two UART on board
- Deep sleep power management implementaion
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Change-Id: Ie933ad91dc0f214f84c40259f99bc6b0b927be87
Reviewed-on: http://git.am.freescale.net:8181/21422
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
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Add support for Freescale T1024/T1023 QorIQ Development System Board.
T1024QDS is a high-performance computing evaluation, development and
test platform for T1024 QorIQ Power Architecture processor.
T1024QDS board Overview
-----------------------
- T1024 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Accelerator: DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
- Ethernet interfaces:
- Two 10M/100M/1G RGMII ports on-board
- Three 1G/2.5Gbps SGMII ports
- Four 1Gbps QSGMII ports
- one 10Gbps XFI or 10G Base-KR interface
- SerDes: 4 lanes up to 10.3125GHz Supporting SGMII/QSGMII, XFI, PCIe, SATA and Aurora
- PCIe: Three PCI Express controllers with five PCIe slots.
- IFC: 128MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
- Video: DIU supports video up to 1280x1024x32 bpp.
- Chrontel CH7201 for HDMI connection.
- TI DS90C387R for direct LCD connection.
- Raw (not encoded) video connector for testing or other encoders.
- QUICC Engine block
- 32-bit RISC controller for flexible support of the communications peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
- Deep sleep power management implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- eSPI: Three SPI flash devices.
- SATA: one SATA 2.O.
- USB: Two USB2.0 ports with internal PHY (one Type-A and one micro Type mini-AB)
- eSDHC: Support SD, SDHC, SDXC and MMC/eMMC.
- I2C: Four I2C controllers.
- UART: Two UART on board.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Change-Id: I8d4f93e21c2f6d76fa09144994e9724596a3a601
Reviewed-on: http://git.am.freescale.net:8181/21421
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
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The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
- Three PCI Express 2.0 controllers
- Additional peripheral interfaces
- One SATA 2.0 controller
- Two USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/eSDHC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Change-Id: If6cc23503c20f25f1ae2d59d64e06bee2be85753
Reviewed-on: http://git.am.freescale.net:8181/21420
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
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corenetxx_fmanv3_smp_defconfig
T1024 and T1040 use the same defconfig(Corenet platform with FMan_v3 enabled).
- rename t1040_32bit_smp_defconfig to corenet32_fmanv3_smp_defconfig
- rename t1040_64bit_smp_defconfig to corenet64_fmanv3_smp_defconfig
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Change-Id: Ic6a7588b4e1233c9a41fcc84e3824dd7e9965152
Reviewed-on: http://git.am.freescale.net:8181/21415
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
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Erratum A-008116 can cause a Serial RapidIO phyiscal or
logical/transport error interrupt (PINTn) that orginates
on port 2 is incorrectly reported as originating on port 1.
Valid workaround needed if using Serial RapidIO port 2.
Upon detection of a Serial RapidIO interrupt, each port's
LTLEDCSR and PnEDCSR registers must be read to determine
the port origin.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Change-Id: Ide60f7c3bcb56f4d427102b307f895ed3c04cc45
Reviewed-on: http://git.am.freescale.net:8181/22436
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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On the t208xrdb and t1040rdb, the SPI devices use
n25q512ax3, and not n25q512a.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Change-Id: Ied5fdda2e98b24bc06e449bbb23d18e6d53fdde1
Reviewed-on: http://git.am.freescale.net:8181/22634
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Because m25p80.c depends on this option.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Change-Id: I599d54566a2b1c725bf34a08f1cf2ec446ab40c2
Reviewed-on: http://git.am.freescale.net:8181/22633
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Merge commit 'a8341457254bcbf5253109ac8c54904643f13e6f'
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PCL10 is a cluster low power state in which cluster clock is gated off.
For e6500-based platform, cluster will enter PCL10 state automatically
when all cores of this cluster are offline.
Signed-off-by: Hongtao Jia <hongtao.jia@freescale.com>
Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com>
Change-Id: Ibac7138ff685bbaeaed139629e9f2833e3148379
Reviewed-on: http://git.am.freescale.net:8181/22315
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
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