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2013-04-17powerpc: export debug register save function for KVMBharat Bhushan
KVM need this function when switching from vcpu to user-space thread. My subsequent patch will use this function. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
2013-04-17KVM: PPC: exit to user space on "ehpriv" instructionBharat Bhushan
"ehpriv" instruction is used for setting software breakpoints by user space. This patch adds support to exit to user space with "run->debug" have relevant information. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
2013-04-17booke: exit to user space if emulator requestBharat Bhushan
This allows the exit to user space if emulator request by returning EMULATE_EXIT_USER. This will be used in subsequent patches in list Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
2013-04-17KVM: extend EMULATE_EXIT_USER to support different exit reasonsBharat Bhushan
Currently the instruction emulator code returns EMULATE_EXIT_USER and common code initializes the "run->exit_reason = .." and "vcpu->arch.hcall_needed = .." with one fixed reason. But there can be different reasons when emulator need to exit to user space. To support that the "run->exit_reason = .." and "vcpu->arch.hcall_needed = .." initialization is moved a level up to emulator. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
2013-04-17Rename EMULATE_DO_PAPR to EMULATE_EXIT_USERBharat Bhushan
Instruction emulation return EMULATE_DO_PAPR when it requires exit to userspace on book3s. Similar return is required for booke. EMULATE_DO_PAPR reads out to be confusing so it is renamed to EMULATE_EXIT_USER. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
2013-04-17KVM: PPC: debug stub interface parameter definedBharat Bhushan
This patch defines the interface parameter for KVM_SET_GUEST_DEBUG ioctl support. Follow up patches will use this for setting up hardware breakpoints, watchpoints and software breakpoints. Also kvm_arch_vcpu_ioctl_set_guest_debug() is brought one level below. This is because I am not sure what is required for book3s. So this ioctl behaviour will not change for book3s. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
2013-04-17KVM: PPC: e500: Emulate TMCFG0 TMRN registerMihai Caraman
Emulate TMCFG0 TMRN register exposing one HW thread per vcpu. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Change-Id: I979a199c089a01d4f8039496314ae44512f9b980 Reviewed-on: http://git.am.freescale.net:8181/1474 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-17KVM: PPC: Book3E: Emulate MCSRR0/1 SPR and rfmci instructionMihai Caraman
Emulate MCSRR0/1 SPR and rfmci instruction since they are used by A-006198 erratum fix. Also fix kvm_exit_names array in the process. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Change-Id: I15372519a9b3010ab8dfb43255a8b78ef10c4893 Reviewed-on: http://git.am.freescale.net:8181/1299 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-17KVM: PPC: e500: Add e6500 core to Kconfig descriptionMihai Caraman
Add e6500 core to Kconfig description. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Change-Id: I6b073aec408739315df9573e10271541e2f9f4d1 Reviewed-on: http://git.am.freescale.net:8181/1255 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-17KVM: PPC: e500mc: Enable e6500 coresMihai Caraman
Extend processor compatibility names to e6500 cores. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Change-Id: Ibbf4e2e3d65c4192fe92dc75efb32e6f870fe2bd Reviewed-on: http://git.am.freescale.net:8181/1254 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-17KVM: PPC: e500: Remove E.PT and E.HV.LRAT categories from VCPUsMihai Caraman
Embedded.Page Table (E.PT) category is not supported yet in e6500 kernel. Configure TLBnCFG to remove E.PT and E.HV.LRAT categories from VCPUs. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Change-Id: Id2d73fd09784f9bfb741f1126b6772d841303e7e Reviewed-on: http://git.am.freescale.net:8181/1253 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-17KVM: PPC: e500: Emulate TLBnPS, EPTCFG registers and expose via ONE_REGMihai Caraman
MMU registers were exposed to user-space using sregs interface. Add them to ONE_REG interface using kvmppc_get_one_reg/kvmppc_set_one_reg delegation mechanism. Add support for TLBnPS registers available in MMU Architecture Version (MAV) 2.0. EPTCFG register defined by E.PT is accessed unconditionally by Linux guests in the presence of MAV 2.0. Emulate it now. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Change-Id: Idb1a31de66d9c649ac303631032edb7c8aefbb8f Reviewed-on: http://git.am.freescale.net:8181/1252 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-17KVM: PPC: e500: Move vcpu's MMU configuration to dedicated functionsMihai Caraman
Vcpu's MMU default configuration and geometry update logic was buried in a chunk of code. Move them to dedicated functions to add more clarity. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Change-Id: Ia352aaa01b3a2c981408525a3a3c09a016fee1e2 Reviewed-on: http://git.am.freescale.net:8181/1251 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-17KVM: PPC: Book3E: Refactor ONE_REG ioctl implementationMihai Caraman
Refactor Book3E ONE_REG ioctl implementation to use kvmppc_get_one_reg/ kvmppc_set_one_reg delegation interface introduced by Book3S. This is necessary for MMU SPRs which are platform specifics. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Change-Id: Iac2d6108f6fc0798a54d3c8f2bf0e33d51057b55 Reviewed-on: http://git.am.freescale.net:8181/1249 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-16b4_qds: add corenet_ds_init_earlyHaiying Wang
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Change-Id: Ie84e3f6f73d85ca07745bb4b1df2d90e6a31a021 Reviewed-on: http://git.am.freescale.net:8181/1356 Reviewed-by: Aggrwal Poonam-B10812 <Poonam.Aggrwal@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-16powerpc: Replaced tlbilx with tlbwe in the initialization codeDiana Craciun
On Freescale e6500 cores EPCR[DGTMI] controls whether guest supervisor state can execute TLB management instructions. If EPCR[DGTMI]=0 tlbwe and tlbilx are allowed to execute normally in the guest state. A hypervisor may choose to virtualize TLB1 and for this purpose it may use IPROT to protect the entries for being invalidated by the guest. However, because tlbwe and tlbilx execution in the guest state are sharing the same bit, it is not possible to have a scenario where tlbwe is allowed to be executed in guest state and tlbilx traps. When guest TLB management instructions are allowed to be executed in guest state the guest cannot use tlbilx to invalidate TLB1 guest entries. Linux is using tlbilx in the boot code to invalidate the temporary entries it creates when initializing the MMU. The patch is replacing the usage of tlbilx in initialization code with tlbwe with VALID bit cleared. Linux is also using tlbilx in other contexts (like huge pages or indirect entries) but removing the tlbilx from the initialization code offers the possibility to have scenarios under hypervisor which are not using huge pages or indirect entries. Signed-off-by: Diana Craciun <Diana.Craciun@freescale.com> Change-Id: Iebc083d54b16582bdb3a77fbddde75c1fc61f741 Reviewed-on: http://git.am.freescale.net:8181/1236 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-16powerpc/corenet/config: add missing SCSI configs forShaohui Xie
corenet64_smp_defconfig Otherwise there wil be no SCSI device nodes. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Change-Id: I86f9531d9b88d0fabfba4b1dcfd3f9e20bdcd576 Reviewed-on: http://git.am.freescale.net:8181/1392 Reviewed-by: Zang Tiefei-R61911 <tie-fei.zang@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-16powerpc/defconfig: Add new defconfigs for BSC913x platformsHarninder Rai
BSC913x are heterogeneous platforms having DSP and PowerPC. * Lot of new IPs like AIC (Antenna Interface Controller), RF (radio) etc * Such IPs are not present in any other 85xx platform * Lot of optimizations related to ethernet/ASF (Application Specific Fastpath) are enabled in this config For 913x platforms having more than one core, bsc913x_smp_defconfig is also added. Beyond CONFIG_SMP=y and its dependencies,this should be identical to bsc913x_defconfig Signed-off-by: Harninder Rai <harninder.rai@freescale.com> Change-Id: I2266e57c2136f85d08d64835959755bbce110301 Reviewed-on: http://git.am.freescale.net:8181/924 Reviewed-by: Gala Kumar-B11780 <kumar.gala@freescale.com> Reviewed-by: Burmi Naveen-B16502 <NaveenBurmi@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-16powerpc/85xx: add P1020RDB-PD platform supportJerry Huang
The p1020rdb-pd has the similar feature as the p1020rdb. Therefore, p1020rdb-pd use the same platform file as the p1/p2 rdb board. Overview of P1020RDB-PD platform: - DDR3 2GB - NOR flash 64MB - NAND flash 128MB - SPI flash 16MB - I2C EEPROM 256Kb - eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch - eTSEC2 (SGMII PHY) - eTSEC3 (RGMII PHY) - SDHC - 2 USB ports - 4 TDM ports - PCIe Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Change-Id: Ie5295fe5ba8b4490ab6b4c9a6fb85453da759f9a Reviewed-on: http://git.am.freescale.net:8181/1273 Reviewed-by: Xie Xiaobo-R63061 <X.Xie@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-16powerpc/85xx: add the P1020RDB-PD DTS supportHaijun.Zhang
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Change-Id: Ia9a6afd32ce096c14e55c1ba3cbd663eb24a51ff Reviewed-on: http://git.am.freescale.net:8181/1272 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-16powerpc/85xx: Enhance cache-sram kernel boot parameterClaudiu Manoil
Two command line parameters are combined into one since they should always be used simultaneously. The term offset is misleading, replace it with addr as it represents a physical address. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Change-Id: I46cb777524248c3cc9c84b6e131a5cb513a652ab Reviewed-on: http://git.am.freescale.net:8181/1237 Reviewed-by: Tang Yuantian-B29983 <yuantian.tang@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-15Merge remote-tracking branch 'fslkvm/for-sdk1.4' into verifyAndy Fleming
2013-04-15KVM: PPC: Fix mfspr/mtspr MMUCFG emulationMihai Caraman
On mfspr/mtspr emulation path Book3E's MMUCFG SPR with value 1015 clashes with G4's MSSSR0 SPR. Move MSSSR0 emulation from generic part to Books3S. MSSSR0 also clashes with Book3S's DABRX SPR. DABRX was not explicitly handled so Book3S execution flow will behave as before. Signed-off-by: Mihai Caraman <mihai.caraman@freescale.com> Change-Id: Ie4530a47a3b9a1121a74fc3314ac35255cc0591e Reviewed-on: http://git.am.freescale.net:8181/1250 Reviewed-by: Yoder Stuart-B08248 <stuart.yoder@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-15Add SOC version listHaijun Zhang
Add soc version list and checkout function fo mpc85xx. Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Change-Id: Iff4ba9356a5642094af1efaadb69920146c2da1b Reviewed-on: http://git.am.freescale.net:8181/1195 Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-12powerpc/rcpm: add sleep support for T4/B4 chipsChen-Hui Zhao
RCPM unit controls the power managment of T4/B4 chips. Software can access RCPM registers to put specific thread/core in PH10/PH15/PH20/PH30 state or put the device in LPM10/LPM20/LPM40 mode. The RCPM unit supports several wake up sources through internal timers and internal and external interrupts. When the device enter sleep state, it will be put in LPM20 mode. The command is "echo standby > /sys/power/state". Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> (cherry picked from commit 8b6d17409699ecac9799b9a68fdfeeb299f5f3a8) Change-Id: Id456db72f2d3af5c1638ab271f6cdabcc3794ded Reviewed-on: http://git.am.freescale.net:8181/1181 Reviewed-by: Wood Scott-B07421 <scottwood@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-12powerpc/rcpm: add sleep feature for SoCs using RCPMChen-Hui Zhao
The SoCs which have a RCPM (Run Control/Power Management) module support power management feature. This patch implements sleep feature. In sleep mode, the clocks of cores and unused IP blocks will be turned off. The IP blocks which are allowed to wake up the system are still running. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> (cherry picked from commit 96b915172420c4089d656f981c1c954ce3aa87bd) Change-Id: I3fcd637916a01777919a91e03ceef929e46a901b Reviewed-on: http://git.am.freescale.net:8181/1180 Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-12powerpc/e500: work around erratum A-006184Scott Wood
Erratum A-006184 says that a hang can happen under certain circumstances when taking an exception. The erratum workaround gives the use of a watchdog as an option, to get unstuck if a hang does occur. Signed-off-by: Scott Wood <scottwood@freescale.com> Change-Id: Ib63bea70bb2ad7ea4cee9b96ec4f7aefc21ea3b3 Reviewed-on: http://git.am.freescale.net:8181/1113 Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-12powerpc: Add DPA ETH support to defconfigsAndy Fleming
Change-Id: I12a97a69392476adcae8054fffa4fdbb5cab094f Signed-off-by: Andy Fleming <afleming@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/1266 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-12qoriq: Enable muxing MDIO busesAndy Fleming
The MDIO muxing drivers needed to be enabled on the platforms which use them, and the devices needed to be probed. Change-Id: I6aa210cabb663f63c44c2ddfa5ccc9941e4799ab Signed-off-by: Andy Fleming <afleming@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/1265 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-12dpaa_eth: Add compatible string to parent deviceBogdan Hamciuc
Make it so our probing function is called at boot-time. Signed-off-by: Bogdan Hamciuc <bogdan.hamciuc@freescale.com> Change-Id: Iaea6116e679216a6d8432643a55c2036e4e07b1a Reviewed-on: http://git.am.freescale.net:8181/1264 Reviewed-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com> Tested-by: Fleming Andrew-AFLEMING <AFLEMING@freescale.com>
2013-04-11kvm/powerpc/e500mc: fix tlb invalidation on cpu migrationScott Wood
The existing check handles the case where we've migrated to a different core than we last ran on, but it doesn't handle the case where we're still on the same cpu we last ran on, but some other vcpu has run on this cpu in the meantime. Without this, guest segfaults (and other misbehavior) have been seen in smp guests. Cc: stable@vger.kernel.org # 3.8.x Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: Remove unused argument to kvmppc_core_dequeue_externalPaul Mackerras
Currently kvmppc_core_dequeue_external() takes a struct kvm_interrupt * argument and does nothing with it, in any of its implementations. This removes it in order to make things easier for forthcoming in-kernel interrupt controller emulation code. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11kvm/ppc/e500: eliminate tlb_refsScott Wood
Commit 523f0e5421c12610527c620b983b443f329e3a32 ("KVM: PPC: E500: Explicitly mark shadow maps invalid") began using E500_TLB_VALID for guest TLB1 entries, and skipping invalidations if it's not set. However, when E500_TLB_VALID was set for such entries, it was on a fake local ref, and so the invalidations never happen. gtlb_privs is documented as being only for guest TLB0, though we already violate that with E500_TLB_BITMAP. Now that we have MMU notifiers, and thus don't need to actually retain a reference to the mapped pages, get rid of tlb_refs, and use gtlb_privs for E500_TLB_VALID in TLB1. Since we can have more than one host TLB entry for a given tlbe_ref, be careful not to clear existing flags that are relevant to other host TLB entries when preparing a new host TLB entry. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11kvm/ppc/e500: g2h_tlb1_map: clear old bit before setting new bitScott Wood
It's possible that we're using the same host TLB1 slot to map (a presumably different portion of) the same guest TLB1 entry. Clear the bit in the map before setting it, so that if the esels are the same the bit will remain set. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11kvm/ppc/e500: h2g_tlb1_rmap: esel 0 is validScott Wood
Add one to esel values in h2g_tlb1_rmap, so that "no mapping" can be distinguished from "esel 0". Note that we're not saved by the fact that host esel 0 is reserved for non-KVM use, because KVM host esel numbering is not the raw host numbering (see to_htlb1_esel). Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: booke: Added debug handlerBharat Bhushan
Installed debug handler will be used for guest debug support and debug facility emulation features (patches for these features will follow this patch). Signed-off-by: Liu Yu <yu.liu@freescale.com> [bharat.bhushan@freescale.com: Substantial changes] Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: Added one_reg interface for timer registersBharat Bhushan
If userspace wants to change some specific bits of TSR (timer status register) then it uses GET/SET_SREGS ioctl interface. So the steps will be: i) user-space will make get ioctl, ii) change TSR in userspace iii) then make set ioctl. It can happen that TSR gets changed by kernel after step i) and before step iii). To avoid this we have added below one_reg ioctls for oring and clearing specific bits in TSR. This patch adds one registerface for: 1) setting specific bit in TSR (timer status register) 2) clearing specific bit in TSR (timer status register) 3) setting/getting the TCR register. There are cases where we want to only change TCR and not TSR. Although we can uses SREGS without KVM_SREGS_E_UPDATE_TSR flag but I think one reg is better. I am open if someone feels we should use SREGS only here. 4) getting/setting TSR register Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: move tsr update in a separate functionBharat Bhushan
This is done so that same function can be called from SREGS and ONE_REG interface (follow up patch). Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: BookE: Handle alignment interruptsAlexander Graf
When the guest triggers an alignment interrupt, we don't handle it properly today and instead BUG_ON(). This really shouldn't happen. Instead, we should just pass the interrupt back into the guest so it can deal with it. Reported-by: Gao Guanhua-B22826 <B22826@freescale.com> Tested-by: Gao Guanhua-B22826 <B22826@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: booke: Allow multiple exception typesBharat Bhushan
Current kvmppc_booke_handlers uses the same macro (KVM_HANDLER) and all handlers are considered to be the same size. This will not be the case if we want to use different macros for different handlers. This patch improves the kvmppc_booke_handler so that it can support different macros for different handlers. Signed-off-by: Liu Yu <yu.liu@freescale.com> [bharat.bhushan@freescale.com: Substantial changes] Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: booke: use vcpu reference from thread_structBharat Bhushan
Like other places, use thread_struct to get vcpu reference. Signed-off-by: Bharat Bhushan <bharat.bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: E500: Remove kvmppc_e500_tlbil_all usage from guest TLB codeAlexander Graf
The guest TLB handling code should not have any insight into how the host TLB shadow code works. kvmppc_e500_tlbil_all() is a function that is used for distinction between e500v2 and e500mc (E.HV) on how to flush shadow entries. This function really is private between the e500.c/e500mc.c file and e500_mmu_host.c. Instead of this one, use the public kvmppc_core_flush_tlb() function to flush all shadow TLB entries. As a nice side effect, with this we also end up flushing TLB1 entries which we forgot to do before. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: E500: Make clear_tlb_refs and clear_tlb1_bitmap staticAlexander Graf
Host shadow TLB flushing is logic that the guest TLB code should have no insight about. Declare the internal clear_tlb_refs and clear_tlb1_bitmap functions static to the host TLB handling file. Instead of these, we can use the already exported kvmppc_core_flush_tlb(). This gives us a common API across the board to say "please flush any pending host shadow translation". Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: e500: Implement TLB1-in-TLB0 mappingAlexander Graf
When a host mapping fault happens in a guest TLB1 entry today, we map the translated guest entry into the host's TLB1. This isn't particularly clever when the guest is mapped by normal 4k pages, since these would be a lot better to put into TLB0 instead. This patch adds the required logic to map 4k TLB1 shadow maps into the host's TLB0. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: E500: Split host and guest MMU partsAlexander Graf
This patch splits the file e500_tlb.c into e500_mmu.c (guest TLB handling) and e500_mmu_host.c (host TLB handling). The main benefit of this split is readability and maintainability. It's just a lot harder to write dirty code :). Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: e500: Call kvmppc_mmu_map for initial mappingAlexander Graf
When emulating tlbwe, we want to automatically map the entry that just got written in our shadow TLB map, because chances are quite high that it's going to be used very soon. Today this happens explicitly, duplicating all the logic that is in kvmppc_mmu_map() already. Just call that one instead. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: E500: Propagate errors when shadow mappingAlexander Graf
When shadow mapping a page, mapping this page can fail. In that case we don't have a shadow map. Take this case into account, otherwise we might end up writing bogus TLB entries into the host TLB. While at it, also move the write_stlbe() calls into the respective TLBn handlers. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: E500: Explicitly mark shadow maps invalidAlexander Graf
When we invalidate shadow TLB maps on the host, we don't mark them as not valid. But we should. Fix this by removing the E500_TLB_VALID from their flags when invalidating. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: E500: Move write_stlbe higherAlexander Graf
Later patches want to call the function and it doesn't have dependencies on anything below write_host_tlbe. Move it higher up in the file. Signed-off-by: Alexander Graf <agraf@suse.de>
2013-04-11KVM: PPC: BookE: Add EPR ONE_REG syncAlexander Graf
We need to be able to read and write the contents of the EPR register from user space. This patch implements that logic through the ONE_REG API and declares its (never implemented) SREGS counterpart as deprecated. Signed-off-by: Alexander Graf <agraf@suse.de>
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