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2014-12-11ls1021aqds: add qe node to ls1021aqds dtsZhao Qiang
add qe node(qe-tdm and qe-uart) into ls1021a-qds.dts Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I1ab52c2330246e807fd4c96103d2c063b6d8d8ba Reviewed-on: http://git.am.freescale.net:8181/21868 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ls1021a/dts: Add device nodes for FlexCAN IP instancesBhupesh Sharma
This patch adds the device nodes for 4 FlexCAN IP instances available on LS1021A SoC in the ls1021a.dtsi file and enables only the first two instances which are supported on the QDS board in ls1021a-qds.dts file. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> --- Previous version of this patch under review upstream: http://patchwork.ozlabs.org/patch/363588/ Will re-spin the patch with the DTS Change-Id: I592e5f8562ad173801a53433aec9a91b00ba8bb0 Reviewed-on: http://git.am.freescale.net:8181/21855 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11Enable IFC for ls1021Jaiprakash Singh
Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Change-Id: I501144de5deaecb1bbbe913fc1ef82e8102d84a3 Reviewed-on: http://git.am.freescale.net:8181/21811 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm/dts/ls1021a: Add GPIO controller nodesShaveta Leekha
Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Change-Id: Ib16b8e2466757d782ec4bb5e8549f2dcb9208e32 Reviewed-on: http://git.am.freescale.net:8181/21801 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11gpio: enable GPIO support in ls1021a_defconfigShaveta Leekha
LS1021a-qds has the same controller as GPIO on powerpc platform(MPC8XXX), so remove GPIO_MXC and add the one for GPIO_MPC8XXX Enable gpio as default Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Change-Id: I13531087c312ef9fa3bb607b5202592d13b29727 Reviewed-on: http://git.am.freescale.net:8181/21800 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm:dts:ls1021a-twr:correct qspi flash informationChao Fu
Correct qspi flash information on ls1021a-qds board. And remove flash partion in node, it is not useful. Signed-off-by: Chao Fu <B44548@freescale.com> Change-Id: I8b2dc47446c5d54ce12e3d7d138fa9d9a3b9ba6c Reviewed-on: http://git.am.freescale.net:8181/21364 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm:dts:ls1021a-qds:correct qspi flash informationChao Fu
Correct qspi flash information on ls1021a-qds board. And remove flash partion in node, it is not useful. Signed-off-by: Chao Fu <B44548@freescale.com> Change-Id: Ib9b3964127984457032f73be53bbfc847cf438bf Reviewed-on: http://git.am.freescale.net:8181/21360 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm:dts:ls1021a:add qspi-memory address and correct qspi compatibleChao Fu
The new QSPI driver add DDR read mode, so add qspi-memory map for QSPI access in DDR mode in dts node. Modify qspi node compatible for LS1 paltform. Signed-off-by: Chao Fu <b44548@freescale.com> Change-Id: Ia92dda63bf857b845767ae62f2c7eb9a84371aa1 Reviewed-on: http://git.am.freescale.net:8181/21356 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ls1021a: Enable GIANFAR for LS1Claudiu Manoil
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Change-Id: Ie34306997587de53d71a44d643989a3808644a4c Reviewed-on: http://git.am.freescale.net:8181/21178 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: ls1021a: add gating clocks to IP blocks.Xiubo Li
A given application may not use all the peripherals on the device. In this case, it may be desirable to disable unused peripherals. DCFG provides a mechanism for gating clocks to IP blocks that are not used when running an application. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> --- This patch has been sent out to the community and under discussion： URL：http://www.spinics.net/lists/arm-kernel/msg370133.html Change-Id: Iedf07d12955b3fa011a0bef27236f73405cefb44 Reviewed-on: http://git.am.freescale.net:8181/21604 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11fb: dcu: convert to use regmap API.Xiubo Li
The regmap framework has one feature of register cache, which will be more easy to add big endian mode and PM support. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> -- The first DRM version will be send out to the community before 15 Dec 2014. Change-Id: I3aa3c30f4ab42b64b80669b483b45a62ae31d6bb Reviewed-on: http://git.am.freescale.net:8181/21571 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Dongsheng Wang <dongsheng.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11driver/memory:Move Freescale IFC driver to a common driverb44839
Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/memory and fix the header file includes. Also remove module_platform_driver() and instead call platform_driver_register() from subsys_initcall() to make sure this module has been loaded before MTD partition parsing starts. Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> --- Cherry-picked from:d2ae2e20fbdde5a65f3a5a153044ab1e5c53f7cc Change-Id: I3cc83c716adf27a4988b818d57706980dbbefdea Reviewed-on: http://git.am.freescale.net:8181/20970 Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
2014-12-11arm: dts: ls1021a-twr: add SII9022A HDMI DT nodeXiubo Li
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> --- The first DRM version will be send out to the community before 30 November 2014. Change-Id: Ia5538da4db87431fd80ffaacc07c201d20a8bc2b Reviewed-on: http://git.am.freescale.net:8181/19651 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: dts: ls1021a: Add DCU nodeXiubo Li
This patch adds DCU node in SoC level DTS for Freescale LS1021A-TWR. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> --- The first DRM version will be send out to the community before 30 November 2014. Change-Id: I74671a92d530699be6868f7f1591eadbd40a6879 Reviewed-on: http://git.am.freescale.net:8181/19649 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11dtsi: ls1021a: Add 40-bit dt node support for DCU.Xiubo Li
Signed-off-by: Alison Wang <b18965@freescale.com> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> --- The first DRM version will be send out to the community before 30 November 2014. Change-Id: I6a20f9f5c1b8b8c596e635b25aa37055e23f82a7 Reviewed-on: http://git.am.freescale.net:8181/19648 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ls1021a-twr/qe: add qe node to ls1-twrZhao Qiang
add qe node to ls1021atwr fdt. Signed-off-by: Zhao Qiang <B45475@freescale.com> --- upstream link: http://patchwork.ozlabs.org/patch/398470/ it is under discussion. Change-Id: I4f0bc40003265f85bde01a9982ef7f91edd1d08e Reviewed-on: http://git.am.freescale.net:8181/21121 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11qe-uart: modify qe-uart to adapt both powerpc and armZhao Qiang
qe has been supported by arm board ls1021, qe-uart need to be supported by ls1021. modify the code to make qe-uart can work on both powerpc and ls1021. Signed-off-by: Zhao Qiang <B45475@freescale.com> --- upstream link: http://patchwork.ozlabs.org/patch/398471/ it is under discussion. Change-Id: I07a9a091882cd572330b38e7a6e0632aea9a9042 Reviewed-on: http://git.am.freescale.net:8181/21119 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11rheap: move rheap.c from arch/powerpc/lib/ to lib/Zhao Qiang
qe need to use the rheap, so move it to public directory. Signed-off-by: Zhao Qiang <B45475@freescale.com> --- upstream link: http://patchwork.ozlabs.org/patch/393170/ it is under discussion. Change-Id: Ied2765d6e0eb3b7ade0fef02cfe226c8a8566c5f Reviewed-on: http://git.am.freescale.net:8181/16841 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11qe: move qe from arch/powerpc/sysdev/ to drivers/soc/Zhao Qiang
ls1 has qe ip block too, so move qe code from platform directory to public directory. Signed-off-by: Zhao Qiang <B45475@freescale.com> --- patch on upstream can be found with this link: http://patchwork.ozlabs.org/patch/385724/, it is under discussion Change-Id: I39aed531a4792990e3bb8ecc6f4e57f8d9b41bae Reviewed-on: http://git.am.freescale.net:8181/15818 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11Revert "arm: ls1021a: remove the FSL_SOC config added by SOC_LS1021A"Jingchang Lu
This reverts commit 14bbc976701a2ebc62343d3122e5ff772060a35f. LS1021A shares IPs with sophisticated PowerPC platform, many PowerPC drivers have depends on FSL_SOC defination, so to consistent with this, FSL_SOC is introduced. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: Ie5a69b78d317d09f9fee54dde3f1cd4bffdb9588 Reviewed-on: http://git.am.freescale.net:8181/19915 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm:dts:ls1021a: add PCIe device nodeMinghuan Lian
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Change-Id: I5deb88a99bd7b5d40251a4935d4d8a556abad7ae Reviewed-on: http://git.am.freescale.net:8181/19712 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com> Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: ls1021a: remove dma_zone_size definationJingchang Lu
CONFIG_ZONE_DMA is enough to claim the dma limitation, and no need for limitation smaller than 4GB, so remove the dma_zone_size defination. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- the upstream include this change in patchwork is: https://patchwork.kernel.org/patch/4946151/ Change-Id: Ia2ed1fd18519e1e2553e2aa8ce1c1729657a6ed3 Reviewed-on: http://git.am.freescale.net:8181/19874 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: configs: ls1021a: enable LTC2945, WDT and CLK_QOIRQJingchang Lu
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I7cde95ba1ca9acbf6d2d01649b3ecb3d08db02c1 Reviewed-on: http://git.am.freescale.net:8181/19912 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Hongtao Jia <hongtao.jia@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11Add LTC2945 node to ls1021a-twr.dtsJia Hongtao
Signed-off-by: Jia Hongtao <hongtao.jia@freescale.com> Change-Id: I08008c3dcd2b85b0c54b9f9ee939287f57745517 Reviewed-on: http://git.am.freescale.net:8181/19641 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a: add wakeup device ftm0 node for ls1021aWang Dongsheng
Add ftm0 node, cause of ftm0 can be set as a alarm before system going to deep sleep. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Change-Id: Ie337ec554f6acd625cd691a0e07ffb96807cfa10 Reviewed-on: http://git.am.freescale.net:8181/19838 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm : dts : ls1021a : Modify USB3.0 dts nodeSuresh Gupta
Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Change-Id: I7aa37e4914623a303eb520c6d8fd6d4f84e9ddb2 Reviewed-on: http://git.am.freescale.net:8181/19815 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm : dts : ls1021a : Remove unwanted code from USB2.0 dts nodeNikhil Badola
Remove #address-cells and #size-cells from USB 2.0 node in ls1021a Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Change-Id: Ia2ff9aea201ef18b352437bda267571c235db689 Reviewed-on: http://git.am.freescale.net:8181/15675 Reviewed-by: Jingchang Lu <jingchang.lu@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a: add alias for the clockgen sysclk nodeJingchang Lu
This add an alias named sysclk for the sysclk node for fdt fixup procedure locating it uniquely. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I7e6bd6cb4d81fe44c73944be91cab3fe56810094 Reviewed-on: http://git.am.freescale.net:8181/19199 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com> Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a: change sysclk compatible to "fixed-clock"Jingchang Lu
The sysclk could be well probed by "fixed-clock" compatible, no custom compatible is needed any more. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I17a21e20ced4304e716e5a9ba07ff56b2adb45a7 Reviewed-on: http://git.am.freescale.net:8181/17833 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a: remove the tbi node from SoC level dtsJingchang Lu
remove the tbi node which will be added to boards level dts. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I1b7893526e63d0207637f2ae0576c9d5f62a6a06 Reviewed-on: http://git.am.freescale.net:8181/17829 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a-twr: add aliases for enet phyJingchang Lu
This add aliases for enet phy to make it be found easily in u-boot on dynamically change the enet "phy-handle" and "phy-connection-type" property. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I60e19aa48856c9b9048415d1c8924b626d70332a Reviewed-on: http://git.am.freescale.net:8181/17831 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a-qds: add tbi node and aliases for enet phyJingchang Lu
This move the tbi node to boards level device tree source. And add aliases for enet phy to make it be found easily by u-boot on dynamically change the enet "phy-handle" and "phy-connection-type" property. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I80748fdbbeab06cb5804128600369317dbececd6 Reviewed-on: http://git.am.freescale.net:8181/17830 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: ls1021a: remove the FSL_SOC config added by SOC_LS1021AJingchang Lu
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I2deac22e04a04c2523c7839d5974a41288e5bb2b Reviewed-on: http://git.am.freescale.net:8181/17837 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: dts: ls1021a: change duart compatible to "fsl,16550-FIFO64"Jingchang Lu
this patch change the duart compatible to 64-byte FIFO mode. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: I4d306671daed4262a6f354a3507304d82468c41d Reviewed-on: http://git.am.freescale.net:8181/17835 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11arm: configs: add Freescale LS1021A initial defconfigJingchang Lu
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Change-Id: Ia3ba1dbeb66d4c929cfe19122d221a2af36377f8 Reviewed-on: http://git.am.freescale.net:8181/17838 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Huan Wang <alison.wang@freescale.com> Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com> Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
2014-12-11ARM: imx: Add Freescale LS1021A SMP supportJingchang Lu
Freescale LS1021A SoC deploys two cortex-A7 processors, this adds bring-up support for the secondary core. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464481/
2014-12-11ARM: imx: Add initial support for Freescale LS1021AJingchang Lu
The LS1021A SoC is a dual-core Cortex-A7 based processor, this add the initial support for it. Signed-off-by: Jingchang Lu <b35083@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464451/
2014-12-11ARM: dts: Add initial LS1021A TWR board dts supportJingchang Lu
Signed-off-by: Chen Lu <B46807@freescale.com> Signed-off-by: Chao Fu <B44548@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464461/
2014-12-11ARM: dts: Add initial LS1021A QDS board dts supportJingchang Lu
Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Chao Fu <B44548@freescale.com> Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464471/
2014-12-11ARM: dts: Add SoC level device tree support for LS1021AJingchang Lu
Add Freescale LS1021A SoC device tree support Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Adrian Sendroiu <adrian.sendroiu@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Chao Fu <b44548@freescale.com> Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Zhao Qiang <B45475@freescale.com> Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> --- This patch has been sent to upstream for review: https://patchwork.kernel.org/patch/4464491/
2014-12-11ARM: call of_clk_init from default time_init handlerSebastian Hesselbarth
Most DT ARM machs require common clock providers initialized before timers. Currently, arch/arm machs use .init_time to call of_clk_init right before clocksource_of_init. This prevents to remove that callback and use the default one instead. This patch adds a call to of_clk_init() to the default .init_time callback for COMMON_CLK enabled machs to allow to remove custom callbacks where applicable. While at it, also reorder includes alphabetically. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> --- This patch is pulled back from upstream: commit 4178bac4f6e955869395b30246687d41183a5edb
2014-12-11powerpc/e6500: Work around erratum A-008139Scott Wood
Erratum A-008139 can cause duplicate TLB entries if an indirect entry is overwritten using tlbwe while the other thread is using it to do a lookup. Work around this by using tlbilx to invalidate prior to overwriting. To avoid the need to save another register to hold MAS1 during the workaround code, TID clearing has been moved from tlb_miss_kernel_e6500 until after the SMT section. Signed-off-by: Scott Wood <scottwood@freescale.com> (cherry picked from commit 48cd9b5d590aee1664170968a9eae068e36761eb) Change-Id: I34cc02219f9081dbf8ff7729677a995b7a8bb4c5 Reviewed-on: http://git.am.freescale.net:8181/19463 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Mihai Caraman <mihai.caraman@freescale.com> Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
2014-10-19fmd: add new dtsi file for fmanV3LMandy Lavi
Change-Id: I65f6c770784cdf4ff8e5a16283597aec86daee56 Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com> Reviewed-on: http://git.am.freescale.net:8181/17428 Reviewed-by: Igal Liberman <Igal.Liberman@freescale.com> Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com> Tested-by: Mandy Lavi <Mandy.Lavi@freescale.com>
2014-09-17qe-tdm: move siram_init_flag to qe.cZhao Qiang
Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: Id21f861ffec995ad68378a9d2eda245ef989b489 Reviewed-on: http://git.am.freescale.net:8181/19009 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
2014-09-17qe-hdlc: qe-hdlc work in normal mode instead of internal-loopback modeZhao Qiang
qe-hdlc worked in internal-loopback without TDMR ds26522, now it can work with TDMR ds26522 in normal mode, so modify it to normal mode. Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I7eeb4ec196d74cb53f3bffced0889637c72ed5d6 Reviewed-on: http://git.am.freescale.net:8181/19008 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
2014-09-17t1040rdb: add slic tdm node to t1040rdbZhao Qiang
add slic tdm node into t1040rdb.dts Signed-off-by: Zhao Qiang <B45475@freescale.com> Change-Id: I1862ebef1b7bfd5a43258afbd62bcfe417dc61c0 Reviewed-on: http://git.am.freescale.net:8181/19000 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Xiaobo Xie <X.Xie@freescale.com> Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
2014-09-05T104xRDB/dts: add bqman node placeholder before fman to support ARZhang Zhuoyu
the device tree is walked in a bottom-up order to suspend devices. Callback sequence of devices is determinated by the first time it appears in device tree not where it is defined, thus add two placeholders of bqman before fman to make sure fman suspended before bqman. Signed-off-by: Zhang Zhuoyu <Zhuoyu.Zhang@freescale.com>
2014-08-07merge ENGR00300868Rich Schmitt
2014-08-06Revert "powerpc: Enable erratum A-008007 workaorund for T1040 Rev1.0"Priyanka Jain
This reverts commit 062853ac8f4b6fb5fee1770b67d4684023929e10. New PBI-based workaround which resets PVR register for erratum A-008007 is implemented in RCW. So no workaround implementation is required in Linux Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Change-Id: I6d952796efda066fd648179dd9508a0f8c4c2ba2 Reviewed-on: http://git.am.freescale.net:8181/15311 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Tested-by: Richard Schmitt <richard.schmitt@freescale.com> Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
2014-08-06powerpc/fsl-booke: Add initial T1042RDB board supportVijay Rai
T1042RDB is Freescale Reference Design Board supporting the T1042 QorIQ Power Architecture processor. T1042RDB board Overview ----------------------- - SERDES Connections, 8 lanes supporting: - PCI - SGMII - SATA 2.0 - DDR Controller - Supports rates of up to 1600 MHz data-rate - Supports one DDR3LP UDIMM - IFC/Local Bus - NAND flash: 1GB 8-bit NAND flash - NOR: 128MB 16-bit NOR Flash - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - CPLD - Clocks - System and DDR clock (SYSCLK, DDRCLK) - SERDES clocks - Power Supplies - USB - Supports two USB 2.0 ports with integrated PHYs - Two type A ports with 5V@1.5A per port. - SDHC - SDHC/SDXC connector - SPI - On-board 64MB SPI flash - I2C - Devices connected: EEPROM, thermal monitor, VID controller - Other IO - Two Serial ports - ProfiBus port Add support for T1042 RDB board: -add device tree Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Change-Id: I4dd5e168e4e6e62e10a362ec41b1edc33f988731 Reviewed-on: http://git.am.freescale.net:8181/15312 Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com> Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
generated by cgit v0.10.2 at 2024-08-08 09:26:00 (GMT)