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path: root/drivers/gpu/drm/nouveau/core
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2013-07-08drm/nvc0/gr: fix gpc firmware regressionMaarten Lankhorst
"drm/nve0-/gr: some new gpc registers can have multiple copies" 5ee86c4190f9e caused a regression for nvc0, because the bit indicating last transfer has occured was no longer set, resulting in random system lockups. Reported-by: Ronald Uitermark <ronald645@gmail.com> Tested-by: Ronald Uitermark <ronald645@gmail.com> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nva3/disp: Fix HDMI audio regressionIlia Mirkin
This is the nva3 counterpart to commit beba44b17 (drm/nv84/disp: Fix HDMI audio regression). The regression happened as a result of refactoring in commit 8e9e3d2de (drm/nv84/disp: move hdmi control into core). Reported-and-tested-by: Max Baldwin <archerseven@gmail.com> Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Cc: stable@vger.kernel.org
2013-07-05drm/nv50-/disp: Use output specific mask in interruptEmil Velikov
The commit commit 476e84e126171d809f9c0b5d97137f5055f95ca8 Author: Ben Skeggs <bskeggs@redhat.com> Date: Mon Feb 11 09:24:23 2013 +1000 drm/nv50-/disp: initial supervisor support for off-chip encoders changed the write mask in one of the interrupt functions for on-chip encoders, causing a regression in certain VGA dual-head setups. This commit reintroduces the mask thus resolving the regression Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66129 Reported-and-Tested-by: Yves-Alexis <corsac@debian.org> Cc: stable@vger.kernel.org [3.9+] CC: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nouveau: use vmalloc for pgt allocationMarcin Slusarz
Page tables on nv50 take 48kB, which can be hard to allocate in one piece. Let's use vmalloc. Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com> Cc: stable@vger.kernel.org [3.7+] Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: remove some more of the hardcoded register writesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: factor out yet more unknown magic into versioned functionsBen Skeggs
NVC1/NVD9 are the only chipsets that should have anything different happen on them after this. We previously weren't doing these register modifications, and NVIDIA do. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvd7/devinit: use fermi class, not teslaBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvf0-/gr: ctxsw scratch reg count got bumped to 16Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: remove hardcoding of UNK count/mask in GPCCS ucodeBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvf0/gr: build cs ucode for GK110Ben Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: extend one of the magic calculations for >4 GPCsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvf0/gr: fix ddx shaders locking up on meBen Skeggs
This can be generalised and used on GK104 (probably even GF117), but lets just make it work for now. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0/devinit: minor typoBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvf0/gr: enable support, if external cs ucode is availableBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvf0/gr: magic sequence that makes PGRAPH come out of hidingBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvf0/ce: enable supportBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvf0/fifo: enable supportBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvd7/gr: initial supportMaarten Lankhorst
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: generate cs register lists from grctx dataBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: tpc regs a subset of gpc, add separate list for gpc/unk regsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nve0-/gr: some new gpc registers can have multiple copiesBen Skeggs
GK110 exposes more than one, and needs to be dealt with in the ctxsw ucode just like the TPC sets are. Broadcast is at +0xe00. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: pull out a group of separately context-switched gpc regsBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05drm/nvc0-/gr: make register lists from initvals functionsBen Skeggs
Generated context verified to be the same for all supported chipsets. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvd0-/disp: handle case where display engine is missing/disabledMaarten Lankhorst
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4Ben Skeggs
No code changes, proven by envyas producing identical binaries. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/bsp/nv84: initial vp2 engine implementationIlia Mirkin
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/vp/nv84: initial vp2 engine implementationIlia Mirkin
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/core: xtensa engine base class implementationIlia Mirkin
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/vdec: fork vp3 implementations from vp2Ilia Mirkin
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/core: move falcon class to engine/Ben Skeggs
Not really "core" per-se. About to merge Ilia's work adding another similar class for the VP2 xtensa engines, so, seems like a good time to move all these to engine/. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/vm: perform a bar flush when flushing vmMaarten Lankhorst
Appears to fix the regression from "drm/nvc0/vm: handle bar tlb flushes internally". nvidia always seems to do this flush after writing values. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switchesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc8/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc4/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc1/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc3/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc0/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvd9/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve4/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc0-/gr: bump maximum gpc/tpc limitsBen Skeggs
Needed for GK110, separate commit to catch any unexpected breaks to other parts of the code. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvf0/gr: initial register/context setupBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve7/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nve6/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/vm: make each vma take a reference on its parent vmBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/core: remove nouveau_mm.mutex, no more usersBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/vm: take subdev mutex, not the mm, protects against race with ↵Ben Skeggs
vm/nvc0 nvc0_vm_flush() accesses the pgd list, which will soon be able to race with vm_unlink() during channel destruction. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc0/vm: handle bar tlb flushes internallyBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nv50-/vm: take mutex rather than irqsave spinlockBen Skeggs
These operations can take quite some time, and we really don't want to have to hold a spinlock for too long. Now that the lock ordering for vm and the gr/nv84 hw bug workaround has been reversed, it's possible to use a mutex here. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nv50/vm: remove explicit vm knowledge from enginesBen Skeggs
This reverses the lock ordering between VM and gr/nv84:nvc0. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nv50/vm: handle bar tlb flushes internallyBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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