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path: root/drivers/gpu
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2013-07-08drm/radeon/dpm: implement vblank_too_short callback for siAlex Deucher
Check if we can switch the mclk during the vblank time otherwise we may get artifacts on the screen when the mclk changes. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08drm/radeon/dpm: implement vblank_too_short callback for caymanAlex Deucher
Check if we can switch the mclk during the vblank time otherwise we may get artifacts on the screen when the mclk changes. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08drm/radeon/dpm: implement vblank_too_short callback for btcAlex Deucher
Check if we can switch the mclk during the vblank time otherwise we may get artifacts on the screen when the mclk changes. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08drm/radeon/dpm: implement vblank_too_short callback for evergreenAlex Deucher
Check if we can switch the mclk during the vblank time otherwise we may get artifacts on the screen when the mclk changes. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08drm/radeon/dpm: implement vblank_too_short callback for 7xxAlex Deucher
Check if we can switch the mclk during the vblank time otherwise we may get artifacts on the screen when the mclk changes. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08drm/radeon/dpm: add checks against vblank timeAlex Deucher
If the vblank time is too short to adjust mclk, assume multiple displays (no mclk adjustments). Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08drm/radeon/dpm: add helper to calculate vblank timeAlex Deucher
Required for checking vblank time for mclk changes. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08drm/radeon: remove stray line in old pm codeAlex Deucher
Looks like a remnant from an old rebase. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08drm/radeon/dpm: fix display_gap programming on rv7xxAlex Deucher
Check the driver state rather than the register as the crtc registers may not be enabled yet. Should fix: https://bugzilla.kernel.org/show_bug.cgi?id=60510 https://bugs.freedesktop.org/show_bug.cgi?id=66651 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05drm/radeon/dpm: implement force performance level for TNAlex Deucher
Allows you to force the selected performance level via sysfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05drm/radeon/dpm: implement force performance level for ON/LNAlex Deucher
Allows you to force the selected performance level via sysfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05drm/radeon/dpm: implement force performance level for SIAlex Deucher
Allows you to force the selected performance level via sysfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05drm/radeon/dpm: implement force performance level for caymanAlex Deucher
Allows you to force a performance level via sysfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05drm/radeon/dpm: implement force performance levels for 7xx/eg/btcAlex Deucher
Allows you to limit the selected power levels via sysfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05drm/radeon/dpm: add infrastructure to force performance levelsAlex Deucher
This allows you to force specific power levels within a power state. Due to hardware restrictions between generations, the interface is limited to the following 3 selections: auto: all levels enabled low: forced to the lowest power level high: forced to the highest power level Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05drm/radeon: fix surface setup on r1xxAlex Deucher
r1xx asics have a slightly different surface register setup compared to newer asics. There is no specific enable bit for macro tiling, rather, to disable macro tiling, you need to set the surface pitch to 0. With this fixed, the special rn50 handling can go. Noticed-by: Mark Kettenis <mark.kettenis@xs4all.nl> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05drm/radeon: add support for 3d perf states on older asicsAlex Deucher
Certain older rv770 asics have both a performance and a 3D performance state rather than just multiple performance levels in the state power state. The current code would select the performance state rather than the 3D performance state when the "performance" profile was selected. This change switches to the "balanced" profile by default which ends up being the internal performance profile. When the user selects the "performance" profile, it selects the internal 3D performance state so the user can select the higher performance modes. For most asics this changes nothing. For certain rv770 asics with static performance and 3D performance states, this allows you to select between then using by selecting the "balanced" and "performance" dpm profiles. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05drm/radeon: set default clocks for SI when DPM is disabledAlex Deucher
Fix patching of vddc values for SI and enable manually forcing clocks to default levels as per NI. This improves the out of the box performance with SI asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03drm/radeon/sumo: implement support for disable_gfx_power_gating_in_uvd flagAlex Deucher
Some asic revisions need to disable PG when UVD is active. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03drm/radeon/tn: disable PG when changing UVD clocksAlex Deucher
Causes hangs for some people. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03drm/radeon/sumo: disable PG when changing UVD clocksAlex Deucher
Causes hangs for some people. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03drm/radeon/aruba: disable additional rlc featuresAlex Deucher
They cause problems with dynamic clocking. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03drm/radeon: fix endian bug in radeon_atom_get_mclk_range_table()Alex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-02drm/radeon/dpm: fix compilation with certain versions of gccMike Lothian
Add #include <linux/seq_file.h> to *_dpm.c files Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-02drm/radeon/dpm: clarify debugfs warningAlex Deucher
For chips without debugfs dpm support say that it's not implemented rather than not supported to avoid confusion about DPM support in general. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01drm/radeon/dpm: add debugfs support for SIAlex Deucher
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01drm/radeon/dpm: add debugfs support for caymanAlex Deucher
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01drm/radeon/dpm: add debugfs support for TNAlex Deucher
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01drm/radeon/dpm: add debugfs support for ON/LNAlex Deucher
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01drm/radeon/dpm: add debugfs support for 7xx/evergreen/btcAlex Deucher
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01drm/radeon/dpm: add debugfs support for rv6xxAlex Deucher
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01drm/radeon/dpm: add infrastructure to support debugfs infoAlex Deucher
This lays the frameworks to report realtime power level feedback. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01drm/radeon/dpm: re-enable state transitions for CaymanAlex Deucher
Was disabled due to stability issues on certain boards caused by the a bug in the parsing of the atom mc reg tables. That's fixed now so re-enable. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01drm/radeon/dpm: re-enable state transitions for BTCAlex Deucher
Was disabled due to stability issues on certain boards caused by the a bug in the parsing of the atom mc reg tables. That's fixed now so re-enable. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01drm/radeon: fix typo in radeon_atom_init_mc_reg_table()Alex Deucher
Bad pointer math. Fixes hangs in state transitions with BTC+ asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01drm/radeon/atom: fix endian bug in radeon_atom_init_mc_reg_table()Alex Deucher
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01drm/radeon: remove sumo dpm/uvd bringup leftoversAlex Deucher
Function doesn't do anything useful. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01Merge branch 'drm-nouveau-next' of ↵Dave Airlie
git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next - Various fixes that make surviving concurrent piglit more possible. - Buffer object deletion no longer synchronous - Context/register initialisation updates that have been reported to solve some stability issues (particularly on some problematic GF119 chips) - Kernel side support for VP2 video decoding engines * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (44 commits) drm/nvd0-/disp: handle case where display engine is missing/disabled drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4 drm/nouveau/bsp/nv84: initial vp2 engine implementation drm/nouveau/vp/nv84: initial vp2 engine implementation drm/nouveau/core: xtensa engine base class implementation drm/nouveau/vdec: fork vp3 implementations from vp2 drm/nouveau/core: move falcon class to engine/ drm/nouveau/kms: don't fail if there's no dcb table entries drm/nouveau: remove limit on gart drm/nouveau/vm: perform a bar flush when flushing vm drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switches drm/nvc8/gr: update initial register/context values drm/nvc4/gr: update initial register/context values drm/nvc1/gr: update initial register/context values drm/nvc3/gr: update initial register/context values drm/nvc0/gr: update initial register/context values drm/nvd9/gr: update initial register/context values drm/nve4/gr: update initial register/context values drm/nvc0-/gr: bump maximum gpc/tpc limits drm/nvf0/gr: initial register/context setup ...
2013-07-01drm/nvd0-/disp: handle case where display engine is missing/disabledMaarten Lankhorst
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4Ben Skeggs
No code changes, proven by envyas producing identical binaries. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/bsp/nv84: initial vp2 engine implementationIlia Mirkin
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/vp/nv84: initial vp2 engine implementationIlia Mirkin
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/core: xtensa engine base class implementationIlia Mirkin
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/vdec: fork vp3 implementations from vp2Ilia Mirkin
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/core: move falcon class to engine/Ben Skeggs
Not really "core" per-se. About to merge Ilia's work adding another similar class for the VP2 xtensa engines, so, seems like a good time to move all these to engine/. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/kms: don't fail if there's no dcb table entriesBen Skeggs
Fixes module not loading on Tesla K20. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau: remove limit on gartMaarten Lankhorst
Most graphics cards nowadays have a multiple of this limit as their vram, so limiting GART doesn't seem to make much sense. Signed-off-by: Maarten >Lnkhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nouveau/vm: perform a bar flush when flushing vmMaarten Lankhorst
Appears to fix the regression from "drm/nvc0/vm: handle bar tlb flushes internally". nvidia always seems to do this flush after writing values. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switchesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01drm/nvc8/gr: update initial register/context valuesBen Skeggs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
generated by cgit v0.10.2 at 2024-11-09 19:49:04 (GMT)