| Age | Commit message (Collapse) | Author |
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In case of interrupt arrive immediately after requesting irq,
kernel will panic due to uninitialized variable.
Fix below exception:
Unable to handle kernel NULL pointer dereference
at virtual address 00000000
pgd = 80003000
[00000000] *pgd=80000080004003, *pmd=00000000
Internal error: Oops: 206 [#1] SMP THUMB2
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.12.19-rt30+ #138
task: ef07c000 ti: ef080000 task.ti: ef080000
PC is at __swait_wake_locked+0x10/0x4e
LR is at complete+0x21/0x2e
pc : [<8002ee4a>] lr : [<8002f2bb>] psr: 400001b3
sp : ef081d00 ip : 0000001f fp : ef080000
r10: 00000001 r9 : 00000000 r8 : 00000003
r7 : ef0329ac r6 : 80000193 r5 : 00000000 r4 : ef0329ac
r3 : 00000000 r2 : 00000001 r1 : 00000003 r0 : ef0329ac
Flags: nZcv IRQs off FIQs on Mode SVC_32 ISA Thumb Segment kernel
Control: 70c53c7d Table: 80003000 DAC: 02851004
Process swapper/0 (pid: 1, stack limit = 0xef080248)
Stack: (0xef081d00 to 0xef082000)
1d00: ef0329ac ef0329a8 80000193 ef081d20
00000000 00000000 804c252c 8002f2bb
1d20: 80000000 804d6a13 ef3cc2c0 ef011c00
000000a3 801c3c1d 801c3bdb 8003b8b7
1d40: ef011c00 ef3cc2c0 802e1ed0 00000000
ef011c00 8049cd7c 00000000 ef081de4
1d60: 803f6b32 815115d0 804c252c 8003b9b9
00000000 ef011c00 8049cd7c 8003d5cf
1d80: 000000a3 8003b3fb 000000a3 8000ca3d
f0002000 ef081db0 804a8c8c 800083df
1da0: 802e1ed0 00000133 ffffffff 802e245b
804fd8fc 60000113 00000066 00001dc5
1dc0: 804fd8fc 60000113 00000000 00000000
803f6b32 815115d0 804c252c ef080000
1de0: 0000001f ef081df8 8023cb13 802e1ed0
00000133 ffffffff ef032010 ef005e10
1e00: ef005e00 00000000 00000000 8023cb23
f02c0000 801c4123 00000000 ef111280
1e20: ef032010 ef3caf40 ef3caf40 800b44ff
ef07c000 00000000 ef3caf40 ef111300
1e40: ef269f80 800b4b37 804c256c 8023cce7
ef063684 00000003 ef111300 00000000
1e60: 804fbbd4 ef005e10 00000000 ef005e10
ef005e44 804fbbd4 804c2364 80482039
1e80: 000000ad 00000000 ef080000 80198371
ef005e10 ef005e44 804c2364 00000000
1ea0: 80482039 801984a5 00000000 804c2364
80198471 8019742d ef06365c ef110434
1ec0: 804c2364 804bfb30 ef269f80 80197e3b
803f6bae 803f6bb3 00000071 804c2364
1ee0: 80490ad0 8049b374 804d6d40 8019882d
00000000 00000006 80490ad0 800085f5
1f00: ef105300 ef105580 00000000 ef105580
802ea500 803d4d54 00000000 800aeae1
1f20: 804ae908 00000113 80471461 815188d2
815188da 80028f35 00000000 80447320
1f40: 00000000 000000ad 00000006 00000006
00000001 00000006 80490ad0 8049b374
1f60: 804d6d40 804d6d40 000000ad 80490adc
00000000 8047192d 00000006 00000006
1f80: 80471461 00000000 00000000 802db775
00000000 00000000 00000000 00000000
1fa0: 00000000 802db77b 00000000 8000c219
00000000 00000000 00000000 00000000
1fc0: 00000000 00000000 00000000 00000000
00000000 00000000 00000000 00000000
1fe0: 00000000 00000000 00000000 00000000
00000013 00000000 deadbeef deadbeef
[<8002ee4a>] (__swait_wake_locked+0x10/0x4e)
from [<8002f2bb>] (complete+0x21/0x2e)
[<8002f2bb>] (complete+0x21/0x2e)
from [<801c3c1d>] (fsl_qspi_irq_handler+0x43/0x46)
[<801c3c1d>] (fsl_qspi_irq_handler+0x43/0x46)
from [<8003b8b7>] (handle_irq_event_percpu+0x33/0x104)
[<8003b8b7>] (handle_irq_event_percpu+0x33/0x104)
from [<8003b9b9>] (handle_irq_event+0x31/0x48)
[<8003b9b9>] (handle_irq_event+0x31/0x48)
from [<8003d5cf>] (handle_fasteoi_irq+0x6b/0xa4)
[<8003d5cf>] (handle_fasteoi_irq+0x6b/0xa4)
from [<8003b3fb>] (generic_handle_irq+0x13/0x1c)
[<8003b3fb>] (generic_handle_irq+0x13/0x1c)
from [<8000ca3d>] (handle_IRQ+0x3d/0x60)
[<8000ca3d>] (handle_IRQ+0x3d/0x60)
from [<800083df>] (gic_handle_irq+0x2b/0x44)
[<800083df>] (gic_handle_irq+0x2b/0x44)
from [<802e245b>] (__irq_svc+0x3b/0x5c)
Exception stack(0xef081db0 to 0xef081df8)
1da0: 804fd8fc 60000113 00000066 00001dc5
1dc0: 804fd8fc 60000113 00000000 00000000
803f6b32 815115d0 804c252c ef080000
1de0: 0000001f ef081df8 8023cb13 802e1ed0 00000133 ffffffff
[<802e245b>] (__irq_svc+0x3b/0x5c)
from [<802e1ed0>] (_raw_spin_unlock_irqrestore+0x16/0x18)
[<802e1ed0>] (_raw_spin_unlock_irqrestore+0x16/0x18)
from [<8023cb13>] (of_find_property+0x29/0x32)
[<8023cb13>] (of_find_property+0x29/0x32)
from [<8023cb23>] (of_get_property+0x7/0xc)
[<8023cb23>] (of_get_property+0x7/0xc)
from [<801c4123>] (fsl_qspi_probe+0x197/0x5b0)
[<801c4123>] (fsl_qspi_probe+0x197/0x5b0)
from [<80198371>] (driver_probe_device+0x65/0x140)
[<80198371>] (driver_probe_device+0x65/0x140)
from [<801984a5>] (__driver_attach+0x35/0x48)
[<801984a5>] (__driver_attach+0x35/0x48)
from [<8019742d>] (bus_for_each_dev+0x3b/0x46)
[<8019742d>] (bus_for_each_dev+0x3b/0x46)
from [<80197e3b>] (bus_add_driver+0x8b/0x164)
[<80197e3b>] (bus_add_driver+0x8b/0x164)
from [<8019882d>] (driver_register+0x4b/0x76)
[<8019882d>] (driver_register+0x4b/0x76)
from [<800085f5>] (do_one_initcall+0x65/0xd4)
[<800085f5>] (do_one_initcall+0x65/0xd4)
from [<8047192d>] (kernel_init_freeable+0xbd/0x150)
[<8047192d>] (kernel_init_freeable+0xbd/0x150)
from [<802db77b>] (kernel_init+0x7/0x90)
[<802db77b>] (kernel_init+0x7/0x90)
from [<8000c219>] (ret_from_fork+0x11/0x38)
Code: 4607 4688 4692 46a9 (681e) 1f1c
---[ end trace 2857aa3b399c215c ]---
Kernel panic - not syncing: Fatal exception in interrupt
CPU1: stopping
CPU: 1 PID: 0 Comm: swapper/1 Tainted: G D 3.12.19-rt30+ #138
[<80010829>] (unwind_backtrace+0x1/0x88)
from [<8000e53b>] (show_stack+0xb/0xc)
[<8000e53b>] (show_stack+0xb/0xc)
from [<802df461>] (dump_stack+0x4d/0x60)
[<802df461>] (dump_stack+0x4d/0x60)
from [<8000ff23>] (handle_IPI+0x7f/0xd0)
[<8000ff23>] (handle_IPI+0x7f/0xd0)
from [<800083ef>] (gic_handle_irq+0x3b/0x44)
[<800083ef>] (gic_handle_irq+0x3b/0x44)
from [<802e245b>] (__irq_svc+0x3b/0x5c)
Exception stack(0xef09bfa0 to 0xef09bfe8)
bfa0: ffffffed 00000000 01087000 00000000
ef09a000 ef09a010 80000000 804d7054
bfc0: 80003010 410fc075 00000000 00000000
00000008 ef09bfe8 8000cc21 8000cc22
bfe0: 60000133 ffffffff
[<802e245b>] (__irq_svc+0x3b/0x5c)
from [<8000cc22>] (arch_cpu_idle+0x1a/0x20)
[<8000cc22>] (arch_cpu_idle+0x1a/0x20)
from [<8003b395>] (cpu_startup_entry+0x7d/0xc4)
[<8003b395>] (cpu_startup_entry+0x7d/0xc4)
from [<80008485>] (__enable_mmu+0x1/0x1c)
Signed-off-by: Haikun Wang <b53464@freescale.com>
Change-Id: If47a75274ae794a504cee0fca02920c9af1a29c1
Reviewed-on: http://git.am.freescale.net:8181/30121
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Huan Wang <alison.wang@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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For the QuadSPI SPI NOR flash driver, quad reading is used. This patch will
add quad reading support for ST's flash n25q128a13 on LS1021A TWR board.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Change-Id: Icf3c1334825fb9a0fe957bc6b75fa4dfd54c6960
Reviewed-on: http://git.am.freescale.net:8181/24670
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Some new Micron SPI N25Q512 chips require reading the flag
status register to determine when operations have completed.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Change-Id: I52a87e1ae55da75248108d6db39f027318bacf22
Reviewed-on: http://git.am.freescale.net:8181/22632
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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FSL Quadspi module register bitwise is big-endian, but on ohter paltform
is little endian.
Add functions for Quadspi register read/write for bitwise:
qspi_readl
qpsi_writel
Add devtype for LS1021:
struct fsl_qspi_devtype_data ls1_data
Signed-off-by: Chao Fu <B44548@freescale.com>
The upstream status of this patch can be found at: http://patchwork.ozlabs.org/patch/399388/
Change-Id: Ib1a8bc11a52e8d9bb1021c8956a5783d3915de2e
Reviewed-on: http://git.am.freescale.net:8181/20296
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Li Xiubo <Li.Xiubo@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Currently, we read 5 bytes for ID, but s25fl128s has the same ext_id(0x4d01)
with s25fl129p1. The s25fl128s can support the DDR Quad read, while s25fl129p1
does not. So we have to distinguish the two NOR flashs.
This patch reads out 6 bytes for the ID, and use the 6 bytes ID to search the
right flash_info.
The detail of the patch is:
[1] change the "ext_id" from u16 to u32.
We can store two bytes or three bytes with the @ext_id now.
[2] search the right flash_info with the 6byte ID and the new @ext_id.
We use "matched" variable to track the legacy two bytes @ext_id.
If the flash_info's @ext_id is three bytes, we will use the
sixth byte of the ID to check it.
[3] add the new item to spi_nor_ids for s25fl128s.
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream link of this patch: http://patchwork.ozlabs.org/patch/353244/
Change-Id: Id27774eefbf9e1a8f80e1dcd8fb0d3f9363923c1
Reviewed-on: http://git.am.freescale.net:8181/20134
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add DDR quad read opcode and LUT sequence for Micron N25Q256A.
The performace :
=================================================
mtd_speedtest: MTD device: 1
mtd_speedtest: not NAND flash, assume page size is 512 bytes.
mtd_speedtest: MTD device size 33554432, eraseblock size 65536,
page size 512, count of eraseblocks 512, pages per eraseblock 128, OOB size 0
mtd_speedtest: testing eraseblock write speed
mtd_speedtest: eraseblock write speed is 2426 KiB/s
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 32157 KiB/s
mtd_speedtest: testing page write speed
mtd_speedtest: page write speed is 2362 KiB/s
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 17741 KiB/s
mtd_speedtest: testing 2 page write speed
mtd_speedtest: 2 page write speed is 2384 KiB/s
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 24058 KiB/s
mtd_speedtest: Testing erase speed
mtd_speedtest: erase speed is 1927529 KiB/s
mtd_speedtest: Testing 2x multi-block erase speed
mtd_speedtest: 2x multi-block erase speed is 2184533 KiB/s
mtd_speedtest: Testing 4x multi-block erase speed
mtd_speedtest: 4x multi-block erase speed is 2184533 KiB/s
mtd_speedtest: Testing 8x multi-block erase speed
mtd_speedtest: 8x multi-block erase speed is 2340571 KiB/s
mtd_speedtest: Testing 16x multi-block erase speed
mtd_speedtest: 16x multi-block erase speed is 2340571 KiB/s
mtd_speedtest: Testing 32x multi-block erase speed
mtd_speedtest: 32x multi-block erase speed is 2340571 KiB/s
mtd_speedtest: Testing 64x multi-block erase speed
mtd_speedtest: 64x multi-block erase speed is 2340571 KiB/s
mtd_speedtest: finished
=================================================
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream link of this patch: https://patchwork.kernel.org/patch/4075001/
Change-Id: Ice094cec23114af5cda5dd4b24c3b2e60719fd6a
Reviewed-on: http://git.am.freescale.net:8181/20132
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch adds the DDR(or DTR) quad read support for the Micron
SPI NOR flash.
Tested with n25q256a.
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream link of this patch: https://patchwork.kernel.org/patch/4075011/
Change-Id: Ib226886ff8d9e80d6aa5fb72dc86278188b2e3a3
Reviewed-on: http://git.am.freescale.net:8181/20131
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add the DDR quad read support for the fsl-quadspi driver.
Check the "spi-nor,ddr-quad-read-dummy" DT property, if the DT node is exit,
it means we could enable the DDR quad read.
(1) Test this patch with imx6sx-sdb board (Spansion s25fl128s)
The clock rate is 66MHz.
(2) The information of NOR flash:
-----------------------------------------------
root@imx6qdlsolo:~# mtdinfo /dev/mtd0
mtd0
Name: 21e4000.qspi
Type: nor
Eraseblock size: 65536 bytes, 64.0 KiB
Amount of eraseblocks: 256 (16777216 bytes, 16.0 MiB)
Minimum input/output unit size: 1 byte
Sub-page size: 1 byte
Character device major/minor: 90:0
Bad blocks are allowed: false
Device is writable: true
-----------------------------------------------
(3) Test this patch set with UBIFS & bonnie++:
-----------------------------------------------
ubiattach /dev/ubi_ctrl -m 0
ubimkvol /dev/ubi0 -N test -m
mount -t ubifs ubi0:test tmp
bonnie++ -d tmp -u 0 -s 10 -r 5
-----------------------------------------------
(4) Test this patch with mtd_speedtest.ko
root@imx6qdlsolo:~# insmod mtd_speedtest.ko dev=0
=================================================
mtd_speedtest: MTD device: 0
mtd_speedtest: not NAND flash, assume page size is 512 bytes.
mtd_speedtest: MTD device size 16777216, eraseblock size 65536, page size 512,
count of eraseblocks 256, pages per eraseblock 128, OOB size 0
mtd_speedtest: testing eraseblock write speed
mtd_speedtest: eraseblock write speed is 665 KiB/s
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 49799 KiB/s
mtd_speedtest: testing page write speed
mtd_speedtest: page write speed is 662 KiB/s
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 24236 KiB/s
mtd_speedtest: testing 2 page write speed
mtd_speedtest: 2 page write speed is 657 KiB/s
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 32637 KiB/s
mtd_speedtest: Testing erase speed
mtd_speedtest: erase speed is 518 KiB/s
mtd_speedtest: Testing 2x multi-block erase speed
mtd_speedtest: 2x multi-block erase speed is 506 KiB/s
mtd_speedtest: Testing 4x multi-block erase speed
mtd_speedtest: 4x multi-block erase speed is 503 KiB/s
mtd_speedtest: Testing 8x multi-block erase speed
mtd_speedtest: 8x multi-block erase speed is 501 KiB/s
mtd_speedtest: Testing 16x multi-block erase speed
mtd_speedtest: 16x multi-block erase speed is 498 KiB/s
mtd_speedtest: Testing 32x multi-block erase speed
mtd_speedtest: 32x multi-block erase speed is 496 KiB/s
mtd_speedtest: Testing 64x multi-block erase speed
mtd_speedtest: 64x multi-block erase speed is 495 KiB/s
mtd_speedtest: finished
=================================================
(5) Conclusion:
The DDR quad read could be 49799 KiB/s.
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream status of this patch can be found at: https://patchwork.kernel.org/patch/4074991/
Change-Id: I80c58bec32659d375c4656402e0c3d3ce3ba2e55
Reviewed-on: http://git.am.freescale.net:8181/20130
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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We can get the read/write/erase opcode from the spi nor framework now.
What's more is that we can get the correct dummy cycles.
This patch uses the information stored in the spi_nor{} to remove the
hardcode in the fsl_qspi_init_lut().
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream status of this patch can be found: https://patchwork.kernel.org/patch/4074971/
Change-Id: I32f982872df1729582f4122ac0dede934d749a04
Reviewed-on: http://git.am.freescale.net:8181/20129
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch adds the DDR quad read support by the following:
[1] add SPI_NOR_DDR_QUAD read mode.
[2] add DDR Quad read opcodes:
SPINOR_OP_READ_1_4_4_D / SPINOR_OP_READ4_1_4_4_D
[3] add set_ddr_quad_mode() to initialize for the DDR quad read.
Currently it only works for Spansion NOR.
[3] about the dummy cycles.
We set the dummy with 8 for DDR quad read by default.
The m25p80.c can not support the DDR quad read, but the SPI NOR controller
can set the dummy value in its child DT node, and the SPI NOR framework
can parse it out.
Test this patch for Spansion s25fl128s NOR flash.
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream status of this patch can be found at: https://patchwork.kernel.org/patch/4074961
Change-Id: Id67e247e357bdd8bea99816e31f603898671d968
Reviewed-on: http://git.am.freescale.net:8181/20125
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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serial_flash_cmds.h defines our opcodes a little differently. Let's
borrow its naming, since it's borrowed from the SFDP standard, and it's
more extensible.
This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode
listing.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Huang Shijie <b32955@freescale.com>
(cherry picked from commit 58b89a1f4c2a65b10b8f7b90b6ff2161b19bb0d1)
Change-Id: Id3eff06b36acaa388d2581af59abc569c6a7f474
Reviewed-on: http://git.am.freescale.net:8181/20058
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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For the DDR Quad read, the dummy cycles maybe 3 or 6 which is less then 8.
The dummy cycles is actually 8 for SPI fast/dual/quad read.
This patch makes preparations for the DDR quad read, it fixes the wrong dummy
value for both the spi-nor.c and m25p80.c.
Signed-off-by: Huang Shijie <b32955@freescale.com>
The upstream status of this patch can be found at: https://patchwork.kernel.org/patch/4074921/
Change-Id: I7ca208d1964812f77f66708c659d826c39baff4d
Reviewed-on: http://git.am.freescale.net:8181/20056
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Qualify these with a better namespace, and prepare them for use in more
drivers.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Huang Shijie <b32955@freescale.com>
(cherry picked from commit b02e7f3ef0beb72da8fc64542f0ac977996ec56b)
Change-Id: I50fac2cb23653825b2f8e3ac65dd0ecb35eaf78b
Reviewed-on: http://git.am.freescale.net:8181/20054
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add the copyright information for spi-nor.c and spi-nor.h.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Change-Id: Idde8bf06ec19e581234865b700207ee60e953755
Reviewed-on: http://git.am.freescale.net:8181/15511
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Fix errors like this:
ERROR: "spi_nor_ids" [drivers/mtd/devices/m25p80.ko] undefined!
ERROR: "spi_nor_scan" [drivers/mtd/devices/m25p80.ko] undefined!
make[1]: *** [__modpost] Error 1
make: *** [modules] Error 2
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Change-Id: I61a5d463500e2646dbb10dbab543550bf1ef009e
Reviewed-on: http://git.am.freescale.net:8181/15510
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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(0) What is the QuadSPI controller?
The QuadSPI(Quad Serial Peripheral Interface) acts as an interface to
one single or two external serial flash devices, each with up to 4
bidirectional data lines.
(1) The QuadSPI controller is driven by the LUT(Look-up Table) registers.
The LUT registers are a look-up-table for sequences of instructions.
A valid sequence consists of four LUT registers.
(2) The definition of the LUT register shows below:
---------------------------------------------------
| INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
---------------------------------------------------
There are several types of INSTRx, such as:
CMD : the SPI NOR command.
ADDR : the address for the SPI NOR command.
DUMMY : the dummy cycles needed by the SPI NOR command.
....
There are several types of PADx, such as:
PAD1 : use a singe I/O line.
PAD2 : use two I/O lines.
PAD4 : use quad I/O lines.
....
(3) Test this driver with the JFFS2 and UBIFS:
For jffs2:
-------------
#flash_eraseall /dev/mtd0
#mount -t jffs2 /dev/mtdblock0 tmp
#bonnie++ -d tmp -u 0 -s 10 -r 5
For ubifs:
-------------
#flash_eraseall /dev/mtd0
#ubiattach /dev/ubi_ctrl -m 0
#ubimkvol /dev/ubi0 -N test -m
#mount -t ubifs ubi0:test tmp
#bonnie++ -d tmp -u 0 -s 10 -r 5
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Change-Id: Ie32163e49eb62af82bf311e9165363a2f8880841
Reviewed-on: http://git.am.freescale.net:8181/15509
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add the spi_nor_match_id() to find the proper spi_device_id with the
NOR flash's name in the spi_nor_ids table.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Change-Id: I471348a87ccde741055745d14cd25c84b480a803
Reviewed-on: http://git.am.freescale.net:8181/15508
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch cloned most of the m25p80.c. In theory, it adds a new spi-nor layer.
Before this patch, the layer is like:
MTD
------------------------
m25p80
------------------------
spi bus driver
------------------------
SPI NOR chip
After this patch, the layer is like:
MTD
------------------------
spi-nor
------------------------
m25p80
------------------------
spi bus driver
------------------------
SPI NOR chip
With the spi-nor controller driver(Freescale Quadspi), it looks like:
MTD
------------------------
spi-nor
------------------------
fsl-quadspi
------------------------
SPI NOR chip
New APIs:
spi_nor_scan: used to scan a spi-nor flash.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
[Brian: rebased to include additional m25p_ids[] entry]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Change-Id: I7c22c4c83350eac8c325ccd8292450fde79bb069
Reviewed-on: http://git.am.freescale.net:8181/15507
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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