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This reverts commit 5e921ed07acbc6f05536aac89b9edc2578663840.
Change-Id: Ic4d1166b5ad6419f369e3be278f41ea5764ff6fc
Reviewed-on: http://git.am.freescale.net:8181/23784
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
Tested-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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Change-Id: I428d24ec05b1e6ef2137ad2ba6385ddfa3a01872
Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/22882
Reviewed-by: Nir Erez <nir.erez@freescale.com>
Reviewed-by: Matthew Weigel <Matthew.Weigel@freescale.com>
Tested-by: Matthew Weigel <Matthew.Weigel@freescale.com>
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- add CONFIG_FMAN_V3L by default for FMan_V3L platform.
- t1024 officially supports 6 portals of QMan/BMan instead of 10
- remove CONFIG_ALTIVEC as e5500 core has no ALTIVEC.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Change-Id: I71a5426ad441ef034c66e2d794a86b366092530d
Reviewed-on: http://git.am.freescale.net:8181/23188
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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Support PTPd 1588 stack by adding PTP 1588 clock
using the dTSEC
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Change-Id: I4f6fb9a721cede75c6cf23560014b55b46c84fef
Reviewed-on: http://git.am.freescale.net:8181/20295
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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The hardware can automatically generate pause frames when the number
of free buffers drops under a certain threshold, but in order to do this,
the address of the last free buffer needs to be written to a specific
register for each RX queue.
This has to be done in 'gfar_clean_rx_ring' which is called for each
RX queue. In order not to impact performance, by adding a register write
for each incoming packet, this operation is done only when the PAUSE frame
transmission is enabled.
Whenever the link is readjusted, this capability is turned on or off.
Change-Id Ib4751d205a00c0813355cf23c4428bf6dcbda003
Signed-off-by: Matei Pavaluca <matei.pavaluca@freescale.com>
Change-Id: I22a836b86f256128ea1bd39e87902321030f7742
Reviewed-on: http://git.am.freescale.net:8181/23138
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
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Local flow control options needed in order to resolve the negotiation
are incorrectly calculated.
Previously 'mii_advertise_flowctrl' was called to determine the local advertising
options, but these were determined based on FLOW_CTRL_RX/TX flags which are
never set through ethtool.
The patch simply translates from ethtool flow options to mii flow options.
Change-Id: I3ed7801eecaa6b5b8501ba1c8e860c92f959d559
Signed-off-by: Pavaluca Matei <matei.pavaluca@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/23137
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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The phy device supports 802.3x flow control, but the specific flags are not set
in the phy initialisation code. Flow control flags need to be added to the
supported capabilities of the phydev by the driver.
This is needed in order for ethtool to work ('ethtool -A' code checks for these
flags)
Change-Id: I71d8411a82777aff36bf98a09097eef1935ff113
Signed-off-by: Pavaluca Matei <matei.pavaluca@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/23136
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
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mpc85xx_pmc_set_wake() is only for powerpc platform. For LS1 platform,
no such function. Use a weak function definition to void compile
problem.
Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
Change-Id: I84ab02a65addabd2f8d7a9681e5f80c7b06c5ad0
Reviewed-on: http://git.am.freescale.net:8181/22821
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Yang Li <LeoLi@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Add the GFAR_DBG_LOOP config option and debugfs support
to be able to configure packet forwarding loops in the
Gianfar driver. This config option is disabled by default
and should be used only for debugging/ benchmarking
purposes.
For details on how to configure a packet forwarding debug
loop refer to the help section of CONFIG_GFAR_DBG_LOOP.
Change-Id: I24d440edc4c7d63a055205e022b743e30f58409b
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Reviewed-on: http://git.am.freescale.net:8181/22861
Reviewed-by: Richard Schmitt <richard.schmitt@freescale.com>
Tested-by: Richard Schmitt <richard.schmitt@freescale.com>
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Merge remote-tracking branch 't1024-linux/master'
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DPA Shared Ethernet has no plan to support NAPI so
far, so setup a dummy net device for NAPI.
Signed-off-by: Pan Jiafei <Jiafei.Pan@freescale.com>
Change-Id: I2cdd19c0aa7cfe64a0a7fb4f1397b5a0e24cc5f6
Reviewed-on: http://git.am.freescale.net:8181/21951
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jianhua Xie <jianhua.xie@freescale.com>
Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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Fqs back to outbound OP must have a higher priority compared
to fqs from core to outbound OP, otherwise the buffer will
be exhausted.
Signed-off-by: Pan Jiafei <Jiafei.Pan@freescale.com>
Change-Id: Ia4de53493d06768f86c617340927e2af4d722011
Reviewed-on: http://git.am.freescale.net:8181/21442
Reviewed-by: Jianhua Xie <jianhua.xie@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Tested-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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This can avoid buffer pool is exhausted by others,
so that it can avoid deadlock for outbound OP.
Signed-off-by: Pan Jiafei <Jiafei.Pan@freescale.com>
Change-Id: I6fd1a604e0ae004837e02a4ac925360967da9827
Reviewed-on: http://git.am.freescale.net:8181/21441
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jianhua Xie <jianhua.xie@freescale.com>
Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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It maybe a hw bug.
Signed-off-by: Pan Jiafei <Jiafei.Pan@freescale.com>
Change-Id: I7f328e7f325e886ee1e1c2bd468117b1b043dd9a
Reviewed-on: http://git.am.freescale.net:8181/21440
Reviewed-by: Jianhua Xie <jianhua.xie@freescale.com>
Tested-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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Signed-off-by: Pan Jiafei <Jiafei.Pan@freescale.com>
Change-Id: Ifcd657229e3cbc9eab88866ac4a05230321a6a6d
Reviewed-on: http://git.am.freescale.net:8181/21439
Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
Tested-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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CAPWAP stands for Control and Provisioning of Wireless Access Points.
CAPWAP is a standard, interoperable protocol that enables a controller
to manage a collection of wireless access points.
There are three drivers in Kernel Space: CAPWAP Domain driver,
CAPWAP Bridge driver and CAPWAP Tunnel driver.
CAPWAP Domain Driver implements configuration for CAPWAP Domain,
including PCD configuration and FQs setup. User must configure and
initialize CAPWAP domain before CAPWAP Tunnel and CAPWAP Bridge works.
CAPWAP Tunnel Driver is a misc device driver, which registers four
misc devices for four CAPWAP tunnels:
fsl-capwap-ctrl-dtls,
fsl-capwap-ctl-n-dtls,
fsl-capwap-data-dtls,
fsl-capwap-data-n-dtls.
The misc device provides file-operation to transmit/receive DTLS/non-DTLS
packets. For example, read from the device fsl-capwap-ctrl-dtls can receive
DTLS control packet; Write to the device fsl-capwap-ctrl-dtls can transmit
DTLS control packet.
The CAPWAP Bridge Driver is also a misc device driver; it can bridge packets
between PCIe NIC and CAPWAP data tunnels.
To support capwap drivers, there should be a shared ethernet port in dts file
to use as CAPWAP Ethernet port.
Signed-off-by: Pan Jiafei <Jiafei.Pan@freescale.com>
Change-Id: I7c99191156ebee5dd43673d20fb5c8469a780546
Reviewed-on: http://git.am.freescale.net:8181/21438
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Jianhua Xie <jianhua.xie@freescale.com>
Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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Signed-off-by: Pan Jiafei <Jiafei.Pan@freescale.com>
Change-Id: I98b45ed877ab65e5ce2cd673787a7657e5faacbc
Reviewed-on: http://git.am.freescale.net:8181/21437
Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
Tested-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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Signed-off-by: Pan Jiafei <Jiafei.Pan@freescale.com>
Change-Id: Ia7c5b214817804e6e1ee31d74608ffbacd09cf39
Reviewed-on: http://git.am.freescale.net:8181/21433
Reviewed-by: Mandy Lavi <Mandy.Lavi@freescale.com>
Tested-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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Signed-off-by: Mandy Lavi <mandy.lavi@freescale.com>
Change-Id: I426f384c05479a5ddc1607e9b8fa92d972c612ce
Reviewed-on: http://git.am.freescale.net:8181/21432
Reviewed-by: Jiafei Pan <Jiafei.Pan@freescale.com>
Reviewed-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Tested-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
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The same hang issue was observed on T1024 as well.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Change-Id: Ifad3fff1b430be90b6cc9548a959365ecd28236d
Reviewed-on: http://git.am.freescale.net:8181/21425
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Xiaobo Xie <X.Xie@freescale.com>
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ERR005829 handling
This patch adds support for non RX-FIFO (legacy) mode and conditional ERRATA
ERR005829 handling in flexcan driver.
Both these features are now selectable via Kconfig entries and hence can
be turned-on/off as per a SoC feature set availability.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Change-Id: I2a5a4970b7e5b18a45fb421f1c0d008ad5a3b0f8
Reviewed-on: http://git.am.freescale.net:8181/21856
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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The FlexCAN IP on certain SoCs like (Freescale's LS1021A) is modelled in
a big-endian fashion, i.e. the registers and the message buffers are
organized in a BE way.
More details about the LS1021A SoC can be seen here:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=LS1021A&nodeId=018rH325E4017B#
This patch ensures that the register read/write APIs are remodelled to
address such cases, while ensuring that existing platforms (where the
FlexCAN IP was modelled in LE way) do not break.
Tested on LS1021A-QDS board.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Change-Id: Ibaa6b1816670537466b227b5032be73338435c03
Reviewed-on: http://git.am.freescale.net:8181/21854
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch adds ls1021a flexcan device entry to the flexcan driver code.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
---
Previous version of this patch under review upstream:
http://patchwork.ozlabs.org/patch/363588/
Change-Id: Ie01ec4583e1dc4efd90eb05e69ed45ae351d9d4e
Reviewed-on: http://git.am.freescale.net:8181/21853
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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supported in 3.12 kernel
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Change-Id: I731e457b0b29a794c752116921b119c37514758a
Reviewed-on: http://git.am.freescale.net:8181/21852
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch increases the mask in the FLEXCAN_MCR_MAXMB() to 7 bits as in the
newer flexcan cores the MAXMB field is 7 bits wide.
Reported-by: David Jander <david@protonic.nl>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
Cherry-picked from linux-next: 4c728d804c4b9d1ae7f76e8f32c419bc21a6e540
Change-Id: If7f3817dced00e4864da29579ff377788e9ee4ad
Reviewed-on: http://git.am.freescale.net:8181/21851
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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After sending a RTR frame the TX mailbox becomes a RX_EMPTY mailbox. To avoid
side effects when the RX-FIFO is full, this patch puts the TX mailbox into
TX_INACTIVE mode in the transmission complete interrupt handler. This, of
course, leaves a race window between the actual completion of the transmission
and the handling of tx-complete interrupt. However this is the best we can do
without busy polling the tx complete interrupt.
Cc: linux-stable <stable@vger.kernel.org>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
Cherry-picked from linux-next: de5944883ebbedbf5adc8497659772f5da7b7d72
Change-Id: Icfa9443f03246feee26868b9ad17147b2352c9fd
Reviewed-on: http://git.am.freescale.net:8181/21850
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch implements the workaround mentioned in ERR005829:
ERR005829: FlexCAN: FlexCAN does not transmit a message that is enabled to
be transmitted in a specific moment during the arbitration process.
Workaround: The workaround consists of two extra steps after setting up a
message for transmission:
Step 8: Reserve the first valid mailbox as an inactive mailbox (CODE=0b1000).
If RX FIFO is disabled, this mailbox must be message buffer 0. Otherwise, the
first valid mailbox can be found using the "RX FIFO filters" table in the
FlexCAN chapter of the chip reference manual.
Step 9: Write twice INACTIVE code (0b1000) into the first valid mailbox.
Signed-off-by: David Jander <david@protonic.nl>
Cc: linux-stable <stable@vger.kernel.org>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
Cherry-picked from linux-next: 25e924450fcb23c11c07c95ea8964dd9f174652e
Change-Id: I504198f3b5aaba2c0277b596e925ce3bb17a2258
Reviewed-on: http://git.am.freescale.net:8181/21849
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Apparently mailboxes may contain random data at startup, causing some of
them being prepared for message reception. This causes overruns being missed
or even confusing the IRQ check for trasmitted messages, increasing the transmit
counter instead of the error counter.
This patch initializes all mailboxes after the FIFO as RX_INACTIVE.
Signed-off-by: David Jander <david@protonic.nl>
Cc: linux-stable <stable@vger.kernel.org>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
Cherry-picked from linux-next: fc05b884a31dbf259cc73cc856e634ec3acbebb6
Change-Id: I0757258cb27cb2dec26e8afa219b512bba80be4b
Reviewed-on: http://git.am.freescale.net:8181/21848
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch fixes the initialization of the TX mailbox. It is now correctly
initialized as TX_INACTIVE not RX_EMPTY.
Cc: linux-stable <stable@vger.kernel.org>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
Cherry-picked from linux-next: c32fe4ad3e4861b2bfa1f44114c564935a123dda
Change-Id: I3058828c8f0786726589a8fc05a5cc8467644e1b
Reviewed-on: http://git.am.freescale.net:8181/21847
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Apparently can_restart() runs from a (timer-) interrupt and can call
flexcan_chip_[en|dis]able(), so avoid using usleep_range()
Signed-off-by: David Jander <david@protonic.nl>
Cc: linux-stable <stable@vger.kernel.org>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
Cherry-picked from linux-next: 8badd65e48c90d66587359d5329c2813088c0f50
Change-Id: I44fef82e8b413d6751a23fcb05d4a9f39ecb385a
Reviewed-on: http://git.am.freescale.net:8181/21846
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Once the CAN-bus is open and a packet is sent, the controller switches
into the PASSIVE state. Once the BUS is closed again it goes the back
err-warning. The TX error counter goes 0 -> 0x80 -> 0x7f.
This patch makes sure that the user learns about this state chang
(CAN_STATE_ERROR_WARNING => CAN_STATE_ERROR_PASSIVE)
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Matthias Klein <matthias.klein@optimeas.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
Cherry-picked from linux-next: 8ce261d0bb491da957278cdcba207791f329d1da
Change-Id: I311a7075033b493ef06818fb1e15f0eb69e96fa2
Reviewed-on: http://git.am.freescale.net:8181/21845
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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In case we don't have FLEXCAN_HAS_BROKEN_ERR_STATE and the user set
CAN_CTRLMODE_BERR_REPORTING once it can not be unset again until reboot.
So in case neither hardware nor user wants the error interrupt disable
the bit.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
Cherry-picked from linux-next: bc03a54139baafcd8fe89ad115411c2c9c8a4905
Change-Id: Ieb52a8f0cc761a37faf4556284bf2c922c6bec79
Reviewed-on: http://git.am.freescale.net:8181/21844
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Extend FlexCAN driver to support Vybrid. Vybrids variant of the IP
has ECC support which is controlled through the memory error
control register (MECR). There is also an errata which leads to
false positive error detections (ID e5295). This patch disables
the memory error detection completely.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
Cherry-picked from linux-next: cdce844865bea6869b34bacc98af3711774f5bb5
Change-Id: I296ab822a5e2ed6e28b98e348d690eab8ec165ac
Reviewed-on: http://git.am.freescale.net:8181/21843
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Tested-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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ecr register
The funcion flexcan_get_berr_counter() may be called from userspace even if the
interface is down, this the clocks are disabled. This patch switches on the
clocks before accessing the ecr register.
Reported-by: Ashutosh Singh <ashuleapyear@gmail.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
Cherry-picked from linux-next: ec56acfef2af184ca485ffeba16adbd56c110c94
Change-Id: I53ead04b0d5ae7c995809c51aef57acaedd3c3f4
Reviewed-on: http://git.am.freescale.net:8181/21842
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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CAN interfaces only support MTU values of 16 (CAN 2.0) and 72 (CAN FD).
Setting the MTU to other values is pointless but it does not really hurt.
With the introduction of the CAN FD support in drivers/net/can a new
function to switch the MTU for CAN FD has been introduced.
This patch makes use of this can_change_mtu() function to check for correct
MTU settings also in legacy CAN (2.0) devices.
Signed-off-by: Oliver Hartkopp <socketcan@hartkopp.net>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
Cherry-picked from linux-next: c971fa2ae42e73e9ccc2f5e93f268c8742da4c5d
Change-Id: I933a13a6c1f0b65fa748ffca352fa061940d8893
Reviewed-on: http://git.am.freescale.net:8181/21841
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch replaces an open coded pdev->id_entry by platform_get_device_id().
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
---
Cherry-picked from linux-next: d0873e6fc06686cf2dfb9adabb6ca65e9967c60f
Change-Id: I4a70c813dd5ce60b0c81cc57aa41a78413a891a0
Reviewed-on: http://git.am.freescale.net:8181/21840
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch removes #ifdef CONFIG_PM_SLEEP to improve compile coverage.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Cherry-picked from linux-next: 08c6d35154069becb01243176fb72b3bc60ff3cb
Change-Id: I062083cf2a38d7b3dfa2c9a3329c843ed6c91cf8
Reviewed-on: http://git.am.freescale.net:8181/21839
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch moves the soft reset into a seperate function.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Cherry-picked from Linux-next: 4b5b82274a17f0ebbf02378df2ba7f36a3f5af19
Change-Id: I52b4dabb58e6b9af6b5a1825bb20d40d0a8a91a7
Reviewed-on: http://git.am.freescale.net:8181/21838
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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This patch factors out freeze and unfreeze of the CAN core into seperate
functions. Experiments have shown that the transition from and to freeze mode
may take several microseconds, especially the time entering the freeze mode
depends on the current bitrate.
This patch adds a while loop which polls the Freeze Mode ACK bit (FRZ_ACK) that
indicates a successfull mode change. If the function runs into a timeout a
error value is returned.
Cc: linux-stable <stable@vger.kernel.org>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Cherry-picked from linux-next:
b1aa1c7a2165b44ecce66286a3095cc6c7667d1c
Change-Id: I0db4998dab8782d717a99eebb6d3a56ed787bbde
Reviewed-on: http://git.am.freescale.net:8181/21837
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Signed-off-by: Jason Jin <Jason.Jin@freescale.com>
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Change-Id: I3958f741a54691a882323a95b56bc7d8cb1311c4
Reviewed-on: http://git.am.freescale.net:8181/21179
Reviewed-by: Sandeep Malik <Sandeep.Malik@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
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With tx snooping enabled the eTSEC Tx DMA stops in mid-traffic
at this point. Remove the Tx snooping support from gianfar for
now.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: I89018d6cd044e86c49c64b5343c6435ab38fcbf2
Reviewed-on: http://git.am.freescale.net:8181/21177
Reviewed-by: Sandeep Malik <Sandeep.Malik@freescale.com>
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Use of_property_read*() to get arch endian consistent
property values. Do some refactoring in the process.
Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: I9ff10b73854a82333cfc830fed4b921a73519806
Reviewed-on: http://git.am.freescale.net:8181/21176
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Use conversion macros to correctly access the BE
fields of the Rx and Tx Frame Control Block on LE CPUs.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: Ieb5b1d44449f6acbfcc39ba2a0d8cd23669b5d4c
Reviewed-on: http://git.am.freescale.net:8181/21175
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Use conversion macros to correctly access the BE
fields of the Rx and Tx Buffer Descriptors on LE CPUs.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: If8674c721fb8a9cec22b6921d08680c6afb531e2
Reviewed-on: http://git.am.freescale.net:8181/21174
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Allocation of Buffer Descriptors to SRAM is not supported
by the ARM based LS1 platform. The CACHE_SRAM feature is
PPC specific (mpc85xx SoC family more exactly). The mpc85xx
CACHE_SRAM driver lies in the PPC architecture folders, so
the API calls in gianfar must be excluded from non-PPC builds,
otherwise obviously there will be compile errors on ARM (LS1).
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
Change-Id: I5594ec8fd104794d183426b973d35309d44b64e2
Reviewed-on: http://git.am.freescale.net:8181/21173
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Replace PPC specific eieio() with arch independent wmb()
for other architectures, i.e. ARM.
The eieio() macro is not defined on ARM and generates
build error.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
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Cherry-picked from commit: d55398ba81139bc826a8c2417a01280e99f08cf3
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Change-Id: I6cd072cf6e28fc81a686afab8bc42921da2e5020
Reviewed-on: http://git.am.freescale.net:8181/21172
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Use arch independent code to replace the powerpc dependent
spin_event_timeout() from gfar_halt_nodisable().
Added GRS/GTS read accessors to clean-up the implementation
of gfar_halt_nodisable().
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
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Cherry-picked from commit: a4feee89ce4590c7a4aead49ca5a4853dc6ea5dc
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Change-Id: Ie83fed01fbf4fac1593a7e5de62f90cbdad0b50f
Reviewed-on: http://git.am.freescale.net:8181/21171
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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Fix the 32-bit memory access that is not endian safe,
i.e. not giving the desired byte layout for a LE CPU:
tempval = *((u32 *) (tmpbuf + 4)), where 'char tmpbuf[]'.
Get rid of rendundant local vars (tmpbuf[] and idx) and
forced casts. Cleanup comments.
Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
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Cherry-picked from commit: 83bfc3c4765c35ef0dfff8a3d6dedab88f3f50ea
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Change-Id: Id53e47096164a4829c87559a77be32fc2496e3a6
Reviewed-on: http://git.am.freescale.net:8181/21170
Tested-by: Review Code-CDREVIEW <CDREVIEW@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
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