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During asynchronous refills, we don't wait for the refill to
finish. However, we cannot release the engine back to the idle
list until it has actually completed the refill operation. The
engine release will now be done in the IRQ handler, but only
for asynchronous refill operations.
Synchronous refills will continue to release the engine after they
unblock from waiting on the refill.
v2: Fixed review comments on async variable and bool type
Signed-off-by: Andy Gross <andy.gross@ti.com>
Signed-off-by: Rob Clark <rob@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Removing extraneous shadow lut maintenance. There is no need for
this to be in place until power management is added to the driver,
and this extra copy degrades performance for no gain.
Signed-off-by: Andy Gross <andy.gross@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Failures during the dmm probe can cause the kernel to crash. Moved
the spinlock to a global and moved list initializations immediately
after the allocation of the dmm private structure.
Signed-off-by: Andy Gross <andy.gross@ti.com>
Reviewed-by: Rob Clark <rob.clark@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Add support for YWRAP scrolling by shuffling pages around in DMM
instead of sw blits.
Note that fbcon only utilizes this mode if the y resolution is
divided evenly by the font height. So, for example, a 1920x1080
display using a 16 pixel tall font will not utilize this, but a
1280x1024 display would.
Signed-off-by: Rob Clark <rob@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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Dynamic Memory Manager (DMM) is a hardware block in the OMAP4+
processor that contains at least one TILER instance. TILER, or
Tiling and Isometric Lightweight Engine for Rotation, provides
IOMMU capabilities through the use of a physical address translation
table. The TILER also provides zero cost rotation and mirroring.
The TILER provides both 1D and 2D access by providing different views
or address ranges that can be used to access the physical memory that
has been mapped in through the PAT. Access to the 1D view results in
linear access to the underlying memory. Access to the 2D views result
in tiled access to the underlying memory resulted in increased
efficiency.
The TILER address space is managed by a tiler container manager (TCM)
and allocates the address space through the use of the Simple Tiler
Allocation algorithm (SiTA). The purpose of the algorithm is to keep
fragmentation of the address space as low as possible.
Signed-off-by: Andy Gross <andy.gross@ti.com>
Signed-off-by: Rob Clark <rob@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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