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-rwxr-xr-xrecipes-kernel/linux/files/simc-t10xx_device_tree_addition.patch858
1 files changed, 858 insertions, 0 deletions
diff --git a/recipes-kernel/linux/files/simc-t10xx_device_tree_addition.patch b/recipes-kernel/linux/files/simc-t10xx_device_tree_addition.patch
new file mode 100755
index 0000000..eebd9a6
--- /dev/null
+++ b/recipes-kernel/linux/files/simc-t10xx_device_tree_addition.patch
@@ -0,0 +1,858 @@
+From ef320c1ea090606611fcf385171bdb73df4d4eb0 Mon Sep 17 00:00:00 2001
+From: vojo <joris.van.vossen@sintecs.nl>
+Date: Thu, 24 Aug 2017 09:22:41 +0200
+Subject: [PATCH] simc-t10xx_device_tree_patch
+
+---
+ arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi | 4 +-
+ arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi | 4 +-
+ arch/powerpc/boot/dts/fsl/simc-t1022.dts | 304 ++++++++++++++++++++++++++++
+ arch/powerpc/boot/dts/fsl/simc-t1040.dts | 311 +++++++++++++++++++++++++++++
+ arch/powerpc/boot/dts/fsl/simc-t10xx.dtsi | 162 +++++++++++++++
+ 5 files changed, 781 insertions(+), 4 deletions(-)
+ create mode 100644 arch/powerpc/boot/dts/fsl/simc-t1022.dts
+ create mode 100644 arch/powerpc/boot/dts/fsl/simc-t1040.dts
+ create mode 100644 arch/powerpc/boot/dts/fsl/simc-t10xx.dtsi
+
+diff --git a/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi
+index 5f9bf7d..fec0835 100644
+--- a/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-i2c-0.dtsi
+@@ -32,7 +32,7 @@
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+-i2c@118000 {
++i2c0: i2c@118000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+@@ -42,7 +42,7 @@ i2c@118000 {
+ dfsrr;
+ };
+
+-i2c@118100 {
++i2c1: i2c@118100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <1>;
+diff --git a/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi
+index 7989bf5..74f516a 100644
+--- a/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi
++++ b/arch/powerpc/boot/dts/fsl/qoriq-i2c-1.dtsi
+@@ -32,7 +32,7 @@
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+-i2c@119000 {
++i2c2: i2c@119000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <2>;
+@@ -42,7 +42,7 @@ i2c@119000 {
+ dfsrr;
+ };
+
+-i2c@119100 {
++i2c3: i2c@119100 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <3>;
+diff --git a/arch/powerpc/boot/dts/fsl/simc-t1022.dts b/arch/powerpc/boot/dts/fsl/simc-t1022.dts
+new file mode 100644
+index 0000000..3fc75f0
+--- /dev/null
++++ b/arch/powerpc/boot/dts/fsl/simc-t1022.dts
+@@ -0,0 +1,304 @@
++/*
++ * Device tree for the SiMC-T1022 Module
++ *
++ * Copyright 2016 Scalys B.V.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ */
++
++/include/ "t104xsi-pre.dtsi"
++/include/ "simc-t10xx.dtsi"
++
++/ {
++ model = "fsl,simc-t1022";
++ compatible = "fsl,T1040D4RDB";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ interrupt-parent = <&mpic>;
++
++ chosen {
++ name = "chosen";
++
++ dpaa-extended-args {
++ fman1-extd-args {
++ cell-index = <0>;
++ compatible = "fsl,fman-extended-args";
++ fman1_rx3-extd-args {
++ cell-index = <3>;
++ compatible = "fsl,fman-port-1g-rx-extended-args";
++ ar-tables-sizes = <10 10 10 10 10 10 20 2000>;
++ ar-filters-sizes = <10 20 20>;
++ };
++ };
++ };
++ };
++
++ aliases {
++ phy_rgmii_0 = &phy_rgmii_0;
++ phy_rgmii_1 = &phy_rgmii_1;
++ };
++
++ soc: soc@ffe000000 {
++ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
++ reg = <0xf 0xfe000000 0 0x00001000>;
++
++
++ qman: qman@318000 {
++ };
++ bman: bman@31a000 {
++ };
++
++ fman0: fman@400000 {
++ sleep = <&rcpm 0x00000008>;
++
++ enet0: ethernet@e0000 {
++ /*phy-handle = <&sgmii_aqr105_phy_s5>;*/
++ phy-connection-type = "sgmii";
++ fixed-link = <1 1 1000 0 0>;
++ sleep = <&rcpm 0x80000000>;
++ };
++
++ enet1: ethernet@e2000 {
++ /*phy-handle = <&sgmii_aqr105_phy_s4>;*/
++ phy-connection-type = "sgmii";
++ fixed-link = <2 1 1000 0 0>;
++ sleep = <&rcpm 0x40000000>;
++ };
++
++ enet2: ethernet@e4000 {
++ phy-connection-type = "sgmii";
++ fixed-link = <3 1 1000 0 0>;
++ sleep = <&rcpm 0x20000000>;
++ };
++
++ enet3: ethernet@e6000 {
++ phy-handle = <&phy_rgmii_0>;
++ phy-connection-type = "rgmii";
++ sleep = <&rcpm 0x10000000>;
++ local-mac-address = [ ca fe ba be 00 01 ];
++ };
++
++ enet4: ethernet@e8000 {
++ phy-handle = <&phy_rgmii_1>;
++ phy-connection-type = "rgmii";
++ sleep = <&rcpm 0x08000000>;
++ local-mac-address = [ ca fe ba be 00 02 ];
++ };
++
++ mdio0: mdio@fc000 {
++ phy_rgmii_0: ethernet-phy@00 {
++ reg = <0x00>;
++ };
++ phy_rgmii_1: ethernet-phy@01 {
++ reg = <0x01>;
++ };
++ };
++ };
++
++ l2switch: l2switch@800000 {
++ status = "disabled";
++ };
++ };
++
++ fsl,dpaa {
++ compatible = "fsl,t1040-dpaa", "fsl,dpaa";
++ ethernet@0 {
++ compatible = "fsl,t1040-dpa-ethernet", "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet0>;
++ };
++ ethernet@1 {
++ compatible = "fsl,t1040-dpa-ethernet", "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet1>;
++ };
++ ethernet@2 {
++ compatible = "fsl,t1040-dpa-ethernet", "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet2>;
++ };
++ ethernet@3 {
++ compatible = "fsl,t1040-dpa-ethernet", "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet3>;
++ };
++ ethernet@4 {
++ compatible = "fsl,t1040-dpa-ethernet", "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet4>;
++ };
++ };
++
++ qe: qe@ffe139999 {
++ ranges = <0x0 0xf 0xfe140000 0x40000>;
++ reg = <0xf 0xfe140000 0 0x480>;
++ brg-frequency = <0>;
++ bus-frequency = <0>;
++
++ si1: si@700 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,qe-si";
++ reg = <0x700 0x80>;
++ };
++
++ siram1: siram@1000 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "fsl,qe-siram";
++ reg = <0x1000 0x800>;
++ };
++
++ tdma: ucc@2000 {
++ compatible = "fsl,ucc-tdm";
++ rx-clock-name = "clk8";
++ tx-clock-name = "clk9";
++ fsl,rx-sync-clock = "rsync_pin";
++ fsl,tx-sync-clock = "tsync_pin";
++ fsl,tx-timeslot = <0xfffffffe>;
++ fsl,rx-timeslot = <0xfffffffe>;
++ fsl,tdm-framer-type = "e1";
++ fsl,tdm-mode = "normal";
++ fsl,tdm-id = <0>;
++ fsl,siram-entry-id = <0>;
++ };
++
++ ucc@2200 {
++ compatible = "fsl,ucc_hdlc";
++ rx-clock-name = "clk10";
++ tx-clock-name = "clk11";
++ fsl,rx-sync-clock = "rsync_pin";
++ fsl,tx-sync-clock = "tsync_pin";
++ fsl,tx-timeslot = <0xfffffffe>;
++ fsl,rx-timeslot = <0xfffffffe>;
++ fsl,tdm-framer-type = "e1";
++ fsl,tdm-mode = "normal";
++ fsl,tdm-id = <1>;
++ fsl,siram-entry-id = <2>;
++ fsl,tdm-interface;
++ };
++ };
++};
++#include "t1040si-post.dtsi"
++/include/ "qoriq-dpaa-res3.dtsi"
++
++&i2c0 {
++ clock-frequency = <400000>;
++ adt7476: thermal@2e {
++ compatible = "adi,adt7476";
++ reg = <0x2e>;
++ };
++
++ adt7461a@4c {
++ compatible = "adt7461a";
++ reg = <0x4c>;
++ };
++
++ ucd9220: powermanager@4e {
++ compatible = "ti,ucd9224";
++ reg = <0x4e>;
++ };
++
++ eeprom_module@50 {
++ compatible = "microchip,24c1024";
++ reg = <0x50>;
++ };
++
++ eeprom_carrier@54 {
++ compatible = "microchip,24c1024";
++ reg = <0x54>;
++ };
++
++
++ rtc@68 {
++ compatible = "dallas,ds1307";
++ reg = <0x68>;
++ };
++};
++
++&i2c3 {
++ tca9546@70 {
++ /* Actual device is a TI TCA9546, but they are functional compatible */
++ compatible = "philips,pca9546";
++ reg = <0x70>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ i2c@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++
++ at24@30 {
++ compatible = "at24,24c01";
++ reg = <0x30>;
++ };
++ sfp@50 {
++ compatible = "optics,sfp";
++ reg = <0x50>;
++ };
++ };
++
++ i2c@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++
++ at24@30 {
++ compatible = "at24,24c01";
++ reg = <0x30>;
++ };
++ sfp@50 {
++ compatible = "optics,sfp";
++ reg = <0x50>;
++ };
++ };
++
++ i2c@2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++
++ at24@30 {
++ compatible = "at24,24c01";
++ reg = <0x30>;
++ };
++ sfp@50 {
++ compatible = "optics,sfp";
++ reg = <0x50>;
++ };
++ };
++
++ i2c@3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++ clock-frequency = <100000>;
++
++ at24@30 {
++ compatible = "at24,24c01";
++ reg = <0x30>;
++ };
++ sfp@50 {
++ compatible = "optics,sfp";
++ reg = <0x50>;
++ };
++
++ };
++ };
++};
++
++#if 1
++&sdhc {
++ /*bus-width = <4>;*/
++ voltage-ranges = <3300 3300>;
++};
++#endif
++
++#if 0
++ sgmii_vsc8234_phy_s5: ethernet-phy@1c {
++ reg = <0x1c>;
++ };
++
++ sgmii_aqr105_phy_s5: ethernet-phy@5 {
++ reg = <0x5>;
++ };
++#endif
++
+diff --git a/arch/powerpc/boot/dts/fsl/simc-t1040.dts b/arch/powerpc/boot/dts/fsl/simc-t1040.dts
+new file mode 100644
+index 0000000..d3fc108
+--- /dev/null
++++ b/arch/powerpc/boot/dts/fsl/simc-t1040.dts
+@@ -0,0 +1,311 @@
++/*
++ * Device tree for the SiMC-T1040 Module
++ *
++ * Copyright 2016 Scalys B.V.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ */
++
++/include/ "t104xsi-pre.dtsi"
++/include/ "simc-t10xx.dtsi"
++
++/ {
++ model = "fsl,simc-t1040";
++ compatible = "fsl,T1040D4RDB";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ interrupt-parent = <&mpic>;
++
++ chosen {
++ name = "chosen";
++
++ dpaa-extended-args {
++ fman1-extd-args {
++ cell-index = <0>;
++ compatible = "fsl,fman-extended-args";
++ fman1_rx3-extd-args {
++ cell-index = <3>;
++ compatible = "fsl,fman-port-1g-rx-extended-args";
++ ar-tables-sizes = <10 10 10 10 10 10 20 2000>;
++ ar-filters-sizes = <10 20 20>;
++ };
++ };
++ };
++ };
++
++ aliases {
++ phy_rgmii_0 = &phy_rgmii_0;
++ phy_rgmii_1 = &phy_rgmii_1;
++ };
++
++ soc: soc@ffe000000 {
++ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
++ reg = <0xf 0xfe000000 0 0x00001000>;
++
++
++ qman: qman@318000 {
++ };
++ bman: bman@31a000 {
++ };
++
++ fman0: fman@400000 {
++ sleep = <&rcpm 0x00000008>;
++
++ enet0: ethernet@e0000 {
++ status = "disabled";
++ };
++
++ enet1: ethernet@e2000 {
++ phy-connection-type = "sgmii";
++ fixed-link = <2 1 1000 0 0>;
++ sleep = <&rcpm 0x40000000>;
++ };
++
++ enet2: ethernet@e4000 {
++ phy-connection-type = "sgmii";
++ fixed-link = <3 1 1000 0 0>;
++ sleep = <&rcpm 0x20000000>;
++ };
++
++ enet3: ethernet@e6000 {
++ phy-handle = <&phy_rgmii_0>;
++ phy-connection-type = "rgmii";
++ sleep = <&rcpm 0x10000000>;
++ local-mac-address = [ ca fe ba be 00 01 ];
++ };
++
++ enet4: ethernet@e8000 {
++ phy-handle = <&phy_rgmii_1>;
++ phy-connection-type = "rgmii";
++ sleep = <&rcpm 0x08000000>;
++ local-mac-address = [ ca fe ba be 00 02 ];
++ };
++
++ mdio0: mdio@fc000 {
++ phy_rgmii_0: ethernet-phy@00 {
++ reg = <0x00>;
++ };
++ phy_rgmii_1: ethernet-phy@01 {
++ reg = <0x01>;
++ };
++ };
++ };
++
++ l2switch: l2switch@800000 {
++ port@100000 {
++ phy-connection-type = "sgmii";
++ fixed-link = <1 1 1000 0 0>;
++ };
++ port@110000 {
++ phy-connection-type = "sgmii";
++ fixed-link = <1 1 1000 0 0>;
++ };
++ port@120000 {
++ phy-connection-type = "sgmii";
++ fixed-link = <1 1 1000 0 0>;
++ };
++ port@130000 {
++ status = "disabled";
++ };
++ port@140000 {
++ status = "disabled";
++ };
++ port@150000 {
++ status = "disabled";
++ };
++ port@160000 {
++ status = "disabled";
++ };
++ port@170000 {
++ status = "disabled";
++ };
++ };
++ };
++
++ fsl,dpaa {
++ compatible = "fsl,t1040-dpaa", "fsl,dpaa";
++
++ ethernet@1 {
++ compatible = "fsl,t1040-dpa-ethernet", "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet1>;
++ };
++ ethernet@2 {
++ compatible = "fsl,t1040-dpa-ethernet", "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet2>;
++ };
++ ethernet@3 {
++ compatible = "fsl,t1040-dpa-ethernet", "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet3>;
++ };
++ ethernet@4 {
++ compatible = "fsl,t1040-dpa-ethernet", "fsl,dpa-ethernet";
++ fsl,fman-mac = <&enet4>;
++ };
++ };
++
++ qe: qe@ffe139999 {
++ ranges = <0x0 0xf 0xfe140000 0x40000>;
++ reg = <0xf 0xfe140000 0 0x480>;
++ brg-frequency = <0>;
++ bus-frequency = <0>;
++
++ si1: si@700 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "fsl,qe-si";
++ reg = <0x700 0x80>;
++ };
++
++ siram1: siram@1000 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "fsl,qe-siram";
++ reg = <0x1000 0x800>;
++ };
++
++ tdma: ucc@2000 {
++ compatible = "fsl,ucc-tdm";
++ rx-clock-name = "clk8";
++ tx-clock-name = "clk9";
++ fsl,rx-sync-clock = "rsync_pin";
++ fsl,tx-sync-clock = "tsync_pin";
++ fsl,tx-timeslot = <0xfffffffe>;
++ fsl,rx-timeslot = <0xfffffffe>;
++ fsl,tdm-framer-type = "e1";
++ fsl,tdm-mode = "normal";
++ fsl,tdm-id = <0>;
++ fsl,siram-entry-id = <0>;
++ };
++
++ ucc@2200 {
++ compatible = "fsl,ucc_hdlc";
++ rx-clock-name = "clk10";
++ tx-clock-name = "clk11";
++ fsl,rx-sync-clock = "rsync_pin";
++ fsl,tx-sync-clock = "tsync_pin";
++ fsl,tx-timeslot = <0xfffffffe>;
++ fsl,rx-timeslot = <0xfffffffe>;
++ fsl,tdm-framer-type = "e1";
++ fsl,tdm-mode = "normal";
++ fsl,tdm-id = <1>;
++ fsl,siram-entry-id = <2>;
++ fsl,tdm-interface;
++ };
++ };
++};
++#include "t1040si-post.dtsi"
++/include/ "qoriq-dpaa-res3.dtsi"
++
++&i2c0 {
++ clock-frequency = <400000>;
++ adt7476: thermal@2e {
++ compatible = "adi,adt7476";
++ reg = <0x2e>;
++ };
++
++ adt7461a@4c {
++ compatible = "adt7461a";
++ reg = <0x4c>;
++ };
++
++ ucd9220: powermanager@4e {
++ compatible = "ti,ucd9224";
++ reg = <0x4e>;
++ };
++
++ eeprom_module@50 {
++ compatible = "microchip,24c1024";
++ reg = <0x50>;
++ };
++
++ eeprom_carrier@54 {
++ compatible = "microchip,24c1024";
++ reg = <0x54>;
++ };
++
++
++ rtc@68 {
++ compatible = "dallas,ds1307";
++ reg = <0x68>;
++ };
++};
++
++&i2c3 {
++ tca9546@70 {
++ /* Actual device is a TI TCA9546, but they are functional compatible */
++ compatible = "philips,pca9546";
++ reg = <0x70>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ i2c@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0>;
++
++ at24@30 {
++ compatible = "at24,24c01";
++ reg = <0x30>;
++ };
++ sfp@50 {
++ compatible = "optics,sfp";
++ reg = <0x50>;
++ };
++ };
++
++ i2c@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++
++ at24@30 {
++ compatible = "at24,24c01";
++ reg = <0x30>;
++ };
++ sfp@50 {
++ compatible = "optics,sfp";
++ reg = <0x50>;
++ };
++ };
++
++ i2c@2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <2>;
++
++ at24@30 {
++ compatible = "at24,24c01";
++ reg = <0x30>;
++ };
++ sfp@50 {
++ compatible = "optics,sfp";
++ reg = <0x50>;
++ };
++ };
++
++ i2c@3 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <3>;
++ clock-frequency = <100000>;
++
++ at24@30 {
++ compatible = "at24,24c01";
++ reg = <0x30>;
++ };
++ sfp@50 {
++ compatible = "optics,sfp";
++ reg = <0x50>;
++ };
++
++ };
++ };
++};
++
++&sdhc {
++ /*bus-width = <4>;*/
++ voltage-ranges = <3300 3300>;
++};
++
+diff --git a/arch/powerpc/boot/dts/fsl/simc-t10xx.dtsi b/arch/powerpc/boot/dts/fsl/simc-t10xx.dtsi
+new file mode 100644
+index 0000000..562cfc1
+--- /dev/null
++++ b/arch/powerpc/boot/dts/fsl/simc-t10xx.dtsi
+@@ -0,0 +1,162 @@
++/*
++ * Device tree for the SiMC-T10xx series Modules
++ *
++ * Copyright 2016 Scalys B.V.
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ */
++
++/ {
++ reserved-memory {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ bman_fbpr: bman-fbpr {
++ size = <0 0x1000000>;
++ alignment = <0 0x1000000>;
++ };
++ qman_fqd: qman-fqd {
++ size = <0 0x800000>;
++ alignment = <0 0x800000>;
++ };
++ qman_pfdr: qman-pfdr {
++ size = <0 0x2000000>;
++ alignment = <0 0x2000000>;
++ };
++ pme_pdsr: pme-pdsr {
++ compatible = "fsl,pme-pdsr";
++ alloc-ranges = <0 0 0x10000 0>;
++ size = <0 0x1000000>;
++ alignment = <0 0x1000000>;
++ };
++ pme_sre: pme-sre {
++ compatible = "fsl,pme-sre";
++ alloc-ranges = <0 0 0x10000 0>;
++ size = <0 0xa00000>;
++ alignment = <0 0xa00000>;
++ };
++ };
++
++ ifc: localbus@ffe124000 {
++ reg = <0xf 0xfe124000 0 0x2000>;
++ ranges = < 0 0 0xf 0xff800000 0x00010000 /* NAND Flash on CS0 */
++ 1 0 0xf 0xe8000000 0x02000000 >; /* NOR Flash on CS1 */
++
++ nand@0,0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "fsl,ifc-nand";
++ reg = <0 0x0 0x10000>;
++
++ /* Partitions should be mapped using the mtdparts argument in the bootargs */
++ status = "okay";
++ };
++ };
++
++ memory {
++ device_type = "memory";
++ };
++
++ dcsr: dcsr@f00000000 {
++ ranges = <0x00000000 0xf 0x00000000 0x01072000>;
++ };
++
++ bportals: bman-portals@ff4000000 {
++ ranges = <0x0 0xf 0xf4000000 0x2000000>;
++ };
++
++ qportals: qman-portals@ff6000000 {
++ ranges = <0x0 0xf 0xf6000000 0x2000000>;
++ };
++
++ soc: soc@ffe000000 {
++ ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
++ reg = <0xf 0xfe000000 0 0x00001000>;
++
++ spi@110000 {
++ flash@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "micron,n25q512ax3";
++ reg = <0>;
++ spi-max-frequency = <10000000>; /* input clock */
++ };
++ slic@1 {
++ compatible = "maxim,ds26522";
++ reg = <1>;
++ spi-max-frequency = <2000000>; /* input clock */
++ };
++ slic@2 {
++ compatible = "maxim,ds26522";
++ reg = <2>;
++ spi-max-frequency = <2000000>; /* input clock */
++ };
++ };
++
++ };
++
++ pci0: pcie@ffe240000 {
++ reg = <0xf 0xfe240000 0 0x10000>;
++ ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000
++ 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
++ pcie@0 {
++ ranges = <0x02000000 0 0xe0000000
++ 0x02000000 0 0xe0000000
++ 0 0x10000000
++
++ 0x01000000 0 0x00000000
++ 0x01000000 0 0x00000000
++ 0 0x00010000>;
++ };
++ };
++
++ pci1: pcie@ffe250000 {
++ reg = <0xf 0xfe250000 0 0x10000>;
++ ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
++ 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
++ pcie@0 {
++ ranges = <0x02000000 0 0xe0000000
++ 0x02000000 0 0xe0000000
++ 0 0x10000000
++
++ 0x01000000 0 0x00000000
++ 0x01000000 0 0x00000000
++ 0 0x00010000>;
++ };
++ };
++
++ pci2: pcie@ffe260000 {
++ reg = <0xf 0xfe260000 0 0x10000>;
++ ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
++ 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
++ pcie@0 {
++ ranges = <0x02000000 0 0xe0000000
++ 0x02000000 0 0xe0000000
++ 0 0x10000000
++
++ 0x01000000 0 0x00000000
++ 0x01000000 0 0x00000000
++ 0 0x00010000>;
++ };
++ };
++
++ pci3: pcie@ffe270000 {
++ reg = <0xf 0xfe270000 0 0x10000>;
++ ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
++ 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
++ pcie@0 {
++ ranges = <0x02000000 0 0xe0000000
++ 0x02000000 0 0xe0000000
++ 0 0x10000000
++
++ 0x01000000 0 0x00000000
++ 0x01000000 0 0x00000000
++ 0 0x00010000>;
++ };
++ };
++
++};
++
+--
+1.9.1
+
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