diff options
Diffstat (limited to 'recipes-kernel/linux/files/simc-t2081_device_tree_addition.patch')
-rwxr-xr-x | recipes-kernel/linux/files/simc-t2081_device_tree_addition.patch | 431 |
1 files changed, 431 insertions, 0 deletions
diff --git a/recipes-kernel/linux/files/simc-t2081_device_tree_addition.patch b/recipes-kernel/linux/files/simc-t2081_device_tree_addition.patch new file mode 100755 index 0000000..a5382b1 --- /dev/null +++ b/recipes-kernel/linux/files/simc-t2081_device_tree_addition.patch @@ -0,0 +1,431 @@ +From b7b2b9772f77b8238c29022a575b94ed3bf0dbec Mon Sep 17 00:00:00 2001 +From: vojo <joris.van.vossen@sintecs.nl> +Date: Fri, 25 Aug 2017 09:37:45 +0200 +Subject: [PATCH] simc-t2081_device_tree_addition + +--- + arch/powerpc/boot/dts/fsl/simc-t2081.dts | 207 ++++++++++++++++++++++++++++++ + arch/powerpc/boot/dts/fsl/simc-t2081.dtsi | 197 +++++++++++++++ + 2 files changed, 404 insertions(+) + create mode 100644 arch/powerpc/boot/dts/fsl/simc-t2081.dts + create mode 100644 arch/powerpc/boot/dts/fsl/simc-t2081.dtsi + +diff --git a/arch/powerpc/boot/dts/fsl/simc-t2081.dts b/arch/powerpc/boot/dts/fsl/simc-t2081.dts +new file mode 100644 +index 0000000..193170e +--- /dev/null ++++ b/arch/powerpc/boot/dts/fsl/simc-t2081.dts +@@ -0,0 +1,207 @@ ++/* ++ * Device tree for the SiMC-T2081 Module ++ * ++ * Copyright 2017 Scalys B.V. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ */ ++ ++/include/ "t208xsi-pre.dtsi" ++/include/ "simc-t2081.dtsi" ++ ++/ { ++ model = "fsl,simc-t2081"; ++ compatible = "fsl,T2081QDS"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ interrupt-parent = <&mpic>; ++ ++}; ++ ++&soc { ++ fman0: fman@400000 { ++ fm1mac1: ethernet@e0000 { /* 10GEC3 */ ++ /*phy-handle = <&xg_cs4315_phy1>;*/ ++ phy-connection-type = "sgmii"; ++ fixed-link = <1 1 1000 0 0>; ++ }; ++ ++ fm1mac2: ethernet@e2000 { /* 10GEC4 */ ++ /*phy-handle = <&xg_cs4315_phy2>;*/ ++ phy-connection-type = "sgmii"; ++ fixed-link = <2 1 1000 0 0>; ++ }; ++ ++ fm1mac3: ethernet@e4000 { ++ phy-handle = <&phy_rgmii_0>; ++ phy-connection-type = "rgmii"; ++ }; ++ ++ fm1mac4: ethernet@e6000 { ++ phy-handle = <&phy_rgmii_1>; ++ phy-connection-type = "rgmii"; ++ }; ++ ++ fm1mac5: ethernet@e8000 { ++ phy-connection-type = "sgmii"; ++ fixed-link = <5 1 1000 0 0>; ++ }; ++ ++ fm1mac6: ethernet@ea000 { ++ phy-connection-type = "sgmii"; ++ fixed-link = <6 1 1000 0 0>; ++ }; ++ ++ fm1mac9: ethernet@f0000 { /* 10GEC1 */ ++ phy-handle = <&xg_cs4315_phy0>; ++ phy-connection-type = "xgmii"; ++ }; ++ ++ fm1mac10: ethernet@f2000 { /* 10GEC2 */ ++ phy-handle = <&xg_cs4315_phy1>; ++ phy-connection-type = "xgmii"; ++ }; ++ ++ mdio0: mdio@fc000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ phy_rgmii_0: ethernet-phy@00 { ++ reg = <0x0>; ++ }; ++ phy_rgmii_1: ethernet-phy@01 { ++ reg = <0x1>; ++ }; ++ }; ++ ++ xmdio0: mdio@fd000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ xg_cs4315_phy0: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <0x0>; ++ }; ++ xg_cs4315_phy1: ethernet-phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <0x1>; ++ }; ++ }; ++ }; ++}; ++ ++ ++/include/ "t2081si-post.dtsi" ++/include/ "qoriq-dpaa-res3.dtsi" ++/include/ "qoriq-qman-ceetm0.dtsi" ++ ++&i2c0 { ++ clock-frequency = <400000>; ++ adt7476: thermal@2e { ++ compatible = "adi,adt7476"; ++ reg = <0x2e>; ++ }; ++ ++ adt7461a@4c { ++ compatible = "adt7461a"; ++ reg = <0x4c>; ++ }; ++ ++ ucd9220: powermanager@4e { ++ compatible = "ti,ucd9224"; ++ reg = <0x4e>; ++ }; ++ ++ eeprom_module@50 { ++ compatible = "microchip,24c1024"; ++ reg = <0x50>; ++ }; ++ ++ eeprom_carrier@54 { ++ compatible = "microchip,24c1024"; ++ reg = <0x54>; ++ }; ++ ++ ++ rtc@68 { ++ compatible = "dallas,ds1307"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c3 { ++ tca9546@70 { ++ /* Actual device is a TI TCA9546, but they are functional compatible */ ++ compatible = "philips,pca9546"; ++ reg = <0x70>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0>; ++ ++ at24@30 { ++ compatible = "at24,24c01"; ++ reg = <0x30>; ++ }; ++ sfp@50 { ++ compatible = "optics,sfp"; ++ reg = <0x50>; ++ }; ++ }; ++ ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <1>; ++ ++ at24@30 { ++ compatible = "at24,24c01"; ++ reg = <0x30>; ++ }; ++ sfp@50 { ++ compatible = "optics,sfp"; ++ reg = <0x50>; ++ }; ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <2>; ++ ++ at24@30 { ++ compatible = "at24,24c01"; ++ reg = <0x30>; ++ }; ++ sfp@50 { ++ compatible = "optics,sfp"; ++ reg = <0x50>; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <3>; ++ clock-frequency = <100000>; ++ ++ at24@30 { ++ compatible = "at24,24c01"; ++ reg = <0x30>; ++ }; ++ sfp@50 { ++ compatible = "optics,sfp"; ++ reg = <0x50>; ++ }; ++ ++ }; ++ }; ++}; ++ ++&sdhc { ++ /*bus-width = <4>;*/ ++ voltage-ranges = <3300 3300>; ++}; +diff --git a/arch/powerpc/boot/dts/fsl/simc-t2081.dtsi b/arch/powerpc/boot/dts/fsl/simc-t2081.dtsi +new file mode 100644 +index 0000000..62cc360 +--- /dev/null ++++ b/arch/powerpc/boot/dts/fsl/simc-t2081.dtsi +@@ -0,0 +1,197 @@ ++/* ++ * Device tree for the SiMC-T2081 Module ++ * ++ * Copyright 2017 Scalys B.V. ++ * ++ * This software is licensed under the terms of the GNU General Public ++ * License version 2, as published by the Free Software Foundation, and ++ * may be copied, distributed, and modified under those terms. ++ */ ++ ++/ { ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ bman_fbpr: bman-fbpr { ++ size = <0 0x1000000>; ++ alignment = <0 0x1000000>; ++ }; ++ qman_fqd: qman-fqd { ++ size = <0 0x800000>; ++ alignment = <0 0x800000>; ++ }; ++ qman_pfdr: qman-pfdr { ++ size = <0 0x2000000>; ++ alignment = <0 0x2000000>; ++ }; ++ pme_pdsr: pme-pdsr { ++ compatible = "fsl,pme-pdsr"; ++ alloc-ranges = <0 0 0x10000 0>; ++ size = <0 0x1000000>; ++ alignment = <0 0x1000000>; ++ }; ++ pme_sre: pme-sre { ++ compatible = "fsl,pme-sre"; ++ alloc-ranges = <0 0 0x10000 0>; ++ size = <0 0xa00000>; ++ alignment = <0 0xa00000>; ++ }; ++ }; ++ ++ ifc: localbus@ffe124000 { ++ reg = <0xf 0xfe124000 0 0x2000>; ++ ranges = < 0 0 0xf 0xff800000 0x00010000 /* NAND Flash on CS0 */ ++ 1 0 0xf 0xe8000000 0x02000000 >; /* NOR Flash on CS1 */ ++ ++ nand@0,0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "fsl,ifc-nand"; ++ reg = <0 0x0 0x10000>; ++ ++ /* Partitions should be mapped using the mtdparts argument in the bootargs */ ++ status = "okay"; ++ }; ++ }; ++ ++ memory { ++ device_type = "memory"; ++ }; ++ ++ dcsr: dcsr@f00000000 { ++ ranges = <0x00000000 0xf 0x00000000 0x01072000>; ++ }; ++ ++ bportals: bman-portals@ff4000000 { ++ ranges = <0x0 0xf 0xf4000000 0x2000000>; ++ }; ++ ++ qportals: qman-portals@ff6000000 { ++ #address-cells = <1>; ++ ranges = <0x0 0xf 0xf6000000 0x2000000>; ++ }; ++ ++ soc: soc@ffe000000 { ++ ranges = <0x00000000 0xf 0xfe000000 0x1000000>; ++ reg = <0xf 0xfe000000 0 0x00001000>; ++ ++ spi@110000 { ++ flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "micron,n25q512ax3"; ++ reg = <0>; ++ spi-max-frequency = <10000000>; /* input clock */ ++ }; ++ slic@1 { ++ compatible = "maxim,ds26522"; ++ reg = <1>; ++ spi-max-frequency = <2000000>; /* input clock */ ++ }; ++ slic@2 { ++ compatible = "maxim,ds26522"; ++ reg = <2>; ++ spi-max-frequency = <2000000>; /* input clock */ ++ }; ++ }; ++ ++ }; ++ ++ pci0: pcie@ffe240000 { ++ reg = <0xf 0xfe240000 0 0x10000>; ++ ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 ++ 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; ++ pcie@0 { ++ ranges = <0x02000000 0 0xe0000000 ++ 0x02000000 0 0xe0000000 ++ 0 0x20000000 ++ ++ 0x01000000 0 0x00000000 ++ 0x01000000 0 0x00000000 ++ 0 0x00010000>; ++ }; ++ }; ++ ++ pci1: pcie@ffe250000 { ++ reg = <0xf 0xfe250000 0 0x10000>; ++ ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000 ++ 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; ++ pcie@0 { ++ ranges = <0x02000000 0 0xe0000000 ++ 0x02000000 0 0xe0000000 ++ 0 0x20000000 ++ ++ 0x01000000 0 0x00000000 ++ 0x01000000 0 0x00000000 ++ 0 0x00010000>; ++ }; ++ }; ++ ++ pci2: pcie@ffe260000 { ++ reg = <0xf 0xfe260000 0 0x1000>; ++ ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000 ++ 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; ++ pcie@0 { ++ ranges = <0x02000000 0 0xe0000000 ++ 0x02000000 0 0xe0000000 ++ 0 0x20000000 ++ ++ 0x01000000 0 0x00000000 ++ 0x01000000 0 0x00000000 ++ 0 0x00010000>; ++ }; ++ }; ++ ++ pci3: pcie@ffe270000 { ++ reg = <0xf 0xfe270000 0 0x10000>; ++ ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x10000000 ++ 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; ++ pcie@0 { ++ ranges = <0x02000000 0 0xe0000000 ++ 0x02000000 0 0xe0000000 ++ 0 0x20000000 ++ ++ 0x01000000 0 0x00000000 ++ 0x01000000 0 0x00000000 ++ 0 0x00010000>; ++ }; ++ }; ++ ++ fsl,dpaa { ++ compatible = "fsl,t2080-dpaa", "fsl,dpaa"; ++ ethernet@0 { ++ compatible = "fsl,dpa-ethernet"; ++ fsl,fman-mac = <&fm1mac1>; ++ }; ++ ethernet@1 { ++ compatible = "fsl,dpa-ethernet"; ++ fsl,fman-mac = <&fm1mac2>; ++ }; ++ ethernet@2 { ++ compatible = "fsl,dpa-ethernet"; ++ fsl,fman-mac = <&fm1mac3>; ++ }; ++ ethernet@3 { ++ compatible = "fsl,dpa-ethernet"; ++ fsl,fman-mac = <&fm1mac4>; ++ }; ++ ethernet@4 { ++ compatible = "fsl,dpa-ethernet"; ++ fsl,fman-mac = <&fm1mac5>; ++ }; ++ ethernet@5 { ++ compatible = "fsl,dpa-ethernet"; ++ fsl,fman-mac = <&fm1mac6>; ++ }; ++ ethernet@8 { ++ compatible = "fsl,dpa-ethernet"; ++ fsl,fman-mac = <&fm1mac9>; ++ }; ++ ethernet@9 { ++ compatible = "fsl,dpa-ethernet"; ++ fsl,fman-mac = <&fm1mac10>; ++ }; ++ }; ++}; +-- +1.9.1 + |