Upstream u-boot update and added QT1040-1GB device support

57 files changed, 4441 insertions, 372 deletions

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 0f01db0..b770a6a 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -400,12 +400,57 @@ config TARGET_CYRUS_P5040
 	select ARCH_P5040
 	select PHYS_64BIT
 
-config TARGET_SIMC_T10XX
-	bool "Support simc-t10xx"
+config TARGET_SIMC_TXXXX
+	bool "Support simc-txxxx"
+	select BOARD_LATE_INIT if CHAIN_OF_TRUST
+	select PHYS_64BIT
+	select SUPPORT_SPL
+	
+config TARGET_QT1040_1GB
+	bool "Support QT1040-1GB"
+    select ARCH_T1040
+    select BOARD_LATE_INIT if CHAIN_OF_TRUST
+    select PHYS_64BIT
 	select SUPPORT_SPL
-
 endchoice
 
+choice
+	depends on TARGET_SIMC_TXXXX || TARGET_QT1040_1GB
+	prompt "CPU type"
+	optional
+	help
+	Select the exact type of CPU which is used on the version of the simc-txxxx module
+	
+config PPC_T1020
+	bool
+	prompt "T1020"
+	depends on TARGET_SIMC_TXXXX
+	select ARCH_T1020
+	
+config PPC_T1022
+	bool
+	prompt "T1022"
+	depends on TARGET_SIMC_TXXXX
+	select ARCH_T1022
+
+config PPC_T1040
+	bool
+	prompt "T1040"
+	select ARCH_T1040
+
+config PPC_T1042
+	bool
+	prompt "T1042"
+	depends on TARGET_SIMC_TXXXX
+	select ARCH_T1042
+
+#config PPC_T2081
+#	bool
+#	prompt "T2081"
+#	depends on TARGET_SIMC_TXXXX
+#	select ARCH_T2081
+endchoice	
+
 config ARCH_B4420
 	bool
 	select E500MC
@@ -1526,7 +1571,9 @@ source "board/freescale/t4rdb/Kconfig"
 source "board/gdsys/p1022/Kconfig"
 source "board/keymile/kmp204x/Kconfig"
 source "board/sbc8548/Kconfig"
+source "board/scalys/common/Kconfig"
 source "board/scalys/simc-t10xx/Kconfig"
+source "board/scalys/simc-t2081/Kconfig"
 source "board/socrates/Kconfig"
 source "board/varisys/cyrus/Kconfig"
 source "board/xes/xpedite520x/Kconfig"
diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
index 0c72c71..76faa22 100644
--- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h
@@ -14,7 +14,6 @@
 #ifndef __ASM_ARCH_MX85XX_GPIO_H
 #define __ASM_ARCH_MX85XX_GPIO_H
 
-<<<<<<< bc5d0384458466ed5b3608d326eec03cd4f13016
 #ifndef CONFIG_MPC85XX_GPIO
 #include <asm/mpc85xx_gpio.h>
 #endif
@@ -24,12 +23,5 @@ struct mpc85xx_gpio_plat {
 	unsigned long size;
 	uint ngpios;
 };
-=======
-#ifdef CONFIG_MPC8XXX_GPIO
-#include <asm/mpc8xxx_gpio.h>
-#else
-#include <asm/mpc85xx_gpio.h>
-#endif
->>>>>>> dm: gpio: Add DM GPIO driver for MPC8xxx platforms
 
 #endif
diff --git a/board/scalys/common/Kconfig b/board/scalys/common/Kconfig
new file mode 100644
index 0000000..51cdc24
--- /dev/null
+++ b/board/scalys/common/Kconfig
@@ -0,0 +1,81 @@
+if TARGET_SIMC_TXXXX || TARGET_QT1040_1GB
+
+config SYS_VENDOR
+	default "scalys"
+	
+config RAMBOOT_PBL
+	bool
+	default y
+
+config SPL_FSL_PBL
+	bool
+	default y
+
+config NOR_FLASH
+	bool
+	prompt "Support NOR flash"
+	default y
+
+config NAND_FLASH
+	bool
+	prompt "Support NAND flash"
+	default y
+	
+config SPI_FLASH
+	bool
+	prompt "Support SPI flash"
+	default y
+	
+config SDHC_FLASH
+	bool
+	prompt "Support SDHC flash"
+	default y
+
+choice
+	prompt "SYSCLK frequency"
+	default SYS_CLK_FREQ_100
+
+config SYS_CLK_FREQ_66
+	bool
+	prompt "66.6 MHz"
+	
+config SYS_CLK_FREQ_100
+	bool
+	prompt "100 MHz"
+
+endchoice
+
+choice
+	prompt "Bootsource"
+	default NAND_FLASH_BOOT
+	
+config NAND_FLASH_BOOT
+	bool
+	depends on NAND_FLASH
+	prompt "NAND boot"
+	help
+	Select NAND Flash as the bootsource
+	
+config NOR_FLASH_BOOT
+	bool
+	depends on NOR_FLASH
+	prompt "NOR boot"
+	help
+	Select NOR Flash as the bootsource
+
+config SPI_FLASH_BOOT
+	bool
+	depends on SPI_FLASH
+	prompt "SPI boot"
+	help
+	Select SPI Flash as the bootsource
+	
+config SDHC_FLASH_BOOT
+	bool
+	depends on SDHC_FLASH
+	prompt "SDHC boot"
+	help
+	Select SDHC Flash as the bootsource
+endchoice
+
+endif
diff --git a/board/scalys/common/board_configuration_data.c b/board/scalys/common/board_configuration_data.c
index b6374da..fcb4e92 100644
--- a/board/scalys/common/board_configuration_data.c
+++ b/board/scalys/common/board_configuration_data.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -11,7 +11,7 @@
 #include <fdt_support.h>
 
 #include <i2c.h>
-#include <asm-generic/errno.h>
+#include <linux/errno.h>
 #include <malloc.h>
 
 #include "board_configuration_data.h"
@@ -49,7 +49,7 @@ int add_mac_addressess_to_env(const void* blob)
 			
 		memcpy(mac_address, value, 6);
 		
-		//ret = fdtdec_get_byte_array( blob, prop_offset, propname, mac_address, 6 );
+		/* ret = fdtdec_get_byte_array( blob, prop_offset, propname, mac_address, 6 ); */
 		
 		if (count) {
 			snprintf(eth_string, sizeof(eth_string), "eth%iaddr", count);
@@ -93,17 +93,17 @@ const void* get_boardinfo_eeprom(void)
 	/* Read the last 4 bytes to determine the lenght of the DTB data */
 	ret = i2c_read(BCD_I2C_ADDRESS, (BCD_EEPROM_SIZE-4), 2, (uint8_t*) &bcd_data_lenght, 4 );
 	if (ret != 0) {
-		debug("Error reading bcd length\n");
+		printf("Error reading bcd length\n");
 		errno = -ENODEV;
 		goto err_no_free;
 	}
 	
 	/* Convert lenght from big endianess to architecture endianess */
 	bcd_data_lenght = ntohl(bcd_data_lenght);
-	debug("bcd_data_lenght = %i\n", bcd_data_lenght );	
+	printf("bcd_data_lenght = %i\n", bcd_data_lenght );	
 	
 	if (bcd_data_lenght > BCD_EEPROM_SIZE ) {
-		debug("%02x %02x %02x %02x\n", 
+		printf("BCD data length error %02x %02x %02x %02x\n", 
 		      ( (uint8_t*) &bcd_data_lenght)[0],
 		      ( (uint8_t*) &bcd_data_lenght)[1],
 		      ( (uint8_t*) &bcd_data_lenght)[2],
@@ -115,17 +115,17 @@ const void* get_boardinfo_eeprom(void)
 	/* Allocate, and verify memory for the BCD data */
 	bcd_data = (uint8_t*) malloc(bcd_data_lenght);
 	if (bcd_data == NULL) {
-		debug("Error locating memory for BCD data\n");
+		printf("Error locating memory for BCD data\n");
 		goto err_no_free;
 	}
-	debug("Allocated memory for BCD data\n");
+	printf("Allocated memory for BCD data\n");
 	
 	/* Read the DTB BCD data to memory */
 	ret = i2c_read(BCD_I2C_ADDRESS, (BCD_EEPROM_SIZE-bcd_data_lenght), 2, (uint8_t*) bcd_data, bcd_data_lenght );
-	debug("Read data from I2C bus\n");
+	printf("Read data from I2C bus\n");
 
 	if (ret != 0) {
-		debug("Error reading complete BCD data from EEPROM\n");
+		printf("Error reading complete BCD data from EEPROM\n");
 		errno = -ENOMEM;
 		goto err_free;
 	}
@@ -141,7 +141,7 @@ const void* get_boardinfo_eeprom(void)
 	received_crc = ntohl(received_crc);
 	
    	if (calculated_crc !=  received_crc) {
-		debug("Checksum error. expected %08x, got %08x\n",
+		printf("Checksum error. expected %08x, got %08x\n",
 			calculated_crc, received_crc);
 		errno = -EBADMSG;
 		goto err_free;
@@ -389,4 +389,4 @@ U_BOOT_CMD(
 	"Show the Board Configuration Data (stored in eeprom)",
 	""
 );
-#endif
\ No newline at end of file
+#endif
diff --git a/board/scalys/simc-t10xx/Kconfig b/board/scalys/simc-t10xx/Kconfig
index 2b18913..4ac5c59 100644
--- a/board/scalys/simc-t10xx/Kconfig
+++ b/board/scalys/simc-t10xx/Kconfig
@@ -1,72 +1,23 @@
-if TARGET_SIMC_T10XX
+if (TARGET_SIMC_TXXXX || TARGET_QT1040_1GB) && !ARCH_T2081
 
 config SYS_BOARD
 	string
 	default "simc-t10xx"
+	
+endif
 
-config SYS_VENDOR
-	string
-	default "scalys"
+if TARGET_SIMC_TXXXX && !ARCH_T2081
 
 config SYS_CONFIG_NAME
 	string
 	default "simc-t10xx"
-	
-config RAMBOOT_PBL
-	bool
-	default y
-
-config SPL_FSL_PBL
-	bool
-	default y
 
-choice
-	prompt "Bootsource"
-	default NAND
-config NAND
-	bool
-	prompt "NAND boot"
-	help
-	Select NAND as the bootsource
-
-endchoice
-
-choice
-	prompt "SYSCLK frequency"
-	default SYS_CLK_FREQ_100
-
-config SYS_CLK_FREQ_66
-	bool
-	prompt "66.6 MHz"
-	
-config SYS_CLK_FREQ_100
-	bool
-	prompt "100 MHz"
-
-endchoice
-
-choice
-	prompt "CPU type"
-	default PPC_T1040
-	help
-	Select the exact type of CPU which is used on the version of the simc-t10xx module
-	
-config PPC_T1020
-	bool
-	prompt "T1020"
-	
-config PPC_T1022
-	bool
-	prompt "T1022"
+endif
 
-config PPC_T1040
-	bool
-	prompt "T1040"
+if TARGET_QT1040_1GB
 
-config PPC_T1042
-	bool
-	prompt "T1042"
-	
-endchoice
+config SYS_CONFIG_NAME
+	string
+	default "QT1040-1GB"
 
 endif
diff --git a/board/scalys/simc-t10xx/Makefile b/board/scalys/simc-t10xx/Makefile
index 83ac551..59f29ec 100644
--- a/board/scalys/simc-t10xx/Makefile
+++ b/board/scalys/simc-t10xx/Makefile
@@ -1,4 +1,4 @@
-# Copyright 2016 Scalys B.V.
+# Copyright 2017 Scalys B.V.
 # opensource@scalys.com
 # 
 # SPDX-License-Identifier:	GPL-2.0+
@@ -13,7 +13,11 @@ obj-y	+= simc-t10xx.o
 obj-y	+= eth.o
 obj-$(CONFIG_PCI)	+= pci.o
 endif
+ifdef CONFIG_TARGET_QT1040_1GB
+obj-y	+= ddr_QT1040-1GB.o
+else
 obj-y	+= ddr.o
+endif
 obj-y	+= law.o
 obj-y	+= tlb.o
-obj-y	+= dragonfruit.o
\ No newline at end of file
+obj-y	+= dragonfruit.o
diff --git a/board/scalys/simc-t10xx/ddr.c b/board/scalys/simc-t10xx/ddr.c
index f6d04ac..7fed0d2 100644
--- a/board/scalys/simc-t10xx/ddr.c
+++ b/board/scalys/simc-t10xx/ddr.c
@@ -1,24 +1,19 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
-#include <asm/mmu.h>
-//#include <asm/gpio.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-#include <common.h>
 #include <i2c.h>
 #include <hwconfig.h>
 #include <asm/mmu.h>
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
-//#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /* MT41K512M8RH-125 */
 dimm_params_t ddr_raw_timing = {
@@ -45,7 +40,7 @@ dimm_params_t ddr_raw_timing = {
 	.tfaw_ps = 30000,
 	.twr_ps = 15000,
 	.trfc_ps = 260000,
-	.trrd_ps = 6000,
+	.trrd_ps = 5000, //1Kb page size!
 	.twtr_ps = 7500,
 	.trtp_ps = 7500,
 	.refresh_rate_ps = 70200000,
@@ -90,6 +85,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
 
 	/* Clock is launched 1/2 applied cycle after address/command */
 	popts->clk_adjust = 8; 
+	
+	/* Optimized cpo */
+	popts->cpo_sample = 0x46;
 }
 
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
@@ -108,7 +106,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
 	return 0;
 }
 
-phys_size_t initdram(int board_type)
+int dram_init(void)
 {
 	phys_size_t dram_size;
 
@@ -142,5 +140,7 @@ phys_size_t initdram(int board_type)
 	dram_size =  fsl_ddr_sdram_size();
 #endif
 	
-	return dram_size;
+	gd->ram_size = dram_size;
+
+	return 0;
 }
diff --git a/board/scalys/simc-t10xx/ddr_QT1040-1GB.c b/board/scalys/simc-t10xx/ddr_QT1040-1GB.c
new file mode 100644
index 0000000..e4fdcf6
--- /dev/null
+++ b/board/scalys/simc-t10xx/ddr_QT1040-1GB.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+ 
+DECLARE_GLOBAL_DATA_PTR;
+ 
+/* Values for QT1040 */ 
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 1,
+	.rank_density = 1073741824u,
+	.capacity = 1073741824u,
+	.device_width = 16,
+	.primary_sdram_width = 64,
+	.ec_sdram_width = 8,
+	.registered_dimm = 0,
+	.mirrored_dimm = 0,
+	.n_row_addr = 14,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 2,
+	.burst_lengths_bitmask = 0x0c,
+	.tckmin_x_ps = 1250,
+	.caslat_x = (0x7fe << 4),
+	.taa_ps = 13750,
+	.twr_ps = 15000,
+	.trcd_ps = 13750,
+	.trrd_ps = 7500,
+	.trp_ps = 13750,
+	.tras_ps = 37500,
+	.trc_ps = 50600,
+	.trfc_ps = 160000,
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
+	.refresh_rate_ps = 3900000,
+	.tfaw_ps = 50000,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	int i;
+	
+	if (ctrl_num != 0) {
+		printf("Only 1 memory controller supported, but %i requested\n",
+		       ctrl_num);
+		return; 
+	}
+	
+	if (pdimm == NULL ) {
+		printf("Error, no valid dimm pararmeter supplied\n");
+		return;
+	}
+
+	if (!pdimm->n_ranks) {
+		printf("No ranks in dimm parameters. Configuration error?\n");
+		return;
+	}
+	
+	/* DDR speed is fixed in the RCW */
+
+	/* set odt_rd_cfg and odt_wr_cfg. */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		popts->cs_local_opts[i].odt_wr_cfg = 4;
+	}
+	
+	popts->half_strength_driver_enable = 0; /* */
+
+	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+	popts->wrlvl_start  = 5;
+	popts->wrlvl_ctl_2 = 0x05050506;
+	popts->wrlvl_ctl_3 = 0x06060605; /* 1333MT/s */
+	
+ 	popts->ddr_cdr1 = 0x800c0000;
+ 	popts->ddr_cdr2 = 0x00000001;
+	
+	/*
+	 * rtt and rtt_wr override
+	 */
+	popts->rtt_override = 0; /* */
+	
+	/* Enable ZQ calibration */
+	popts->zq_en = 1; /* */
+
+	/* Clock is launched 1/2 applied cycle after address/command */
+	popts->clk_adjust = 4; 
+	
+	/* Optimized cpo */
+	popts->cpo_sample = 0x33;
+}
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			    unsigned int controller_number,
+			    unsigned int dimm_number)
+{
+	const char dimm_model[] = "Soldered-down discrete DDR3";
+	
+	if (((controller_number == 0) && (dimm_number == 0)) ||
+		((controller_number == 1) && (dimm_number == 0))) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+	
+	return 0;
+}
+
+int test123(void){
+	{
+		volatile int waitforme = 0;
+		
+		while (waitforme) {
+			asm volatile ("nop");
+		}
+	}
+	return 0;
+}
+
+
+int dram_init(void)
+{
+	phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+	uint32_t regval;
+	
+	/* Remove reset of DDR using GPIO pin. We do this manually since
+	 * we have not yet access to the DM gpio at this time */
+	/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */
+	
+#define CONFIG_SYS_MPC85XX_GPIO2_ADDR	(CONFIG_SYS_IMMR + 0x131000)
+#define DDR_RST_N			(12)
+/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */
+/* #define DDR_RST_N     MPC85XX_GPIO_NR(2, 12) */
+
+	/* Set output */
+	regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8);
+	regval |= (0x80000000 >> 12);
+	out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8, regval);
+	
+	/* Set direction to acivate gpio pin */
+	regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR);
+	regval |= (0x80000000 >> 12);
+	out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR, regval);
+	
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+#else
+	/* DDR has been initialised by SPL loader */
+	dram_size =  fsl_ddr_sdram_size();
+#endif
+	
+	test123();
+	
+	gd->ram_size = dram_size;
+	
+	return 0;
+}
+
diff --git a/board/scalys/simc-t10xx/dragonfruit.c b/board/scalys/simc-t10xx/dragonfruit.c
index 0ae849c..c8e5a13 100644
--- a/board/scalys/simc-t10xx/dragonfruit.c
+++ b/board/scalys/simc-t10xx/dragonfruit.c
@@ -1,53 +1,68 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+
 #include <common.h>
 #include <asm-generic/gpio.h>
 
 #include "dragonfruit.h"
 
-
 /*
  * SERDER MUX Configuration pins:
  * IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL
  * IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL
  * IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL
- * 
+ */
+#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
+#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
+#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
+#define SERDES_CLK_OE  MPC85XX_GPIO_NR(2, 29)
+
+/* 
  * MUX_SER0_1_SEL
  * 	0: SERDES A => Slot1, lane 0
  *	   SERDES B => Slot1, lane 1
  *	1: SERDES A => CS4315 retimer => SFP+ 0
  * 	   SERDES B => CS4315 retimer => SFP+ 1
-  * 
+ */
+#define SER_0_1_SLOT1	0
+#define SER_0_1_SFP01	1
+
+/* 
  * MUX_SER2_3_SEL
  * 	0: SERDES C => Slot1, lane 2
  * 	   SERDES D => Slot1, lane 3
  * 	1: SERDES C => QSFP+ 2
  * 	   SERDES D => QSFP+ 3
- * 
+ */
+#define SER_2_3_SLOT1	0
+#define SER_2_3_SFP23	2
+
+/* 
  * SERDES E => Slot 4, lane 0 
- *
- * MUX_SER5_6_SEL
+ */
+
+/* MUX_SER5_6_SEL
  *	0: SERDES F => SLOT4, lane 1
  *	   SERDES G => SLOT4, lane 2
  * 	1: SERDES F => SLOT2
  *	   SERDES G => SLOT3
- * 
- * SERDES H => Slot 4, lane 3
  */
+#define SER_5_6_SLOT4	0
+#define SER_5_6_SLOT23	4
 
-#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
-#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
-#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
-#define SERDES_CLK_OE  MPC85XX_GPIO_NR(2, 29)
+/* 
+ * SERDES H => Slot 4, lane 3
+ */
 
 int scalys_carrier_setup_muxing(int serdes_config)
 {
 	int ret = 0;
+	int mux_config = 0;
 
 	ret = gpio_request(MUX_SER0_1_SEL, "mux_ser0_1_sel");
 	if (ret != 0) {
@@ -56,34 +71,121 @@ int scalys_carrier_setup_muxing(int serdes_config)
 	gpio_request(MUX_SER2_3_SEL, "mux_ser2_3_sel");
 	gpio_request(MUX_SER5_6_SEL, "mux_ser5_6_sel");
 	gpio_request(SERDES_CLK_OE, "serdes_clk_oe");
-
+	
+	
+	/* 
+	 * SERDES options for each target as supported by the dragonfruit 
+	 * carrier board. Refer to the QorIQ reference manual for the SERDES options table 
+	 * and all relevant information.
+	 * 
+	 * Note: The SERDES lanes A&B, C&D, and F&G can only be switched 
+	 * as pairs using the multiplexers. Which means some SERDES options are only partly usable.
+	 * 
+	 * Note/TODO: SERDES PLL2 must be powered down using SRDS_PLL_PD_S1 when
+	 * SRDS_PRTCL_S1 is any of the following values: 0x00, 0x40, 0x60, 0x67, 
+	 * 0x85, 0x87, 0x8D, 0x45.
+	 * 
+	 */
 	switch(serdes_config){
-	case 0x06:
-		/* A-D: PCIe1 (5/2.5G); E: PCIe2 (5/2.5G);
-		 * F: PCIe3 (5/2.5G); G: PCIe4 (5/2.5); H: SATA.1 (3/1.5G) */
-		gpio_direction_output(MUX_SER0_1_SEL, 0);
-		gpio_direction_output(MUX_SER2_3_SEL, 0);
-		gpio_direction_output(MUX_SER5_6_SEL, 1);
-
+#if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1020)
+/* With Ethernet Switch (T1040/T1020 only) */
+	//case 0x69:
+	//case 0x67: /* See note 2 */
+	case 0x60: /* See note 2 */
+		mux_config = SER_5_6_SLOT4 | SER_2_3_SFP23 | SER_0_1_SFP01;
+		break;
+	//case 0x8D: /* See note 2 */
+	//case 0x8E:
+	//case 0x66:
+	case 0x89:
+		/* A: unused; B: sg.s3; C: sg.s1; D: sg.s2;
+		 * E: PCIe2 (5/2.5G); F: PCIe3 (5/2.5G); G: unused; H: SATA1(3/1.5G) */
+		mux_config = SER_5_6_SLOT23 | SER_2_3_SFP23 | SER_0_1_SFP01;
 		break;
 	case 0x81:
+		/* A: Unused; B: sg.m3/sg.s3; C: sg.m1/sg.s1; D: sg.m2/sg.s2;
+		 * E: PCIe2 (5/2.5G); F: unused; G: unused; H: SATA1(3/1.5G) */
+	//case 0x88: /* Option has been verified to work, but is not officially supported */
+		/* A: Unused; B: sg.m3; C: sg.m1; D: sg.m2;
+		 * E: PCIe2 (5/2.5G); F: unused; G: SATA.2(3/1.5G); H: SATA1(3/1.5G) */
+		mux_config = SER_5_6_SLOT4 | SER_2_3_SFP23 | SER_0_1_SFP01;
+		break;
+#elif defined(CONFIG_PPC_T1042) || defined(CONFIG_PPC_T1022)
 	case 0x86:
+		/* A: Unused; B: sg.m3; C: sg.m1; D: sg.m2;
+		 * E: PCIe2 (5/2.5G); F: PCIe3 (5/2.5G); G: PCIe4 (5/2.5G); H: SATA1(3/1.5G) */
+		mux_config = SER_5_6_SLOT23 | SER_2_3_SFP23 | SER_0_1_SFP01;
+		break;
+	case 0x81:
+		/* A: Unused; B: sg.m3/sg.s3; C: sg.m1/sg.s1; D: sg.m2/sg.s2;
+		 * E: PCIe2 (5/2.5G); F: unused; G: unused; H: SATA1(3/1.5G) */
 	case 0x88:
-	case 0x89:
-		/* A: PCIe1 (5/2.5G); B: sg.m3; C: sg.m1; D: sg.m2;
-		 * E: PCIe2 (5/2.5G); F:PCIe3 (5/2.5G); G: SATA2(3/1.5G);
-		 * H: SATA1(3/1.5G) */
+		/* A: Unused; B: sg.m3; C: sg.m1; D: sg.m2;
+		 * E: PCIe2 (5/2.5G); F: unused; G: SATA.2(3/1.5G); H: SATA1(3/1.5G) */
+		mux_config = SER_5_6_SLOT4 | SER_2_3_SFP23 | SER_0_1_SFP01;
+		break;
+	case 0x06:
+		/* A-D: PCIe1 (5/2.5G); 
+		 * E: PCIe2 (5/2.5G); F: PCIe3 (5/2.5G); G: PCIe4 (5/2.5G); H: SATA.1 (3/1.5G) */
+		mux_config = SER_5_6_SLOT23 | SER_2_3_SLOT1 | SER_0_1_SLOT1;
+		break;
+	//case 0x08:
+	//case 0x87: /* See note 2 */
+	//case 0xA7:
+	//case 0xAA:
+	//case 0xA2:
+	//case 0x45:
+	//case 0x40: /* See note 2 */
+	//case 0x8E:
+	//case 0x85: /* See note 2 */
+	//case 0xA5:
+	//case 0x00: /* See note 2 */
+#else
+#error "Invalid or unspecified target cpu for dragonfruit carrier board!"
+#endif
+	default:
+		printf("Unsupported SERDES configuration (%02x) detected for dragonfruit carrier board (Warning: Using default multiplexer settings)!\n", serdes_config);
+	}
+	
+	printf("-----------------------------------------------------\n");
+	printf("Serdes lane configuration:\n");
+	if ((mux_config & 1) > 0) {
 		gpio_direction_output(MUX_SER0_1_SEL, 1);
+		printf("A: SFP slot 0 (T2081 only)\n");
+		printf("B: SFP slot 1\n");
+	} else {
+		gpio_direction_output(MUX_SER0_1_SEL, 0);
+		printf("A: PCIe slot 1 on lane 0\n");
+		printf("B: PCIe slot 1 on lane 1\n");
+	}
+	
+	if ((mux_config & 2) > 0) {
 		gpio_direction_output(MUX_SER2_3_SEL, 1);
+		printf("C: SFP slot 2\n");
+		printf("D: SFP slot 3\n");
+	} else {
+		gpio_direction_output(MUX_SER2_3_SEL, 0);
+		printf("C: PCIe slot 1 on lane 2\n");
+		printf("D: PCIe slot 1 on lane 3\n");
+	}
+	
+	printf("E: PCIe slot 4 on lane 0\n");
+	
+	if ((mux_config & 4) > 0) {
 		gpio_direction_output(MUX_SER5_6_SEL, 1);
-
-		break;
-	default:
-		printf("Unsupported SERDES configuration (%02x)\n", serdes_config);
+		printf("F: PCIe slot 2 on lane 0\n");
+		printf("G: PCIe slot 3 on lane 0\n");
+	} else {
+		gpio_direction_output(MUX_SER5_6_SEL, 0);
+		printf("F: PCIe slot 4 on lane 1\n");
+		printf("G: PCIe slot 4 on lane 2\n");
 	}
+	
+	printf("H: PCIe slot 4 on lane 3\n");
+	printf("-----------------------------------------------------\n");
 
 	/* Enable serdes clock */
 	gpio_direction_output(SERDES_CLK_OE, 1);
 
 	return ret;
-}
\ No newline at end of file
+}
diff --git a/board/scalys/simc-t10xx/dragonfruit.h b/board/scalys/simc-t10xx/dragonfruit.h
index 900b2e4..12928b4 100644
--- a/board/scalys/simc-t10xx/dragonfruit.h
+++ b/board/scalys/simc-t10xx/dragonfruit.h
@@ -1,6 +1,14 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
 #ifndef _DRAGON_FRUIT_H
 #define _DRAGON_FRUIT_H
 
 int scalys_carrier_setup_muxing(int serdes_config);
 
-#endif /* _DRAGON_FRUIT_H */
\ No newline at end of file
+#endif /* _DRAGON_FRUIT_H */
diff --git a/board/scalys/simc-t10xx/eth.c b/board/scalys/simc-t10xx/eth.c
index 2f5c401..2b548f1 100644
--- a/board/scalys/simc-t10xx/eth.c
+++ b/board/scalys/simc-t10xx/eth.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  *
  * SPDX-License-Identifier:	GPL-2.0+
@@ -7,17 +7,6 @@
 
 #include <common.h>
 #include <netdev.h>
-#include <asm/immap_85xx.h>
-#include <fm_eth.h>
-#include <fsl_mdio.h>
-#include <malloc.h>
-#include <i2c.h>
-
-
-
-
-#include <common.h>
-#include <netdev.h>
 #include <asm/fsl_serdes.h>
 #include <asm/immap_85xx.h>
 #include <fm_eth.h>
@@ -25,11 +14,7 @@
 #include <malloc.h>
 #include <fsl_dtsec.h>
 #include <vsc9953.h>
-
-//#include "../common/fman.h"
-//#include "../common/qixis.h"
-
-
+#include <i2c.h>
 
 
 #include "../../freescale/common/fman.h"
@@ -53,16 +38,24 @@ int board_eth_init(bd_t *bis)
 	int phy_addr = 0;
 	
 #ifdef CONFIG_VSC9953
-	int lane;
-	phy_interface_t phy_int;
-	struct mii_dev *bus;
+	/*phy_interface_t phy_int;*/
+	/*struct mii_dev *bus;*/
 	struct ccsr_scfg *scfg;
 #endif
 	
 	uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
 	uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
+	uint32_t *gpio4_gpdir = (uint32_t *) 0xffe133000;
+	uint32_t *gpio4_gpdat = (uint32_t *) 0xffe133008;
 	uint32_t regval;
 	
+	/* Try to read a byte from te carrier eeprom te determine if were on the correct carrier */
+	ret = i2c_read(0x54, 0, 2, &i2c_data, 1 );
+	if (ret != 0) {
+		printf("No dragonfruit carrier detected\n");
+		return 0;
+	}
+	
 	printf("Initializing Fman\n");
 
 	memac_mdio_info.regs =
@@ -72,11 +65,24 @@ int board_eth_init(bd_t *bis)
 	/* Register the real 1G MDIO bus */
 	fm_memac_mdio_init(bis, &memac_mdio_info);
 
-	/* Remove reset from Ethernet PHY's 
-	 * IFC_PERR_B : GPIO2_15 : eth1_reset
-	 * IFC_CS_N2  : GPIO2_11 : eth2_reset */
-//	gpio_set_value(2, 0);
-
+   /* Marvell 88E1111 Setup
+	* 
+	* Remove reset from Ethernet PHY's 
+	* 
+	* Carrier board v1.x:
+	* IFC_PERR_B : GPIO2_15 : eth1_reset
+	* IFC_CS_N2  : GPIO2_11 : eth2_reset 
+	*
+	* Carrier board v2.x:
+	* IFC_PERR_B : GPIO2_15 : eth1_reset
+	* IFC_CS_N2  : GPIO4_09 : eth2_reset
+	* 
+	* Note: make sure gpio pins are configured as gpio in RCW! 
+	*/
+
+#if 0 
+	/* TODO: use EEPROM data to chose carrier board version */
+	/* Carrier board v1.x */
 	/* Clear outputs to activate reset */
 	regval = in_be32(gpio2_gpdat);
 	regval &= ~((0x80000000 >> 11 ) | (0x80000000 >> 15));
@@ -94,11 +100,44 @@ int board_eth_init(bd_t *bis)
 	regval = in_be32(gpio2_gpdat);
 	regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15));
 	out_be32(gpio2_gpdat, regval);
-
+#else
+	/* Carrier board v2.x */
+	/* Clear outputs to activate reset */
+	regval = in_be32(gpio2_gpdat);
+	regval &= ~(0x80000000 >> 15);
+	out_be32(gpio2_gpdat, regval);
+	regval = in_be32(gpio4_gpdat);
+	regval &= ~(0x80000000 >> 9);
+	out_be32(gpio4_gpdat, regval);
+	
+	/* Set outputs to output mode */
+	regval = in_be32(gpio2_gpdir);
+	regval |= (0x80000000 >> 15);
+	out_be32(gpio2_gpdir, regval);
+	regval = in_be32(gpio4_gpdir);
+	regval |= (0x80000000 >> 9);
+	out_be32(gpio4_gpdir, regval);
+	
+	/* Wait for 10 ms to to meet reset timing */
+	mdelay(10);
+	
+	/* Set outputs to de-activate reset */
+	regval = in_be32(gpio2_gpdat);
+	regval |= (0x80000000 >> 15);
+	out_be32(gpio2_gpdat, regval);
+	regval = in_be32(gpio4_gpdat);
+	regval |= (0x80000000 >> 9);
+	out_be32(gpio4_gpdat, regval);
+#endif
+	
+	/* Write 0x4111 to reg 0x18 on both PHYs to change LEDs usage */
+	miiphy_write("FSL_MDIO0",0,0x18,0x4111);
+	miiphy_write("FSL_MDIO0",1,0x18,0x4111);
 
 	/* Remove SFP TX_disable */
 	i2c_set_bus_num(0);
-	i2c_data = 0x3b;
+	ret = i2c_read(0x22, 0x0E, 1, &i2c_data, 1);
+	i2c_data &= ~0x04;
 	ret = i2c_write(0x22, 0x0E, 1, &i2c_data, 1);
 
 	mdelay(100);
@@ -163,9 +202,9 @@ int board_eth_init(bd_t *bis)
 	
 #ifdef CONFIG_VSC9953
 	for (i = 0; i < VSC9953_MAX_PORTS; i++) {
-		int lane = -1;
-		int phy_addr = 0;
-		int phy_int = PHY_INTERFACE_MODE_NONE;
+		/*int lane = -1;*/
+		/*int phy_addr = 0;*/
+		/*int phy_int = PHY_INTERFACE_MODE_NONE;*/
 		switch (i) {
 		case 0:
 		case 1:
@@ -193,7 +232,7 @@ int board_eth_init(bd_t *bis)
 			vsc9953_port_enable(i);
 			break;
 		}
-		bus = lane;
+		/*bus = lane;*/
 
 	}
 #endif
diff --git a/board/scalys/simc-t10xx/law.c b/board/scalys/simc-t10xx/law.c
index c3b5e85..df823d1 100644
--- a/board/scalys/simc-t10xx/law.c
+++ b/board/scalys/simc-t10xx/law.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  * 
  * Copyright 2013 Freescale Semiconductor, Inc.
@@ -29,4 +29,4 @@ struct law_entry law_table[] = {
 #endif
 };
 
-int num_law_entries = ARRAY_SIZE(law_table);
\ No newline at end of file
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/scalys/simc-t10xx/pci.c b/board/scalys/simc-t10xx/pci.c
index ab9edbb..9a02f90 100644
--- a/board/scalys/simc-t10xx/pci.c
+++ b/board/scalys/simc-t10xx/pci.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  * 
  * Copyright 2013 Freescale Semiconductor, Inc.
@@ -22,11 +22,16 @@ void pci_init_board(void)
 	uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008;
 	uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
 	uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
-	uint32_t regval;
-
-	debug("%s\n", __FUNCTION__);
+	uint32_t regval;	
+	
+	/*debug("%s\n", __FUNCTION__);*/
 	
-	//TODO, when present pins are available on the board, use them to enable only active slots
+	/*TODO, when present pins are available on the board, use them to enable only active slots*/
+	
+#if 0
+	/* Dragonfruit Carrier board 1.x */
+
+
 	/* 
 	 * IRQ[0-3] : PCIe present detect signals
 	 * IRQ[0] : SLOT1_PRSNT2_N : XXX
@@ -51,7 +56,47 @@ void pci_init_board(void)
 	regval |= ( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) );
 	out_be32(gpio1_gpdir, regval);
 	
+#else
+	/* Dragonfruit Carrier board 2.x */
+	/* 
+	 * PCIe present detect signals:
+	 * IRQ[3] : GPIO1_23 : SLOT1_PRSNT2_N
+	 * IRQ[4] : GPIO1_24 : SLOT2_PRSNT2_N
+	 * IRQ[5] : GPIO1_25 : SLOT3_PRSNT2_N
+	 * IRQ[10] : GPIO1_30 : SLOT4_PRSNT2_N
+	 * 
+	 * Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7 
+	 * IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N (used for all 4 slots)
+	 * IFC_PAR1 : GPIO2_14 : PEX_REFCLK_SEL
+	 */
+	
+	/* Set output to 0 to enable reference clocks */
+	regval = in_be32(gpio1_gpdat);
+	regval &= ~( 0x80000000 >> 12 );
+	out_be32(gpio1_gpdat, regval);
 	
+	/* Set Enable outputs */
+	regval = in_be32(gpio1_gpdir);
+	regval |= ( 0x80000000 >> 12 );
+	out_be32(gpio1_gpdir, regval);
+	
+	/* Set PEX_REFCLK_SEL to 0 to select CLK0  */
+
+	/* Set IFC_PAR1 to output mode */
+	regval = in_be32(gpio2_gpdir);
+	regval |= ( 0x80000000 >> 14 );
+	out_be32(gpio2_gpdir, regval);
+
+	/* Set output to 0 to select clock source 0 */
+	regval = in_be32(gpio2_gpdat);
+	regval &= ~( 0x80000000 >> 14 );
+	out_be32(gpio2_gpdat, regval);
+
+#endif
+	
+	/*
+	 * IFC_PAR0 : GPIO2_13 : PEX_PERST_N
+	 */
 
 	/* Remove reset from PCIe devices */
 
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg
new file mode 100644
index 0000000..48b9f68
--- /dev/null
+++ b/board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+
+0c0a000c 0c000000 00000000 00000000 
+81000002 40000002 e8105000 21000000 
+00000000 cafebabe 00000000 00030ffc 
+00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg
new file mode 100644
index 0000000..5cf027e
--- /dev/null
+++ b/board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+0c0a000c 0c000000 00000000 00000000 
+81000002 40000002 e8023000 21000000 
+00000000 cafebabe 00000000 00030ffc 
+00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg
new file mode 100644
index 0000000..b5cc904
--- /dev/null
+++ b/board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+0c0a000c 0c000000 00000000 00000000
+81000002 40000002 68105000 21000000
+00000000 cafebabe 00000000 00030ffc
+00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg b/board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg
new file mode 100644
index 0000000..dfc4250
--- /dev/null
+++ b/board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg
@@ -0,0 +1,9 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+0c0a000c 0c000000 00000000 00000000 
+81000002 40000002 58105000 21000000 
+00000000 cafebabe 00000000 00030ffc 
+00000314 00005005 00000000 00000000
+
+#58505000 / 58105000
diff --git a/board/scalys/simc-t10xx/simc-t1022_rcw.cfg b/board/scalys/simc-t10xx/simc-t1022_rcw.cfg
deleted file mode 100644
index 1ddbe0c..0000000
--- a/board/scalys/simc-t10xx/simc-t1022_rcw.cfg
+++ /dev/null
@@ -1,17 +0,0 @@
-#PBL preamble and RCW header
-AA55AA55 010E0100
-#
-#120C0015 15000000 00000000 00000000
-#06000000 00C00002 E8104000 21000000
-#00000000 CAFEBABE 00000000 00030ffc
-#00000314 0014500C 00000000 00000000
-#
-#120C0015 15000000 00000000 00000000
-#06000000 00000002 E8105000 21000000
-#00000000 CAFEBABE 00000000 00230FFC
-#00000714 0014500C 00000000 00000000
-
-120C0015 15000000 00000000 00000000
-86000000 00000002 E8104000 21000000
-00000000 CAFEBABE 00000000 00030FFC
-00000314 0014500C 00000000 00000000
diff --git a/board/scalys/simc-t10xx/simc-t1040_rcw.cfg b/board/scalys/simc-t10xx/simc-t1040_rcw.cfg
deleted file mode 100644
index 323ea71..0000000
--- a/board/scalys/simc-t10xx/simc-t1040_rcw.cfg
+++ /dev/null
@@ -1,7 +0,0 @@
-#PBL preamble and RCW header
-AA55AA55 010E0100
-#
-0A0C000C 0C000000 00000000 00000000
-81000002 00400002 E8105000 21000000
-00000000 CAFEBABE 00000000 00030FFC
-00000314 0014500C 00000000 00000000
diff --git a/board/scalys/simc-t10xx/simc-t10x0_nand_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_nand_rcw.cfg
new file mode 100644
index 0000000..ccb3509
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10x0_nand_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+
+0c0c000c 0c000000 00000000 00000000 
+81000002 40000002 e8105000 21000000 
+00000000 cafebabe 00000000 00030ffc 
+00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/simc-t1040_nand_secure_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_nand_secure_rcw.cfg
index 6a69289..6f0ec4d 100644
--- a/board/scalys/simc-t10xx/simc-t1040_nand_secure_rcw.cfg
+++ b/board/scalys/simc-t10xx/simc-t10x0_nand_secure_rcw.cfg
@@ -1,7 +1,7 @@
 #PBL preamble and RCW header
 AA55AA55 010E0100
 #
-0A0C000C 0C000000 00000000 00000000
+0c0C000C 0C000000 00000000 00000000
 # HOLDOFF         E8705000
 # core 0 enabled  E8305000
 # PBL disabled    F8505000
@@ -9,6 +9,6 @@ AA55AA55 010E0100
 
 #Holdoff enabled, PBL enabled No secure boot E8505000
 #Holdoff enabled, PBL enabled with secure boot E8705000
-81000002 00400002 E8305000 21000000
-00000000 CAFEBABE 00000000 00030FFC
-00000314 0014500C 00000000 00000000
\ No newline at end of file
+81000002 40000002 e8305000 21000000 
+00000000 cafebabe 00000000 00030ffc 
+00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/simc-t10x0_nor_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_nor_rcw.cfg
new file mode 100644
index 0000000..a63c1f2
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10x0_nor_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+0c0c000c 0c000000 00000000 00000000 
+81000002 40000002 e8023000 21000000 
+00000000 cafebabe 00000000 00030ffc 
+00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/simc-t10x0_sdhc_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_sdhc_rcw.cfg
new file mode 100644
index 0000000..61236ed
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10x0_sdhc_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+0c0c000c 0c000000 00000000 00000000
+81000002 40000002 68105000 21000000
+00000000 cafebabe 00000000 00030ffc
+00000314 00005005 00000000 00000000
diff --git a/board/scalys/simc-t10xx/simc-t10x0_spi_rcw.cfg b/board/scalys/simc-t10xx/simc-t10x0_spi_rcw.cfg
new file mode 100644
index 0000000..dba4882
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10x0_spi_rcw.cfg
@@ -0,0 +1,9 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+0c0c000c 0c000000 00000000 00000000 
+81000002 40000002 58105000 21000000 
+00000000 cafebabe 00000000 00030ffc 
+00000314 00005005 00000000 00000000
+
+#58505000 / 58105000
diff --git a/board/scalys/simc-t10xx/simc-t10xx.c b/board/scalys/simc-t10xx/simc-t10xx.c
index 46c5677..2f9b8d3 100644
--- a/board/scalys/simc-t10xx/simc-t10xx.c
+++ b/board/scalys/simc-t10xx/simc-t10xx.c
@@ -1,10 +1,11 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+
 #include <common.h>
 #include <command.h>
 #include <netdev.h>
@@ -31,7 +32,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int checkboard(void)
 {
+#ifdef CONFIG_TARGET_QT1040_1GB
+	printf("Board: QT1040-1GB\n" );
+#else
 	printf("Board: simc-t10xx\n" );
+#endif
 	return 0;
 }
 
@@ -110,8 +115,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_liodn(blob);
 
 #ifdef CONFIG_HAS_FSL_DR_USB
-	debug( "fdt_fixup_dr_usb\n" );
-	fdt_fixup_dr_usb(blob, bd);
+	debug( "fsl_fdt_fixup_dr_usb\n" );
+	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
@@ -141,3 +146,8 @@ void board_detail(void)
 	do_bcdinfo();
 }
 #endif
+
+void board_reset(void)
+{
+	printf("U-boot reset command not implemented.\n");
+}
diff --git a/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg b/board/scalys/simc-t10xx/simc-t10xx_nand_pbi.cfg
index c5fd95d..ad31c5b 100644
--- a/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg
+++ b/board/scalys/simc-t10xx/simc-t10xx_nand_pbi.cfg
@@ -30,13 +30,14 @@
 # (IFC_CSPR1)
 09124010 ff8000c3
 #  IFC_CSOR_NAND
-09124130 0108a100
+09124130 85084101
 #  IFC_FTIM0_CS0_NAND to IFC_FTIM0_CS0_NAND 
 091241c0 181c080c
 091241c4 3850141a
 091241c8 03008028
 091241cc 28000000
-# Set IFC_CCR clkdiv to 6 (IFC clock to platform clock/6=83.3MHz)
-0912444c 05008000
+# Set IFC_CCR clkdiv to 2 (=/3) to get: 
+# (platform clock/2/3=83.3MHz)
+0912444c 02008000
 #Flush PBL data (Wait 0xFFFFF cycles )
 091380c0 000fffff
\ No newline at end of file
diff --git a/board/scalys/simc-t10xx/simc-t10xx_nor_pbi.cfg b/board/scalys/simc-t10xx/simc-t10xx_nor_pbi.cfg
new file mode 100644
index 0000000..1e7a20e
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10xx_nor_pbi.cfg
@@ -0,0 +1,44 @@
+#PBI commands
+#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
+09250100 00000400
+09250108 00002000
+#Software Workaround for errata A-008007 to reset PVR register
+09000010 0000000b
+09000014 c0000000
+09000018 81d00017
+89020400 a1000000
+091380c0 000f0000
+89020400 00000000
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1 (LAW 13)
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+
+#Configure IFC controller
+# (IFC_CSPR1)
+#09124010 ff8000c3
+#  IFC_CSOR_NAND
+#09124130 0108a100
+#  IFC_FTIM0_CS0_NAND to IFC_FTIM0_CS0_NAND 
+#091241c0 181c080c
+#091241c4 3850141a
+#091241c8 03008028
+#091241cc 28000000
+
+# Set IFC_CCR clkdiv to 6 (IFC clock to platform clock/6=83.3MHz)
+0912444c 05008000
+#Flush PBL data (Wait 0xFFFFF cycles )
+091380c0 000fffff
\ No newline at end of file
diff --git a/board/scalys/simc-t10xx/simc-t10xx_sdhc_pbi.cfg b/board/scalys/simc-t10xx/simc-t10xx_sdhc_pbi.cfg
new file mode 100644
index 0000000..51945b4
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10xx_sdhc_pbi.cfg
@@ -0,0 +1,36 @@
+#PBI commands
+#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
+09250100 00000400
+09250108 00002000
+#Software Workaround for errata A-008007 to reset PVR register
+09000010 0000000b
+09000014 c0000000
+09000018 81d00017
+89020400 a1000000
+091380c0 000f0000
+89020400 00000000
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 081e000d
+09010000 80000000
+#Configure LAW for CPC1
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+091380c0 000FFFFF
diff --git a/board/scalys/simc-t10xx/simc-t10xx_spi_pbi.cfg b/board/scalys/simc-t10xx/simc-t10xx_spi_pbi.cfg
new file mode 100644
index 0000000..51945b4
--- /dev/null
+++ b/board/scalys/simc-t10xx/simc-t10xx_spi_pbi.cfg
@@ -0,0 +1,36 @@
+#PBI commands
+#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
+09250100 00000400
+09250108 00002000
+#Software Workaround for errata A-008007 to reset PVR register
+09000010 0000000b
+09000014 c0000000
+09000018 81d00017
+89020400 a1000000
+091380c0 000f0000
+89020400 00000000
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 256KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 081e000d
+09010000 80000000
+#Configure LAW for CPC1
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+091380c0 000FFFFF
diff --git a/board/scalys/simc-t10xx/spl.c b/board/scalys/simc-t10xx/spl.c
index 3675169..c861284 100644
--- a/board/scalys/simc-t10xx/spl.c
+++ b/board/scalys/simc-t10xx/spl.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  * 
  * Copyright 2013 Freescale Semiconductor, Inc.
@@ -10,10 +10,11 @@
 #include <common.h>
 #include <malloc.h>
 #include <ns16550.h>
+#include <console.h>
 #include <nand.h>
-#include <i2c.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
+#include <i2c.h>
 #include <spi_flash.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -61,9 +62,40 @@ void board_init_f(ulong bootflag)
 	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
 }
 
+void setup_ifc_nand(enum ifc_chip_sel cs)
+{
+	set_ifc_cspr_ext(cs, CONFIG_SYS_NAND_CSPR_EXT);
+	set_ifc_csor	(cs, CONFIG_SYS_NAND_CSOR);
+	set_ifc_amask	(cs, CONFIG_SYS_NAND_AMASK);
+	set_ifc_cspr	(cs, CONFIG_SYS_NAND_CSPR);
+	set_ifc_ftim	(cs, IFC_FTIM0, CONFIG_SYS_NAND_FTIM0);
+	set_ifc_ftim	(cs, IFC_FTIM1, CONFIG_SYS_NAND_FTIM1);
+	set_ifc_ftim	(cs, IFC_FTIM2, CONFIG_SYS_NAND_FTIM2);
+	set_ifc_ftim	(cs, IFC_FTIM3, CONFIG_SYS_NAND_FTIM3);
+	set_ifc_csor_ext(cs, 0);
+
+}
+
+void setup_ifc_nor(enum ifc_chip_sel cs)
+{
+	set_ifc_cspr_ext(cs, CONFIG_SYS_NOR_CSPR_EXT);
+	set_ifc_csor	(cs, CONFIG_SYS_NOR_CSOR);
+	set_ifc_amask	(cs, CONFIG_SYS_NOR_AMASK);
+	set_ifc_cspr	(cs, CONFIG_SYS_NOR_CSPR);
+	set_ifc_ftim	(cs, IFC_FTIM0, CONFIG_SYS_NOR_FTIM0);
+	set_ifc_ftim	(cs, IFC_FTIM1, CONFIG_SYS_NOR_FTIM1);
+	set_ifc_ftim	(cs, IFC_FTIM2, CONFIG_SYS_NOR_FTIM2);
+	set_ifc_ftim	(cs, IFC_FTIM3, CONFIG_SYS_NOR_FTIM3);
+	set_ifc_csor_ext(cs, 0);
+}
+
 void board_init_r(gd_t *gd, ulong dest_addr)
 {
 	bd_t *bd;
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	uint32_t boot_source;
+	
+	__attribute__((noreturn)) void (*boot)(void) = hang;
 
 	bd = (bd_t *)(gd + sizeof(gd_t));
 	memset(bd, 0, sizeof(bd_t));
@@ -71,11 +103,80 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
 	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
 
-	probecpu();
+	arch_cpu_init();
 	get_clocks();
 	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
 			CONFIG_SPL_RELOC_MALLOC_SIZE);
 
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+
+	dram_init();
+
+	/* Get the boot source from the Power On Status Register (set by QSC) */
+	boot_source = (in_be32(&gur->porsr1) >> 23);
+
+	switch (boot_source) {
+	case 0x23:
+		/* NOR boot */
+		setup_ifc_nor(IFC_CS0);
+		setup_ifc_nand(IFC_CS1);
+
+		memcpy((void*)CONFIG_SYS_NAND_U_BOOT_DST, (void*) CONFIG_SYS_FLASH_BASE + CONFIG_SPL_PAD_TO, CONFIG_SYS_NAND_U_BOOT_SIZE);
+
+		flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+		boot = (void*) CONFIG_SYS_NAND_U_BOOT_START;
+		break;
+
+	case 0x45:
+#if 0
+		/*SPI nor flash */
+		setup_ifc_nand(IFC_CS0);
+		setup_ifc_nor(IFC_CS1);
+		//fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, (uchar *)CONFIG_ENV_ADDR);
+		{
+			struct spi_flash *flash;
+
+			flash = spi_flash_probe(0, 0,
+				CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
+			if (flash == NULL) {
+				puts("\nspi_flash_probe failed");
+				hang();
+			}
+
+			spi_flash_read(flash, CONFIG_SPL_PAD_TO, CONFIG_SYS_NAND_U_BOOT_SIZE, (void*) CONFIG_SYS_NAND_U_BOOT_DST);
+		}
+#endif
+		printf("TODO, load u-boot from SPI....\n");
+		hang();
+		break;
+	case 0x40:
+		/* SD/MMC (eSDHC) boot */
+		#ifdef CONFIG_SPL_MMC_BOOT
+		setup_ifc_nand(IFC_CS0);
+		setup_ifc_nor(IFC_CS1);
+		
+		mmc_initialize(bd);
+		mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)CONFIG_ENV_ADDR);
+		boot = mmc_boot;
+		#endif
+		break;
+	case 0x105:
+		/* NAND boot */
+		setup_ifc_nand(IFC_CS0);
+		setup_ifc_nor(IFC_CS1);
+
+		nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+		    (uchar *)CONFIG_ENV_ADDR);
+		boot = nand_boot;
+		break;
+	default:
+		printf("Unknown boot source (%3x\n", boot_source);
+	break;
+	}
+	boot();
+#if 0
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_initialize(bd);
 #endif
@@ -85,6 +186,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 			    (uchar *)CONFIG_ENV_ADDR);
 #endif
+
 #ifdef CONFIG_SPL_MMC_BOOT
 	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
 			   (uchar *)CONFIG_ENV_ADDR);
@@ -109,4 +211,5 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 #elif defined(CONFIG_SPL_NAND_BOOT)
 	nand_boot();
 #endif
+#endif
 }
diff --git a/board/scalys/simc-t10xx/tlb.c b/board/scalys/simc-t10xx/tlb.c
index fa2dccb..e6edf51 100644
--- a/board/scalys/simc-t10xx/tlb.c
+++ b/board/scalys/simc-t10xx/tlb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * opensource@scalys.com
  * 
  * Copyright 2013 Freescale Semiconductor, Inc.
@@ -40,14 +40,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_256K, 1),
-
 #elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
 	/*
 	 * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot
 	 * the physical address of the SRAM is at 0xbffc0000,
 	 * and virtual address is 0xfffc0000
 	 */
-
 	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
 		      CONFIG_SYS_INIT_L3_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -66,8 +64,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
 	/* *I*G* - Flash, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
 	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
-		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_64M, 1),
 
 #ifndef CONFIG_SPL_BUILD
 #ifdef CONFIG_PCI
@@ -116,21 +114,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 10, BOOKE_PAGESZ_64K, 1),
 #endif
-#ifdef CONFIG_SYS_CPLD_BASE
-	SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 11, BOOKE_PAGESZ_256K, 1),
-#endif
 
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 12, BOOKE_PAGESZ_1G, 1),
+#if defined(CONFIG_SYS_SDRAM_SIZE)
+#if (CONFIG_SYS_SDRAM_SIZE >= 2048)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 13, BOOKE_PAGESZ_1G, 1)
 #endif
+#endif
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/scalys/simc-t2081/Kconfig b/board/scalys/simc-t2081/Kconfig
new file mode 100644
index 0000000..323ae5b
--- /dev/null
+++ b/board/scalys/simc-t2081/Kconfig
@@ -0,0 +1,9 @@
+if TARGET_SIMC_TXXXX && ARCH_T2081
+
+config SYS_BOARD
+	default "simc-t2081"
+
+config SYS_CONFIG_NAME
+	default "simc-t2081"	
+	
+endif
diff --git a/board/scalys/simc-t2081/Makefile b/board/scalys/simc-t2081/Makefile
new file mode 100644
index 0000000..730b5ad
--- /dev/null
+++ b/board/scalys/simc-t2081/Makefile
@@ -0,0 +1,19 @@
+# Copyright 2016 Scalys B.V.
+# opensource@scalys.com
+# 
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+UBOOTINCLUDE += -I$(srctree)/board/$(VENDOR)/common/
+
+ifdef CONFIG_SPL_BUILD
+obj-y	+= spl.o
+else
+obj-y	+= simc-t2081.o
+obj-y	+= eth.o
+obj-$(CONFIG_PCI)	+= pci.o
+endif
+obj-y	+= ddr.o
+obj-y	+= law.o
+obj-y	+= tlb.o
+obj-y	+= dragonfruit.o
diff --git a/board/scalys/simc-t2081/ddr.c b/board/scalys/simc-t2081/ddr.c
new file mode 100644
index 0000000..3d8821c
--- /dev/null
+++ b/board/scalys/simc-t2081/ddr.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* MT41K512M8RH-125 */
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 2,
+	.rank_density = 0x100000000ULL,
+	.capacity = 0x200000000ULL,
+	.primary_sdram_width = 64,
+	.ec_sdram_width = 8,
+	.registered_dimm = 0,
+	.mirrored_dimm = 1,
+	.n_row_addr = 16,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = EDC_ECC,
+	.burst_lengths_bitmask = 0x0c,
+	.tckmin_x_ps = 1250,
+	.tckmax_ps = 1499,
+	.caslat_x = (1 << 11),
+	.taa_ps = 13750,
+	.trcd_ps = 13750,
+	.trp_ps = 13750,
+	.tras_ps = 35000,
+	.trc_ps = 48750,
+	.tfaw_ps = 30000,
+	.twr_ps = 15000,
+	.trfc_ps = 260000,
+	.trrd_ps = 5000, //1Kb page size!
+	.twtr_ps = 7500,
+	.trtp_ps = 7500,
+	.refresh_rate_ps = 70200000,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+			   dimm_params_t *pdimm,
+			   unsigned int ctrl_num)
+{
+	int i;
+	
+	if (ctrl_num != 0) {
+		printf("Only 1 memory controller supported, but %i requested\n",
+		       ctrl_num);
+		return; 
+	}
+	
+	if (pdimm == NULL ) {
+		printf("Error, no valid dimm pararmeter supplied\n");
+		return;
+	}
+
+	if (!pdimm->n_ranks) {
+		printf("No ranks in dimm parameters. Configuration error?\n");
+		return;
+	}
+
+	/* set odt_rd_cfg and odt_wr_cfg. */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		popts->cs_local_opts[i].odt_wr_cfg = 4;
+	}
+
+	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 13;
+	popts->wrlvl_start  = 7; /* 7/8 clock delay */
+	popts->wrlvl_ctl_2 = 0x06070809;
+	popts->wrlvl_ctl_3 = 0x0d0f0a09;
+
+	popts->ddr_cdr1 = 0x800c0000;
+	popts->ddr_cdr2 = 0x00000001;
+
+	/* Clock is launched 1/2 applied cycle after address/command */
+	popts->clk_adjust = 8; 
+	
+	/* cpo optimization */
+	popts->cpo_sample = 0x46;
+}
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			    unsigned int controller_number,
+			    unsigned int dimm_number)
+{
+	const char dimm_model[] = "Soldered-down discrete DDR3";
+
+	if (((controller_number == 0) && (dimm_number == 0)) ||
+		((controller_number == 1) && (dimm_number == 0))) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+	
+	return 0;
+}
+
+int dram_init(void)
+{
+	phys_size_t dram_size;
+
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+	uint32_t regval;
+
+	/* Remove reset of DDR using GPIO pin. We do this manually since
+	 * we have not yet access to the DM gpio at this time */
+	/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */
+	
+#define CONFIG_SYS_MPC85XX_GPIO2_ADDR	(CONFIG_SYS_IMMR + 0x131000)
+#define DDR_RST_N			(12)
+/* DDR_RST_N => IFC_CS3_B => GPIO2_12 */
+/* #define DDR_RST_N     MPC85XX_GPIO_NR(2, 12) */
+
+	/* Set output */
+	regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8);
+	regval |= (0x80000000 >> 12);
+	out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR+0x8, regval);
+	
+	/* Set direction to acivate gpio pin */
+	regval = in_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR);
+	regval |= (0x80000000 >> 12);
+	out_be32((size_t*)CONFIG_SYS_MPC85XX_GPIO2_ADDR, regval);
+    
+	dram_size = fsl_ddr_sdram();
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+#else
+	/* DDR has been initialised by SPL loader */
+	dram_size =  fsl_ddr_sdram_size();
+#endif
+
+	gd->ram_size = dram_size;
+
+	return 0;
+}
diff --git a/board/scalys/simc-t2081/dragonfruit.c b/board/scalys/simc-t2081/dragonfruit.c
new file mode 100644
index 0000000..286b2c2
--- /dev/null
+++ b/board/scalys/simc-t2081/dragonfruit.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/gpio.h>
+#include "dragonfruit.h"
+
+/*
+ * SERDER MUX Configuration pins:
+ * IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL
+ * IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL
+ * IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL
+ */
+#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
+#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
+#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
+#define SERDES_CLK_OE  MPC85XX_GPIO_NR(2, 29)
+
+/* 
+ * MUX_SER0_1_SEL
+ * 	0: SERDES A => Slot1, lane 0
+ *	   SERDES B => Slot1, lane 1
+ *	1: SERDES A => CS4315 retimer => SFP+ 0
+ * 	   SERDES B => CS4315 retimer => SFP+ 1
+ */
+#define SER_0_1_SLOT1	0
+#define SER_0_1_SFP01	1
+
+/* 
+ * MUX_SER2_3_SEL
+ * 	0: SERDES C => Slot1, lane 2
+ * 	   SERDES D => Slot1, lane 3
+ * 	1: SERDES C => QSFP+ 2
+ * 	   SERDES D => QSFP+ 3
+ */
+#define SER_2_3_SLOT1	0
+#define SER_2_3_SFP23	2
+
+/* 
+ * SERDES E => Slot 4, lane 0 
+ */
+
+/* MUX_SER5_6_SEL
+ *	0: SERDES F => SLOT4, lane 1
+ *	   SERDES G => SLOT4, lane 2
+ * 	1: SERDES F => SLOT2
+ *	   SERDES G => SLOT3
+ */
+#define SER_5_6_SLOT4	0
+#define SER_5_6_SLOT23	4
+
+
+/*
+ * SERDES H => Slot 4, lane 3
+ */
+
+int scalys_carrier_setup_muxing(int serdes_config)
+{
+	int ret = 0;
+	int mux_config = 0;
+
+	ret = gpio_request(MUX_SER0_1_SEL, "mux_ser0_1_sel");
+	if (ret != 0) {
+		printf("gpio request failed(%i)\n", ret);
+	}
+	gpio_request(MUX_SER2_3_SEL, "mux_ser2_3_sel");
+	gpio_request(MUX_SER5_6_SEL, "mux_ser5_6_sel");
+	gpio_request(SERDES_CLK_OE, "serdes_clk_oe");
+	
+	
+	/* 
+	 * SERDES options for each target as supported by the dragonfruit 
+	 * carrier board. Refer to the QorIQ reference manual for the SERDES options table 
+	 * and all relevant information.
+	 * 
+	 * Note: The SERDES lanes A&B, C&D, and F&G can only be switched 
+	 * as pairs using the multiplexers. Which means some SERDES options are only partly usable.
+	 * 
+	 * Note 2/TODO: SERDES PLL2 must be powered down using SRDS_PLL_PD_S1 when
+	 * SRDS_PRTCL_S1 is any of the following values: 0x00, 0x40, 0x60, 0x67, 
+	 * 0x85, 0x87, 0x8D, 0x45.
+	 * 
+	 * T2081 has 8 SERDES lanes at up to 10GHz (ie. SERDES 2 configurations are DNC)
+	 * 
+	 */
+	switch(serdes_config){
+#if defined(CONFIG_PPC_T2081)
+		/* TODO: test all major cases */
+	case 0x6E:
+	case 0xC8:
+	case 0xD6:
+	case 0x6C:
+		mux_config = SER_5_6_SLOT4 | SER_2_3_SFP23 | SER_0_1_SFP01;
+		break;
+	case 0xAA: /* Note 2 */
+		mux_config = SER_5_6_SLOT4 | SER_2_3_SLOT1 | SER_0_1_SLOT1;
+		break;
+	case 0xBC: /* Note 2 */
+		mux_config = SER_5_6_SLOT4 | SER_2_3_SFP23 | SER_0_1_SLOT1;
+		break;
+	case 0xCA:
+	case 0xF2: /* Note 2 */
+	case 0xF8:
+	case 0xFA:
+	case 0x70:
+		mux_config = SER_5_6_SLOT23 | SER_2_3_SFP23 | SER_0_1_SFP01;
+		break;
+	case 0xDE: /* Note 2 */
+	case 0xE0: /* Note 2 */
+		mux_config = SER_5_6_SLOT23 | SER_2_3_SLOT1 | SER_0_1_SLOT1;
+		break;
+#else
+#error "Invalid or unspecified target cpu for dragonfruit carrier board!"
+#endif
+	default:
+		printf("Unsupported SERDES configuration (%02x) detected for dragonfruit carrier board (Warning: Using default multiplexer settings)!\n", serdes_config);
+	}
+	
+	
+
+
+
+	
+	printf("-----------------------------------------------------\n");
+	printf("Serdes lane configuration:\n");
+	if ((mux_config & 1) > 0) {
+		gpio_direction_output(MUX_SER0_1_SEL, 1);
+		printf("A: SFP slot 0 (T2081 only)\n");
+		printf("B: SFP slot 1\n");
+	} else {
+		gpio_direction_output(MUX_SER0_1_SEL, 0);
+		printf("A: PCIe slot 1 on lane 0\n");
+		printf("B: PCIe slot 1 on lane 1\n");
+	}
+	
+	if ((mux_config & 2) > 0) {
+		gpio_direction_output(MUX_SER2_3_SEL, 1);
+		printf("C: SFP slot 2\n");
+		printf("D: SFP slot 3\n");
+	} else {
+		gpio_direction_output(MUX_SER2_3_SEL, 0);
+		printf("C: PCIe slot 1 on lane 2\n");
+		printf("D: PCIe slot 1 on lane 3\n");
+	}
+	
+	printf("E: PCIe slot 4 on lane 0\n");
+	
+	if ((mux_config & 4) > 0) {
+		gpio_direction_output(MUX_SER5_6_SEL, 1);
+		printf("F: PCIe slot 2 on lane 0\n");
+		printf("G: PCIe slot 3 on lane 0\n");
+	} else {
+		gpio_direction_output(MUX_SER5_6_SEL, 0);
+		printf("F: PCIe slot 4 on lane 1\n");
+		printf("G: PCIe slot 4 on lane 2\n");
+	}
+	
+	printf("H: PCIe slot 4 on lane 3\n");
+	printf("-----------------------------------------------------\n");
+
+	/* Enable serdes clock */
+	gpio_direction_output(SERDES_CLK_OE, 1);
+
+	return ret;
+}
diff --git a/board/scalys/simc-t2081/dragonfruit.h b/board/scalys/simc-t2081/dragonfruit.h
new file mode 100644
index 0000000..554b2bf
--- /dev/null
+++ b/board/scalys/simc-t2081/dragonfruit.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DRAGON_FRUIT_H
+#define _DRAGON_FRUIT_H
+
+int scalys_carrier_setup_muxing(int serdes_config);
+
+#endif /* _DRAGON_FRUIT_H */
diff --git a/board/scalys/simc-t2081/eth.c b/board/scalys/simc-t2081/eth.c
new file mode 100644
index 0000000..c25a81c
--- /dev/null
+++ b/board/scalys/simc-t2081/eth.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <asm/immap_85xx.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fsl_dtsec.h>
+#include <vsc9953.h>
+#include <i2c.h>
+
+#include "../../freescale/common/fman.h"
+
+uint8_t sfp_phy_config[][2] = {
+	{ 0x1b, 0x90 },
+	{ 0x1b, 0x84 },
+	{ 0x09, 0x0F },
+	{ 0x09, 0x00 },
+	{ 0x00, 0x81 },
+	{ 0x00, 0x40 },
+};
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	struct memac_mdio_info memac_mdio_info;
+	unsigned int i;
+	uint8_t i2c_data;
+	int ret;
+	int phy_addr = 0;
+	
+	uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
+	uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
+	uint32_t *gpio4_gpdir = (uint32_t *) 0xffe133000;
+	uint32_t *gpio4_gpdat = (uint32_t *) 0xffe133008;
+	uint32_t regval;
+	
+	/* Try to read a byte from te carrier eeprom te determine if were on the correct carrier */
+	ret = i2c_read(0x54, 0, 2, &i2c_data, 1 );
+	if (ret != 0) {
+		printf("No dragonfruit carrier detected\n");
+		return 0;
+	}
+	
+	printf("Initializing Fman\n");
+
+	memac_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the real 1G MDIO bus */
+	fm_memac_mdio_init(bis, &memac_mdio_info);
+
+   /* Marvell 88E1111 Setup
+	* 
+	* Remove reset from Ethernet PHY's 
+	* 
+	* Carrier board v1.x:
+	* IFC_PERR_B : GPIO2_15 : eth1_reset
+	* IFC_CS_N2  : GPIO2_11 : eth2_reset 
+	*
+	* Carrier board v2.x:
+	* IFC_PERR_B : GPIO2_15 : eth1_reset
+	* IFC_CS_N2  : GPIO4_09 : eth2_reset
+	* 
+	* Note: make sure gpio pins are configured as gpio in RCW! 
+	*/
+
+#if 0 
+	/* TODO: use EEPROM data to chose carrier board version */
+	/* Carrier board v1.x */
+	/* Clear outputs to activate reset */
+	regval = in_be32(gpio2_gpdat);
+	regval &= ~((0x80000000 >> 11 ) | (0x80000000 >> 15));
+	out_be32(gpio2_gpdat, regval);
+	
+	/* Set outputs to output mode */
+	regval = in_be32(gpio2_gpdir);
+	regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15));
+	out_be32(gpio2_gpdir, regval);
+	
+	/* Wait for 10 ms to to meet reset timing */
+	mdelay(10);
+	
+	/* Set outputs to de-activate reset */
+	regval = in_be32(gpio2_gpdat);
+	regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15));
+	out_be32(gpio2_gpdat, regval);
+#else
+	/* Carrier board v2.x */
+	/* Clear outputs to activate reset */
+	regval = in_be32(gpio2_gpdat);
+	regval &= ~(0x80000000 >> 15);
+	out_be32(gpio2_gpdat, regval);
+	regval = in_be32(gpio4_gpdat);
+	regval &= ~(0x80000000 >> 9);
+	out_be32(gpio4_gpdat, regval);
+	
+	/* Set outputs to output mode */
+	regval = in_be32(gpio2_gpdir);
+	regval |= (0x80000000 >> 15);
+	out_be32(gpio2_gpdir, regval);
+	regval = in_be32(gpio4_gpdir);
+	regval |= (0x80000000 >> 9);
+	out_be32(gpio4_gpdir, regval);
+	
+	/* Wait for 10 ms to to meet reset timing */
+	mdelay(10);
+	
+	/* Set outputs to de-activate reset */
+	regval = in_be32(gpio2_gpdat);
+	regval |= (0x80000000 >> 15);
+	out_be32(gpio2_gpdat, regval);
+	regval = in_be32(gpio4_gpdat);
+	regval |= (0x80000000 >> 9);
+	out_be32(gpio4_gpdat, regval);
+#endif
+	
+	/* Write 0x4111 to reg 0x18 on both PHYs to change LEDs usage */
+	miiphy_write("FSL_MDIO0",0,0x18,0x4111);
+	miiphy_write("FSL_MDIO0",1,0x18,0x4111);
+
+	/* Remove SFP TX_disable */
+	i2c_set_bus_num(0);
+	ret = i2c_read(0x22, 0x0E, 1, &i2c_data, 1);
+	i2c_data &= ~0x04;
+	ret = i2c_write(0x22, 0x0E, 1, &i2c_data, 1);
+
+	mdelay(100);
+	
+	i2c_set_bus_num(3);
+	
+	for (phy_addr=0; phy_addr<4; phy_addr++) {
+		i2c_data = (1 << phy_addr);
+		ret = i2c_write(0x70, 0, 1, &i2c_data, 1);
+		if (ret) {
+			printf("Error Setting SFP i2c MUX\n");
+			break;
+		}
+		
+		for ( i = 0; i < 6; i++) {
+			ret = i2c_write(0x56, sfp_phy_config[i][0], 1, &(sfp_phy_config[i][1]), 1);
+			if (ret) {
+				printf("Error sfp phy(%i:%i):%02x to address %02x\n", phy_addr, i, sfp_phy_config[i][1],sfp_phy_config[i][0]);
+				break;
+			}
+		}
+	}
+	
+	/* Two external pin interfaces
+	 * MAC1|MAC2|MAC3 SGMII interface
+	 * MAC3|MAC4|MAC10 EC1|EC2 RGMII interface
+	 */
+	
+	/*
+	 * Program on board RGMII, SGMII PHY addresses.
+	 */
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		int idx = i - FM1_DTSEC1;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_RGMII:
+			if (FM1_DTSEC3 == i)
+				phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
+			if (FM1_DTSEC4 == i)
+				phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
+			/*if (FM1_DTSEC10 == i)
+				phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;*/
+			fm_info_set_phy_address(i, phy_addr);
+			break;
+		case PHY_INTERFACE_MODE_QSGMII:
+			/* TODO, get fixed phy here */
+			fm_info_set_phy_address(i, i+2); 
+			break;
+		case PHY_INTERFACE_MODE_NONE:
+			fm_info_set_phy_address(i, 0);
+			break;
+		case PHY_INTERFACE_MODE_SGMII:
+			printf("TODO, add phy interface to SGMII\n");
+			fm_info_set_phy_address(i, PHY_INTERFACE_MODE_NONE);
+			break;
+		default:
+			printf("Fman1: DTSEC%u set to unknown interface %i\n",
+			       idx + 1, fm_info_get_enet_if(i));
+			//fm_info_set_phy_address(i, 0);
+			break;
+		}
+		fm_info_set_mdio(i,
+				 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+	}
+	
+	cpu_eth_init(bis);
+#endif
+	return pci_eth_init(bis);
+}
+
+/*void fdt_fixup_board_enet(void *fdt)
+{
+	return;
+}*/
diff --git a/board/scalys/simc-t2081/law.c b/board/scalys/simc-t2081/law.c
new file mode 100644
index 0000000..cc03808a
--- /dev/null
+++ b/board/scalys/simc-t2081/law.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ * 
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif	
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/scalys/simc-t2081/pci.c b/board/scalys/simc-t2081/pci.c
new file mode 100644
index 0000000..9a02f90
--- /dev/null
+++ b/board/scalys/simc-t2081/pci.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ * 
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+	
+	uint32_t *gpio1_gpdir = (uint32_t *) 0xffe130000;
+	uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008;
+	uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
+	uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
+	uint32_t regval;	
+	
+	/*debug("%s\n", __FUNCTION__);*/
+	
+	/*TODO, when present pins are available on the board, use them to enable only active slots*/
+	
+#if 0
+	/* Dragonfruit Carrier board 1.x */
+
+
+	/* 
+	 * IRQ[0-3] : PCIe present detect signals
+	 * IRQ[0] : SLOT1_PRSNT2_N : XXX
+	 * IRQ[1] : SLOT2_PRSNT2_N : XXX
+	 * IRQ[2] : SLOT3_PRSNT2_N : XXX
+	 * IRQ[3] : SLOT4_PRSNT2_N : XXX
+	 * 
+	 * Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7 
+	 * IFC_CS_N4 : GPIO1_IO09 : PCIe SLOT1_REFCLK_OE_N
+	 * IFC_CS_N5 : GPIO1_IO10 : PCIe SLOT2_REFCLK_OE_N
+	 * IFC_CS_N6 : GPIO1_IO11 : PCIe SLOT3_REFCLK_OE_N
+	 * IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N
+	 */
+	
+	/* Set output to 0 to enable reference clocks */
+	regval = in_be32(gpio1_gpdat);
+	regval &= ~( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) );
+	out_be32(gpio1_gpdat, regval);
+	
+	/* Set Enable outputs*/
+	regval = in_be32(gpio1_gpdir);
+	regval |= ( (0x80000000 >> 9 ) | ( 0x80000000 >> 10 ) | ( 0x80000000 >> 11 ) | ( 0x80000000 >> 12 ) );
+	out_be32(gpio1_gpdir, regval);
+	
+#else
+	/* Dragonfruit Carrier board 2.x */
+	/* 
+	 * PCIe present detect signals:
+	 * IRQ[3] : GPIO1_23 : SLOT1_PRSNT2_N
+	 * IRQ[4] : GPIO1_24 : SLOT2_PRSNT2_N
+	 * IRQ[5] : GPIO1_25 : SLOT3_PRSNT2_N
+	 * IRQ[10] : GPIO1_30 : SLOT4_PRSNT2_N
+	 * 
+	 * Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7 
+	 * IFC_CS_N7 : GPIO1_IO12 : PCIe SLOT4_REFCLK_OE_N (used for all 4 slots)
+	 * IFC_PAR1 : GPIO2_14 : PEX_REFCLK_SEL
+	 */
+	
+	/* Set output to 0 to enable reference clocks */
+	regval = in_be32(gpio1_gpdat);
+	regval &= ~( 0x80000000 >> 12 );
+	out_be32(gpio1_gpdat, regval);
+	
+	/* Set Enable outputs */
+	regval = in_be32(gpio1_gpdir);
+	regval |= ( 0x80000000 >> 12 );
+	out_be32(gpio1_gpdir, regval);
+	
+	/* Set PEX_REFCLK_SEL to 0 to select CLK0  */
+
+	/* Set IFC_PAR1 to output mode */
+	regval = in_be32(gpio2_gpdir);
+	regval |= ( 0x80000000 >> 14 );
+	out_be32(gpio2_gpdir, regval);
+
+	/* Set output to 0 to select clock source 0 */
+	regval = in_be32(gpio2_gpdat);
+	regval &= ~( 0x80000000 >> 14 );
+	out_be32(gpio2_gpdat, regval);
+
+#endif
+	
+	/*
+	 * IFC_PAR0 : GPIO2_13 : PEX_PERST_N
+	 */
+
+	/* Remove reset from PCIe devices */
+
+	/* Set IFC_PAR0 to output mode */
+	regval = in_be32(gpio2_gpdir);
+	regval |= ( 0x80000000 >> 13 );
+	out_be32(gpio2_gpdir, regval);
+
+	/* Set output to 1 to clear reset */
+	regval = in_be32(gpio2_gpdat);
+	regval |= ( 0x80000000 >> 13 );
+	out_be32(gpio2_gpdat, regval);
+
+	/* Wait for 100 ms to allow the PCIe device to become ready */
+	mdelay(100);
+	
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/scalys/simc-t2081/simc-t2081.c b/board/scalys/simc-t2081/simc-t2081.c
new file mode 100644
index 0000000..f07a36f
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <asm/fsl_pci.h>
+#include <fm_eth.h>
+#include <asm/processor.h>
+#include <asm/gpio.h>
+#include <fsl_esdhc.h>
+#include <dm.h>
+#include "dragonfruit.h"
+#include <board_configuration_data.h>
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: simc-t2081\n" );
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	const void* bcd_dtc_blob;
+	int serdes_config;
+	ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int ret;
+	
+	debug("t2081: misc_init_r\n");
+	/*
+	 * Initialize and set the LED's on the module to indicate u-boot is alive
+	 * IFC_A30 : led green : GPIO2_30
+	 * IFC_A31 : led red   : GPIO2_31
+	 */
+	#define MODULE_LED_RED      MPC85XX_GPIO_NR(2, 31)
+	#define MODULE_LED_GREEN    MPC85XX_GPIO_NR(2, 30)
+	gpio_request(MODULE_LED_RED, "module_led_red");
+	gpio_request(MODULE_LED_GREEN, "module_led_green");
+
+	gpio_direction_output(MODULE_LED_RED, 0);
+	gpio_direction_output(MODULE_LED_GREEN, 1);
+	
+	/* SERDES configuration is determined boot time through the RCW config.
+	 * It is located in the fourth RCW word (bit 128-135 of the RCW). */
+	serdes_config = ( in_be32(&gur->rcwsr[4]) >> 24);
+	scalys_carrier_setup_muxing(serdes_config);
+	
+	bcd_dtc_blob = get_boardinfo_eeprom();
+	if (bcd_dtc_blob != NULL) {
+		/* Board Configuration Data is intact, ready for parsing */
+		ret = add_mac_addressess_to_env(bcd_dtc_blob);
+		if (ret != 0) {
+			printf("Error adding BCD data to environement\n");
+		}
+	}
+
+	return 0;
+}
+
+/* Platform data for the GPIOs */
+static const struct mpc85xx_gpio_plat gpio_platdata[] = {
+	{ .addr = 0x130000, .ngpios = 32 },
+	{ .addr = 0x131000, .ngpios = 32 },
+	{ .addr = 0x132000, .ngpios = 32 },
+	{ .addr = 0x133000, .ngpios = 32,},
+};
+
+U_BOOT_DEVICES(mpc85xx_gpios) = {
+	{ "gpio_mpc85xx", &gpio_platdata[0] },
+	{ "gpio_mpc85xx", &gpio_platdata[1] },
+	{ "gpio_mpc85xx", &gpio_platdata[2] },
+	{ "gpio_mpc85xx", &gpio_platdata[3] },
+};
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	debug( "t2081: ft_board_setup\n" );
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	debug( "fdt_fixup_memory\n" );
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+    
+#ifdef CONFIG_PCI
+	debug( "pci_of_setup\n" );
+	FT_FSL_PCI_SETUP;
+#endif
+	debug( "fdt_fixup_liodn\n" );
+	fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+	debug( "fsl_fdt_fixup_dr_usb\n" );
+	fsl_fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	debug( "fdt_fixup_fman_ethernet\n" );
+	fdt_fixup_fman_ethernet(blob);
+#endif
+
+    return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	struct fsl_esdhc_cfg *cfg;
+
+	cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
+	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+	cfg->sdhc_clk = gd->arch.sdhc_clk;
+	cfg->max_bus_width = 4;
+	return fsl_esdhc_initialize(bis, cfg);
+
+	return 0;
+}
+
+#if 0
+void board_detail(void) 
+{
+	do_bcdinfo();
+}
+#endif
diff --git a/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg b/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg
new file mode 100644
index 0000000..e3ed70b
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg
@@ -0,0 +1,44 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fffc0009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1 (LAW 13)
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure IFC controller
+# (IFC_CSPR1)
+09124010 ff8000c3
+#  IFC_CSOR_NAND
+09124130 85084101
+#  IFC_FTIM0_CS0_NAND to IFC_FTIM0_CS0_NAND 
+091241c0 181c080c
+091241c4 3850141a
+091241c8 03008028
+091241cc 28000000
+# Set IFC_CCR clkdiv to 2 (=/3) to get: 
+# (platform clock/2/3=83.3MHz)
+0912444c 02008000
+#Flush PBL data (Wait 0xFFFFF cycles )
+091380c0 000fffff
diff --git a/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
new file mode 100644
index 0000000..2746cf4
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
@@ -0,0 +1,20 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+#0a06000c 0c000000 00000000 00000000
+#aa000002 00004000 e8105000 21000000
+#00000000 cafebabe 00000000 00030ffc
+#00000314 0000000c 00000000 00000001
+#
+
+# #SerDes=0xaa, Core:1200MHz, DDR:1600MT/s
+# 0a06000c 0c000000 00000000 00000000
+# 66000002 00404000 e8105000 21000000
+# 00000000 cafebabe 00000000 00030ffc
+# 00000314 00000008 00000000 00000001
+
+
+0c06000c 0c000000 00000000 00000000
+aa000002 40404000 e8105000 21000000
+00000000 cafebabe 00000000 00030ffc
+00000314 80000009 00000000 00000001
diff --git a/board/scalys/simc-t2081/simc-t2081_nor_pbi.cfg b/board/scalys/simc-t2081/simc-t2081_nor_pbi.cfg
new file mode 100644
index 0000000..fd38b58
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_nor_pbi.cfg
@@ -0,0 +1,31 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fffc0009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1 (LAW 13)
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data (Wait 0xFFFFF cycles )
+091380c0 000fffff
diff --git a/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg
new file mode 100644
index 0000000..d8ac2bd
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_nor_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+#
+0c06000c 0c000000 00000000 00000000
+aa000002 40404000 e8023000 21000000
+00000000 cafebabe 00000000 00030ffc
+00000314 80000009 00000000 00000001
+
diff --git a/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg b/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg
new file mode 100644
index 0000000..fd38b58
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_sdhc_pbi.cfg
@@ -0,0 +1,31 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fffc0009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1 (LAW 13)
+09000cd0 00000000
+09000cd4 fffc0000
+09000cd8 81000011
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data (Wait 0xFFFFF cycles )
+091380c0 000fffff
diff --git a/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg
new file mode 100644
index 0000000..f06629c
--- /dev/null
+++ b/board/scalys/simc-t2081/simc-t2081_sdhc_rcw.cfg
@@ -0,0 +1,18 @@
+#PBL preamble and RCW header
+AA55AA55 010E0100
+
+#SerDes=0xaa, Core:1200MHz, DDR:1600MT/s
+# 0a06000c 0c000000 00000000 00000000
+# 66000002 00404000 68105000 21000000
+# 00000000 cafebabe 00000000 00030ffc
+# 00000314 00000008 00000000 00000001
+
+# 0c06000c 0c000000 00000000 00000000
+# 66000002 40404000 68105000 21000000
+# 00000000 cafebabe 00000000 00030ffc
+# 00000314 80000008 00000000 00000001
+
+0c06000c 0c000000 00000000 00000000
+aa000002 40404000 68105000 21000000
+00000000 cafebabe 00000000 00030ffc
+00000314 80000009 00000000 00000001
diff --git a/board/scalys/simc-t2081/spl.c b/board/scalys/simc-t2081/spl.c
new file mode 100644
index 0000000..f0fb9dd
--- /dev/null
+++ b/board/scalys/simc-t2081/spl.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ * 
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <console.h>
+#include <nand.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <i2c.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	return CONFIG_DDR_CLK_FREQ;
+}
+
+#define FSL_CORENET_CCSR_PORSR1_RCW_MASK	0xFF800000
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, sys_clk, uart_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+	/* Update GD pointer */
+	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+	/* compiler optimization barrier needed for GCC >= 3.4 */
+	__asm__ __volatile__("" : : : "memory");
+
+	console_init_f();
+
+	/* initialize selected port with appropriate baud rate */
+	sys_clk = get_board_sys_clk();
+	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+	uart_clk = sys_clk * plat_ratio / 2;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     uart_clk / 16 / CONFIG_BAUDRATE);
+
+	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void setup_ifc_nand(enum ifc_chip_sel cs)
+{
+	set_ifc_cspr_ext(cs, CONFIG_SYS_NAND_CSPR_EXT);
+	set_ifc_csor	(cs, CONFIG_SYS_NAND_CSOR);
+	set_ifc_amask	(cs, CONFIG_SYS_NAND_AMASK);
+	set_ifc_cspr	(cs, CONFIG_SYS_NAND_CSPR);
+	set_ifc_ftim	(cs, IFC_FTIM0, CONFIG_SYS_NAND_FTIM0);
+	set_ifc_ftim	(cs, IFC_FTIM1, CONFIG_SYS_NAND_FTIM1);
+	set_ifc_ftim	(cs, IFC_FTIM2, CONFIG_SYS_NAND_FTIM2);
+	set_ifc_ftim	(cs, IFC_FTIM3, CONFIG_SYS_NAND_FTIM3);
+	set_ifc_csor_ext(cs, 0);
+
+}
+
+void setup_ifc_nor(enum ifc_chip_sel cs)
+{
+	set_ifc_cspr_ext(cs, CONFIG_SYS_NOR_CSPR_EXT);
+	set_ifc_csor	(cs, CONFIG_SYS_NOR_CSOR);
+	set_ifc_amask	(cs, CONFIG_SYS_NOR_AMASK);
+	set_ifc_cspr	(cs, CONFIG_SYS_NOR_CSPR);
+	set_ifc_ftim	(cs, IFC_FTIM0, CONFIG_SYS_NOR_FTIM0);
+	set_ifc_ftim	(cs, IFC_FTIM1, CONFIG_SYS_NOR_FTIM1);
+	set_ifc_ftim	(cs, IFC_FTIM2, CONFIG_SYS_NOR_FTIM2);
+	set_ifc_ftim	(cs, IFC_FTIM3, CONFIG_SYS_NOR_FTIM3);
+	set_ifc_csor_ext(cs, 0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	bd_t *bd;
+	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	uint32_t boot_source;
+	
+	__attribute__((noreturn)) void (*boot)(void) = hang;
+
+	bd = (bd_t *)(gd + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+	arch_cpu_init();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+
+	gd->ram_size = dram_init();
+
+	/* Get the boot source from the Power On Status Register (set by QSC) */
+	boot_source = (in_be32(&gur->porsr1) >> 23);
+
+	switch (boot_source) {
+	case 0x23:
+		/* NOR boot */
+		setup_ifc_nor(IFC_CS0);
+		setup_ifc_nand(IFC_CS1);
+
+		memcpy((void*)CONFIG_SYS_NAND_U_BOOT_DST, (void*) CONFIG_SYS_FLASH_BASE + CONFIG_SPL_PAD_TO, CONFIG_SYS_NAND_U_BOOT_SIZE);
+
+		flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
+		boot = (void*) CONFIG_SYS_NAND_U_BOOT_START;
+		break;
+
+	case 0x45:
+#if 0
+		/*SPI nor flash */
+		setup_ifc_nand(IFC_CS0);
+		setup_ifc_nor(IFC_CS1);
+		//fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, (uchar *)CONFIG_ENV_ADDR);
+		{
+			struct spi_flash *flash;
+
+			flash = spi_flash_probe(0, 0,
+				CONFIG_SF_DEFAULT_SPEED, CONFIG_SF_DEFAULT_MODE);
+			if (flash == NULL) {
+				puts("\nspi_flash_probe failed");
+				hang();
+			}
+
+			spi_flash_read(flash, CONFIG_SPL_PAD_TO, CONFIG_SYS_NAND_U_BOOT_SIZE, (void*) CONFIG_SYS_NAND_U_BOOT_DST);
+		}
+#endif
+		printf("TODO, load u-boot from SPI....\n");
+		hang();
+		break;
+	case 0x40:
+		/* SD/MMC (eSDHC) boot */
+		#ifdef CONFIG_SPL_MMC_BOOT
+		setup_ifc_nand(IFC_CS0);
+		setup_ifc_nor(IFC_CS1);
+		
+		mmc_initialize(bd);
+		mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)CONFIG_ENV_ADDR);
+		boot = mmc_boot;
+		#endif
+		break;
+	case 0x105:
+		/* NAND boot */
+		setup_ifc_nand(IFC_CS0);
+		setup_ifc_nor(IFC_CS1);
+
+		nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+		    (uchar *)CONFIG_ENV_ADDR);
+		boot = nand_boot;
+		break;
+	default:
+		printf("Unknown boot source (%3x\n", boot_source);
+	break;
+	}
+	boot();
+}
diff --git a/board/scalys/simc-t2081/tlb.c b/board/scalys/simc-t2081/tlb.c
new file mode 100644
index 0000000..c03282e
--- /dev/null
+++ b/board/scalys/simc-t2081/tlb.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * opensource@scalys.com
+ * 
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \
+	!defined(CONFIG_SECURE_BOOT)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 512K SRAM, the address of the
+	 * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_512K, 1),
+#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 512K SRAM, in case of Secure Boot
+	 * the physical address of the SRAM is at 0xbffc0000,
+	 * and virtual address is 0xfffc0000
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR,
+		      CONFIG_SYS_INIT_L3_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_512K, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_64M, 1), /* modified to simc-t1040 equivalent */
+
+#ifndef CONFIG_SPL_BUILD
+#ifdef CONFIG_PCI
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256K, 1),
+#endif
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 5, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 7, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+			  
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 12, BOOKE_PAGESZ_1G, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 13, BOOKE_PAGESZ_1G, 1)
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/QT1040-1GB_nand_defconfig b/configs/QT1040-1GB_nand_defconfig
new file mode 100644
index 0000000..b24245f
--- /dev/null
+++ b/configs/QT1040-1GB_nand_defconfig
@@ -0,0 +1,44 @@
+CONFIG_SPL=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_QT1040_1GB=y
+CONFIG_PPC_T1040=y
+CONFIG_SYS_FSL_DDR3=y
+
+CONFIG_HUSH_PARSER=y
+
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_GPIO=y
+
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_IMLS=n
+CONFIG_CMD_I2C=y
+CONFIG_CMD_FAT=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_MARVELL=y
+
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB=y
+
+CONFIG_OF_LIBFDT=y 
+CONFIG_SPL_OF_LIBFDT=y 
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_BEST_MATCH=y
+CONFIG_OF_BOARD_SETUP=y
+
+CONFIG_CMD_DM=y
+CONFIG_SPL_DM=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_MPC85XX_GPIO=y
+
+CONFIG_SYS_MALLOC_F=n
diff --git a/configs/T1_simc-t10xx_nand_defconfig b/configs/T1_simc-t10xx_nand_defconfig
index b6275f8..80b24e7 100644
--- a/configs/T1_simc-t10xx_nand_defconfig
+++ b/configs/T1_simc-t10xx_nand_defconfig
@@ -1,8 +1,9 @@
 CONFIG_SPL=y
 CONFIG_PPC=y
 CONFIG_MPC85xx=y
-CONFIG_TARGET_SIMC_T10XX=y
-
+CONFIG_TARGET_SIMC_TXXXX=y
+CONFIG_PPC_T1040=y
+CONFIG_SYS_FSL_DDR3=y
 
 CONFIG_HUSH_PARSER=y
 
@@ -16,6 +17,10 @@ CONFIG_CMD_NAND=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_IMLS=n
 CONFIG_CMD_I2C=y
+CONFIG_CMD_FAT=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_MARVELL=y
 
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
diff --git a/configs/T2_simc-t2081_nand_defconfig b/configs/T2_simc-t2081_nand_defconfig
new file mode 100644
index 0000000..780b70f
--- /dev/null
+++ b/configs/T2_simc-t2081_nand_defconfig
@@ -0,0 +1,43 @@
+CONFIG_SPL=y
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_SIMC_TXXXX=y
+CONFIG_PPC_T2081=y
+
+CONFIG_HUSH_PARSER=y
+
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_GPIO=y
+
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_IMLS=n
+CONFIG_CMD_I2C=y
+CONFIG_CMD_FAT=y
+
+CONFIG_PHYLIB=y
+CONFIG_PHY_MARVELL=y
+
+CONFIG_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_CMD_USB=y
+
+CONFIG_OF_LIBFDT=y 
+CONFIG_SPL_OF_LIBFDT=y 
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_FIT_BEST_MATCH=y
+CONFIG_OF_BOARD_SETUP=y
+
+CONFIG_CMD_DM=y
+CONFIG_SPL_DM=y
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_MPC85XX_GPIO=y
+
+CONFIG_SYS_MALLOC_F=n
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index fecb2fc..ffeda94 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -34,8 +34,6 @@ config DWAPB_GPIO
 	help
 	  Support for the Designware APB GPIO driver.
 
-<<<<<<< 82a006ca2df310164bb48c36a793d1b733cf4af8
-<<<<<<< bc5d0384458466ed5b3608d326eec03cd4f13016
 config AT91_GPIO
 	bool "AT91 PIO GPIO driver"
 	depends on DM_GPIO
@@ -48,17 +46,7 @@ config AT91_GPIO
 	  The assignment to a function of an embedded peripheral is
 	  the responsibility of AT91 Pinctrl driver. This driver is
 	  responsible for the general-purpose I/O.
-=======
-config MPC8XXX_GPIO
-	bool "NXP (Freescale) MPC8xxx driver"
-	depends on DM_GPIO
-	default n
-	help
-	   Support for the NXP (Freescale) MPC/QorIQ GPIO controller
->>>>>>> dm: gpio: Add DM GPIO driver for MPC8xxx platforms
 
-=======
->>>>>>> merge with master
 config ATMEL_PIO4
 	bool "ATMEL PIO4 driver"
 	depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 3209071..1396467 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -37,11 +37,7 @@ obj-$(CONFIG_DA8XX_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_DM644X_GPIO)	+= da8xx_gpio.o
 obj-$(CONFIG_ALTERA_PIO)	+= altera_pio.o
 obj-$(CONFIG_MPC83XX_GPIO)	+= mpc83xx_gpio.o
-<<<<<<< bc5d0384458466ed5b3608d326eec03cd4f13016
 obj-$(CONFIG_MPC85XX_GPIO)	+= mpc85xx_gpio.o
-=======
-obj-$(CONFIG_MPC8XXX_GPIO)	+= gpio-mpc8xxx.o
->>>>>>> dm: gpio: Add DM GPIO driver for MPC8xxx platforms
 obj-$(CONFIG_SH_GPIO_PFC)	+= sh_pfc.o
 obj-$(CONFIG_OMAP_GPIO)	+= omap_gpio.o
 obj-$(CONFIG_DB8500_GPIO)	+= db8500_gpio.o
diff --git a/include/configs/QT1040-1GB.h b/include/configs/QT1040-1GB.h
new file mode 100644
index 0000000..3aa4c37
--- /dev/null
+++ b/include/configs/QT1040-1GB.h
@@ -0,0 +1,907 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * 
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _QT1040_1GB_H
+#define _QT1040_1GB_H
+
+#include "simc-t10x0.h"
+#include <generated/autoconf.h>
+
+
+
+#define CONFIG_MTD_UBI_WL_THRESHOLD	4096
+#define CONFIG_MTD_UBI_BEB_LIMIT	20
+
+
+#define MPC85XX_GPIO_NR(port, pin)     ((((port)-1)*32)+((pin)&31))
+
+/*
+ * SIMC-T10xx board configuration file
+ */
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)    /* MT29F8G08ABBCAH4*/
+
+/*
+ * System and DDR clock
+ */
+#define CONFIG_SYS_CLK_FREQ		100000000	/* 100 MHz */
+#define CONFIG_DDR_CLK_FREQ		133333333	/* 133.33MHz */
+
+#ifdef CONFIG_RAMBOOT_PBL
+
+/* We have to specify all the PBL and RCW since they are used without being 
+ * proccessed by the preprocessor */
+#if defined(CONFIG_NAND_FLASH_BOOT)
+/* normal boot from NAND flash */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_nand_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/qt1040-1gb_nand_rcw.cfg
+#elif defined(CONFIG_NOR_FLASH_BOOT)
+/* normal boot from NOR flash */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_nor_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/qt1040-1gb_nor_rcw.cfg
+#elif defined(CONFIG_SPI_FLASH_BOOT)
+/* normal boot from SPI flash */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_spi_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/qt1040-1gb_spi_rcw.cfg
+#elif defined(CONFIG_SDHC_FLASH_BOOT)
+/* normal boot from SDHC flash */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_sdhc_pbi.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/qt1040-1gb_sdhc_rcw.cfg
+#else
+/* unknown configuration, this should not happen */
+#error Invalid or unsupported Boot configuration
+#endif
+
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+
+#define CONFIG_SPL_I2C_SUPPORT
+
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SYS_TEXT_BASE            0x30001000
+#define CONFIG_SPL_TEXT_BASE            0xFFFD8000
+#define CONFIG_SPL_PAD_TO               0x40000
+#define CONFIG_SPL_MAX_SIZE             0x28000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif /* CONFIG_SPL_BUILD */
+
+#define RESET_VECTOR_OFFSET             0x27FFC
+#define BOOT_PAGE_OFFSET                0x27000
+
+#define CONFIG_SYS_MAX_FLASH_BANKS      1
+
+#ifdef CONFIG_NAND_FLASH
+#define CONFIG_SPL_NAND_SUPPORT
+
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	( (2048-256) *1024)
+#define CONFIG_U_BOOT_HDR_SIZE		(16 << 10)
+
+
+#define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
+#define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
+#ifndef CONFIG_SDHC_FLASH_BOOT 
+#define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+#endif /* CONFIG_NAND */
+
+#ifdef CONFIG_SDHC_FLASH_BOOT
+#define CONFIG_SDCARD
+#endif
+
+#ifdef CONFIG_SDCARD
+#define	CONFIG_RESET_VECTOR_ADDRESS	0x30000FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x30000000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x30000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#endif /* CONFIG_RAMBOOT_PBL */
+
+/* High Level Configuration Options */
+#include <asm/config_mpc85xx.h>
+#define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
+#define CONFIG_MP                       /* support multiple processors */
+
+
+/* #define CONFIG_DEEP_SLEEP */ /* support deep sleep */
+#define CONFIG_SILENT_CONSOLE
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
+#endif /* CONFIG_RESET_VECTOR_ADDRESS */
+
+#define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
+
+
+#define CONFIG_PCI_INDIRECT_BRIDGE
+
+
+/* The number of available PCI controllers depends on the RCW */
+#define CONFIG_PCIE1                    /* PCIE controler 1 */
+#define CONFIG_PCIE2                    /* PCIE controler 2 */
+#define CONFIG_PCIE3                    /* PCIE controler 3 */
+#define CONFIG_PCIE4                    /* PCIE controler 4 */
+
+#define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
+
+
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SIZE                 0x2000
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET               0x200000 /* Refer to mtdparts */
+/* 
+ *  CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|SATA|SPI_FLASH|NVRAM|MMC|FAT|EXT4|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
+ */
+
+#if 0
+#if defined(CONFIG_SDCARD)
+/* TODO: move env to boot source */
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE                 0x2000
+#define CONFIG_ENV_OFFSET               (512 * 0x800)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE                 0x2000
+#define CONFIG_ENV_OFFSET               0x200000 /* Refer to mtdparts */
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE                 0x2000
+#define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
+#endif /* CONFIG_SPIFLASH */
+#endif 
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BACKSIDE_L2_CACHE
+#define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
+#define CONFIG_BTB                      /* toggle branch predition */
+#define CONFIG_DDR_ECC
+
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE           0x0BADC0DE
+#endif /* CONFIG_DDR_ECC */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP         64  /* number of TLB1 entries */
+
+/* #define CONFIG_SYS_DRAM_TEST         Executes a memoty test at U-Boot start */
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START        0x00200000
+#define CONFIG_SYS_MEMTEST_END          0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+
+#define CONFIG_PANIC_HANG               /* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
+#define CONFIG_SYS_L3_SIZE              256 << 10
+/* TODO CLEANUP #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) */
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
+
+
+/*
+ * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
+ * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
+ * (CONFIG_SYS_INIT_L3_VADDR) will be different.
+ */
+#define CONFIG_SYS_INIT_L3_VADDR	0xFFFC0000
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
+
+
+#endif /* CONFIG_RAMBOOT_PBL */
+#define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
+#define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
+
+#define CONFIG_SYS_DCSRBAR              0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
+#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR      1
+#define CONFIG_CHIP_SELECTS_PER_CTRL    1
+
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_SDRAM_SIZE           1024    /* In MByte, for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#ifdef CONFIG_NOR_FLASH
+#define CONFIG_SYS_FLASH_BASE           0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#endif
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE            0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
+#define CONFIG_SYS_NAND_CSPR            (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+                                        | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+                                        | CSPR_MSEL_NAND    /* MSEL = NAND */ \
+                                        | CSPR_V)
+
+#define CONFIG_SYS_NAND_AMASK           IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR		(CSOR_NAND_ECC_ENC_EN |	/* ECC on encode */ \
+					 CSOR_NAND_ECC_DEC_EN |	/* ECC on decode */ \
+					 CSOR_NAND_ECC_MODE_4 |	/* 4-bit ECC */ \
+					 CSOR_NAND_RAL_3 |	/* RAL = 3Byes */ \
+					 CSOR_NAND_PGS_2K |	/* Page Size = 2K */ \
+					 CSOR_NAND_SPRZ_128 |	/* Spare size = 128 */ \
+					 CSOR_NAND_PB(64) |	/* Pages Per Block = 64 */ \
+					 CSOR_NAND_BCTLD)	/* Buffer control disable */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
+                                        FTIM0_NAND_TWP(0x18)   | \
+                                        FTIM0_NAND_TWCHT(0x07) | \
+                                        FTIM0_NAND_TWH(0x0a))
+                                        
+#define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
+                                        FTIM1_NAND_TWBE(0x39)  | \
+                                        FTIM1_NAND_TRR(0x0e)   | \
+                                        FTIM1_NAND_TRP(0x18))
+                                        
+#define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
+                                        FTIM2_NAND_TREH(0x0a) | \
+                                        FTIM2_NAND_TWHRE(0x1e))
+                                        
+#define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0xa)
+
+#define CONFIG_SYS_NAND_DDR_LAW         11
+#define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE      1
+/*#define CONFIG_CMD_NAND*/
+
+
+/* NOR configuation */
+/*#define CONFIG_SYS_NO_FLASH*/
+#define CONFIG_MTD
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH    FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_PROTECTION
+/*#define CONFIG_SYS_NOR_BASE		(0xe8000000)
+#define CONFIG_SYS_NOR_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NOR_BASE)
+*/
+#define CONFIG_SYS_FLASH_BASE           0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+
+
+#define CONFIG_SYS_NOR_CSPR_EXT        (0xf)
+#define CONFIG_SYS_NOR_CSPR            (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+					CSPR_PORT_SIZE_16 | \
+					CSPR_MSEL_NOR | \
+					CSPR_V)
+
+#define CONFIG_SYS_NOR_AMASK           IFC_AMASK(32*1024*1024)
+
+#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_AVD_TGL_PGM_EN |	/* AVD Toggle Enable during Burst Program */ \
+					 CSOR_NOR_ADM_SHIFT(7) |	/* Address Data Multiplexing Shift */ \
+					 CSOR_NOR_TRHZ_80) |		/* Time for Read Enable High to Output High Impedance */ \
+					 CSOR_NAND_BCTLD		/* Buffer control disable */
+
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+/*#define CONFIG_BOARD_EARLY_INIT_R*/
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SPL_GPIO_SUPPORT
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR            0xfdd00000  /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH  0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW   0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS       ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+                                            CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+                                            
+#define CONFIG_SYS_INIT_RAM_SIZE            0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET          (CONFIG_SYS_INIT_RAM_SIZE - \
+                                            GENERATED_GBL_DATA_SIZE)
+                                            
+#define CONFIG_SYS_INIT_SP_OFFSET           CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN              (768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN               (32 * 1024 * 1024)
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX                   1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE         1
+#define CONFIG_SYS_NS16550_CLK              (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE           {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1             (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2             (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3             (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4             (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SERIAL_MULTI                 /* Enable both serial ports */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV        /* determine from environment */
+#endif
+
+/* Use the HUSH parser */
+/*#define CONFIG_SYS_HUSH_PARSER*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+
+
+/* new uImage format support */
+#if 0
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE  /* enable fit_format_{error,warning}() */
+#endif
+
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL      /* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED    400000  /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SPEED   400000
+#define CONFIG_SYS_FSL_I2C3_SPEED   400000
+#define CONFIG_SYS_FSL_I2C4_SPEED   400000
+#define CONFIG_SYS_FSL_I2C_SLAVE    0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE   0x7F
+#define CONFIG_SYS_FSL_I2C3_SLAVE   0x7F
+#define CONFIG_SYS_FSL_I2C4_SLAVE   0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET   0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET  0x118100
+#define CONFIG_SYS_FSL_I2C3_OFFSET  0x119000
+#define CONFIG_SYS_FSL_I2C4_OFFSET  0x119100
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+#ifdef CONFIG_PCI
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#ifdef CONFIG_PCIE1
+#define CONFIG_SYS_PCIE1_MEM_VIRT   0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS    0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS   0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE   0x10000000  /* 256M */
+#define CONFIG_SYS_PCIE1_IO_VIRT    0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS     0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS    0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE    0x00010000  /* 64k */
+#endif
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#ifdef CONFIG_PCIE2
+#define CONFIG_SYS_PCIE2_MEM_VIRT   0x90000000
+#define CONFIG_SYS_PCIE2_MEM_BUS    0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS   0xc10000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE   0x10000000  /* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT    0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS     0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS    0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE    0x00010000  /* 64k */
+#endif
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#ifdef CONFIG_PCIE3
+#define CONFIG_SYS_PCIE3_MEM_VIRT   0xa0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS    0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS   0xc20000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE   0x10000000  /* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT    0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS     0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS    0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE    0x00010000  /* 64k */
+#endif
+
+/* controller 4, Base address 203000 */
+#ifdef CONFIG_PCIE4
+#define CONFIG_SYS_PCIE4_MEM_VIRT   0xb0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS    0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS   0xc30000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE   0x10000000  /* 256M */
+#define CONFIG_SYS_PCIE4_IO_VIRT    0xf8030000
+#define CONFIG_SYS_PCIE4_IO_BUS     0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS    0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE    0x00010000  /* 64k */
+#endif
+
+#define CONFIG_E1000
+#define CONFIG_E1000_SPI
+#define CONFIG_CMD_E1000
+
+#define CONFIG_PCI_SCAN_SHOW        /* show pci devices on startup */
+/* #define CONFIG_DOS_PARTITION */
+#endif  /* CONFIG_PCI */
+
+/* SATA */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CONFIG_SYS_SATA_MAX_DEVICE  2
+
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1            CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS      FLAGS_DMA
+
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2            CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS      FLAGS_DMA
+
+#define CONFIG_LBA48
+/* #define CONFIG_DOS_PARTITION */
+#endif
+
+#define CONFIG_SPI_FLASH_MTD
+
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_HAS_FSL_DR_USB
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif /* CONFIG_USB_EHCI*/ 
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+/* #define CONFIG_GENERIC_MMC */
+#define CONFIG_CMD_EXT2
+/*#define CONFIG_CMD_FAT*/
+/* #define CONFIG_DOS_PARTITION */
+#endif
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS     10
+#define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_QMAN_NUM_PORTALS     10
+#define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+
+
+#define CONFIG_QE
+#define CONFIG_U_QE
+
+#if 0
+/* TODO: move FMAN/QE ucode to boot source */
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
+#define CONFIG_SYS_QE_FW_ADDR			(512 * 0x920)
+#endif
+#endif
+#if defined(CONFIG_NAND_FLASH_BOOT)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR		(0x240000)	/* Refer to mtdparts: fman_ucode */
+
+/* #define CONFIG_SYS_QE_FW_IN_NAND
+#define CONFIG_SYS_QE_FW_LENGTH		(0x10000) */
+#define CONFIG_SYS_QE_FW_ADDR		(0x280000)	/* Refer to mtdparts: qe_ucode */
+
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR		0xe8240000	/* Refer to mtdparts: fman_ucode */
+#define CONFIG_SYS_QE_FW_ADDR  		0xe8280000	/* Refer to mtdparts: qe_ucode */
+/* __stringify(CONFIG_LOADADDR) */
+#endif
+
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
+#define CONFIG_SYS_FDT_PAD      (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+/*#define CONFIG_PHY_MARVELL*/
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_RGMII1_PHY_ADDR      0x00
+#define CONFIG_SYS_RGMII2_PHY_ADDR      0x01
+
+#define CONFIG_MII          /* MII PHY management */
+#define CONFIG_ETHPRIME     "FM1@DTSEC4"
+#define CONFIG_PHY_GIGE     /* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO               /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+/*#define CONFIG_CMD_ERRATA*/
+#define CONFIG_CMD_GREPENV
+/*#define CONFIG_CMD_IRQ*/
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+/*#define CONFIG_CMD_REGINFO*/
+
+#ifdef CONFIG_PCI
+/*#define CONFIG_CMD_PCI*/
+#endif
+
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+/*#define CONFIG_CMD_HASH*/
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP                     /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	1000000		/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "           /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ    (64 << 20)  /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN    (64 << 20)  /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+/*#define CONFIG_CMD_MTDPARTS*/
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_NOR_FLASH
+
+/*#define CONFIG_SYS_NO_FLASH*/
+
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#define CONFIG_CMD_BLOB
+#endif
+
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+/* #define CONFIG_UBI_SILENCE_MSG */
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#if defined(CONFIG_SPI_FLASH)
+#define CONFIG_FSL_ESPI
+
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SPANSION
+
+/*#define CONFIG_CMD_SF*/
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_SPEED	10000000
+#define CONFIG_SF_DEFAULT_MODE	0
+#endif
+
+#define MTDIDS_DEFAULT \
+	"nand0=fff800000.flash," \
+	"nor0=fe8000000.nor"
+
+#define MTDPART_DEFAULT_PARTITIONS \
+	"2M@0x0(u-boot)," \
+	"256k(env)," \
+	"256k(fman_ucode)," \
+	"256k(qe_ucode),"
+
+
+#ifdef CONFIG_NAND_FLASH
+
+#endif
+#ifdef CONFIG_NOR_FLASH
+	
+#endif
+#define MTDPARTS_DEFAULT    \
+	"mtdparts=fff800000.flash:" \
+		MTDPART_DEFAULT_PARTITIONS \
+		"0x3fc80000(ubipart_nand)," \
+		"1M@0x3ff00000(bbt)ro;" \
+	"fe8000000.nor:" \
+		MTDPART_DEFAULT_PARTITIONS \
+		"-(ubipart_nor)"
+
+#ifdef CONFIG_NOR_FLASH
+#define NOR_ENV	\
+	"update-uboot-nor-nw=" \
+		"dhcp; tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin.nor;" \
+		"if test $? = \"0\"; then " \
+			"protect off 0xe8000000 0xe81fffff;" \
+			"erase 0xe8000000 0xe81fffff;" \
+			"cp.w ${loadaddr} 0xe8000000 ${filesize};" \
+		"fi\0" \
+	"update-uboot-nor-usb=" \
+		"usb start;" \
+		"fatload usb 0 ${loadaddr} u-boot-with-spl-pbl.bin.nor;" \
+		"if test $? = \"0\"; then " \
+			"protect off 0xe8000000 0xe81fffff;" \
+			"erase 0xe8000000 0xe81fffff;" \
+			"cp.w ${loadaddr} 0xe8000000 ${filesize};" \
+		"fi\0" \
+	\
+	"update-fman-ucode-nor-usb=" \
+		"usb start;" \
+		"fatload usb 0 ${loadaddr} fsl_fman_ucode_t1040_r1.1_106_4_17.bin;" \
+		"if test $? = \"0\"; then " \
+			"protect off 0xe8240000 0xe827ffff;" \
+			"erase 0xe8240000 0xe827ffff;" \
+			"cp.w ${loadaddr} 0xe8240000 ${filesize};" \
+		"fi\0" \
+	"update-qe-ucode-nor-usb=" \
+		"usb start;" \
+		"fatload usb 0 ${loadaddr} iram_Type_A_T1040_r1.0.bin;" \
+		"if test $? = \"0\"; then " \
+			"protect off 0xe8280000 0xe82bffff;" \
+			"erase 0xe8280000 0xe82bffff;" \
+			"cp.w ${loadaddr} 0xe8280000 ${filesize};" \
+		"fi\0" \
+	"update-ubi-rootfs-nor="\
+		"dhcp;" \
+		"ubi part ubipart_nor;" \
+		"if test $? = \"0\"; then " \
+			"tftp ${TFTP_PATH}/ubi_rootfs_image.nor.ubifs;" \
+			"if test $? = \"0\"; then " \
+				"ubi write ${loadaddr} rootfs ${filesize};" \
+			"fi;" \
+		"fi;" \
+		"\0" \
+	\
+	"ubiboot-nor=" \
+		"ubi part ubipart_nor;" \
+		"ubifsmount ubi0:rootfs;" \
+		"ubifsload ${fitaddr} /boot/fitImage.itb;" \
+		"run set_ubiboot_args_nor;" \
+		"bootm ${fitaddr}#conf@1" \
+		"\0" \
+	\
+	"set_ubiboot_args_nor=setenv bootargs ${bootargs} ${mtdparts} ubi.mtd=ubipart_nor ubi.fm_autoconvert=1 root=ubi0:rootfs rw rootfstype=ubifs \0"
+#else
+#define NOR_ENV
+#endif
+
+#ifdef CONFIG_NAND_FLASH
+#define NAND_ENV \
+    "update-uboot-nand-nw=" \
+        "dhcp;" \
+        "tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin.nand;" \
+        "if test $? = \"0\"; then " \
+            "nand erase.part u-boot;" \
+            "nand write ${loadaddr} 0 ${filesize}; "\
+        "fi\0" \
+    "update-uboot-nand-usb=" \
+        "usb start;" \
+        "fatload usb 0 ${loadaddr} u-boot-with-spl-pbl.bin.nand;" \
+        "nand erase.part u-boot;" \
+        "nand write ${loadaddr} u-boot ${filesize};" \
+        "\0" \
+    \
+    "update-fman-ucode-nand-usb=" \
+        "usb start;" \
+        "fatload usb 0 ${loadaddr} fsl_fman_ucode_t1040_r1.1_106_4_17.bin;" \
+        "nand erase.part fman_ucode;" \
+        "nand write ${loadaddr} fman_ucode ${filesize};" \
+        "\0" \
+    \
+    "update-qe-ucode-nand-usb=" \
+        "usb start;" \
+        "fatload usb 0 ${loadaddr} iram_Type_A_T1040_r1.0.bin;" \
+        "nand erase.part qe_ucode;" \
+        "nand write ${loadaddr} qe_ucode ${filesize};" \
+        "\0" \
+    "update-ubi-rootfs-nand="\
+        "dhcp;" \
+        "ubi part ubipart_nand;" \
+        "if test $? = \"0\"; then " \
+            "tftp ${TFTP_PATH}/ubi_rootfs_image.nand.ubifs;" \
+            "if test $? = \"0\"; then " \
+                "ubi write ${loadaddr} rootfs ${filesize};" \
+            "fi;" \
+        "fi;" \
+    "\0" \
+    \
+    "ubiboot-nand=" \
+        "ubi part ubipart_nand;" \
+        "ubifsmount ubi0:rootfs;" \
+        "ubifsload ${fitaddr} /boot/fitImage.itb;" \
+        "run set_ubiboot_args_nand;" \
+        "bootm ${fitaddr}#conf@1" \
+        "\0" \
+    \
+    "set_ubiboot_args_nand=setenv bootargs ${bootargs} ${mtdparts} ubi.mtd=ubipart_nand ubi.fm_autoconvert=1 root=ubi0:rootfs rw rootfstype=ubifs \0"
+#else
+#define NAND_ENV
+#endif
+
+#ifdef CONFIG_NAND_FLASH_BOOT
+#define BOOTCMD "ubiboot-nand"
+#elif defined(CONFIG_NOR_FLASH_BOOT)
+#define BOOTCMD "ubiboot-nor"
+#else
+#define BOOTCMD ""
+#endif
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+#define CONFIG_BAUDRATE		115200
+
+
+#define __USB_PHY_TYPE  utmi
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+    "hwconfig=" \
+        "fsl_ddr:bank_intlv=null;"\
+        "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+        "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+    \
+    "l2switchaddr=02:00:00:ba:be:00\0" \
+    "ethaddr=02:00:00:ba:be:01\0" \
+    "eth1addr=02:00:00:ba:be:02\0" \
+    "eth2addr=02:00:00:ba:be:03\0" \
+    "eth3addr=02:00:00:ba:be:04\0" \
+    "eth4addr=02:00:00:ba:be:05\0" \
+    \
+    "autoload=no\0" \
+    "fitaddr="__stringify(CONFIG_LOADADDR)"\0" \
+    "TFTP_PATH=\0" \
+    \
+    "mtdids=" MTDIDS_DEFAULT "\0" \
+    "mtdparts=" MTDPARTS_DEFAULT "\0" \
+    \
+    NOR_ENV \
+    NAND_ENV \
+    \
+    "setfans=i2c dev 0; i2c mw 0x2e 0x40 1;i2c mw 0x2e 0x7d 0x2;" \
+        "i2c mw 0x2e 0x5c 0xe0;i2c mw 0x2e 0x5d 0xe0;i2c mw 0x2e 0x5e 0xe0;" \
+        "i2c mw 0x2e 0x5f 0xc8;i2c mw 0x2e 0x60 0xc8;i2c mw 0x2e 0x61 0xc8;" \
+        "i2c mw 0x2e 0x30 0x20;i2c mw 0x2e 0x31 0x20;i2c mw 0x2e 0x32 0x20;\0"\
+    \
+    "probe-spi-flash=sf probe 0; if test $? = \"0\"; then " \
+	"setenv mtdids \"${mtdids}\",nor1=fe110000.spi;" \
+	"setenv mtdparts \"${mtdparts};\"fe110000.spi:" MTDPART_DEFAULT_PARTITIONS "-(storage);"\
+	";fi\0" \
+    \
+    "netboot=dhcp; tftp ${fitaddr} ${TFTP_PATH}/fitImage.itb; bootm ${fitaddr}#conf@1\0" \
+    \
+    "bootcmd=run setfans; run "BOOTCMD"\0" \
+    \
+    "bootargs_sata=rootfstype=ext3 root=/dev/sda1\0" \
+    "bootargs=console=ttyS0,115200 rootwait panic=10\0" \
+
+#endif	/* _QT1040_1GB_H */
diff --git a/include/configs/simc-t10x0.h b/include/configs/simc-t10x0.h
index 75cae27..743ba29 100644
--- a/include/configs/simc-t10x0.h
+++ b/include/configs/simc-t10x0.h
@@ -1,3 +1,9 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * 
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
 #ifndef _SIMC_T10X0
 #define _SIMC_T10X0
 
@@ -15,4 +21,4 @@
 #endif
 
 
-#endif /* _SIMC_T10X0 */
\ No newline at end of file
+#endif /* _SIMC_T10X0 */
diff --git a/include/configs/simc-t10xx.h b/include/configs/simc-t10xx.h
index 09a9d6d..1c0c677 100644
--- a/include/configs/simc-t10xx.h
+++ b/include/configs/simc-t10xx.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2016 Scalys B.V.
+ * Copyright 2017 Scalys B.V.
  * 
  * SPDX-License-Identifier:     GPL-2.0+
  */
@@ -10,56 +10,103 @@
 #include "simc-t10x0.h"
 #include <generated/autoconf.h>
 
+
+
+#define CONFIG_MTD_UBI_WL_THRESHOLD	4096
+#define CONFIG_MTD_UBI_BEB_LIMIT	20
+
+
 #define MPC85XX_GPIO_NR(port, pin)     ((((port)-1)*32)+((pin)&31))
 
 /*
  * SIMC-T10xx board configuration file
  */
-#define CONFIG_PHYS_64BIT
-#define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)    /* MT29F8G08ABBCAH4*/
 
 /*
  * System and DDR clock
  */
-#if defined(CONFIG_SYS_CLK_FREQ_66)
-#define CONFIG_SYS_CLK_FREQ		 66666666	/* 66.6 MHz */
-#elif defined(CONFIG_SYS_CLK_FREQ_100)
 #define CONFIG_SYS_CLK_FREQ		100000000	/* 100 MHz */
-#endif
-
 #define CONFIG_DDR_CLK_FREQ		133333333	/* 133.33MHz */
 
 #ifdef CONFIG_RAMBOOT_PBL
 
 
 
-/* PBI commands are cpu independent for now */
-/*#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg*/
-
-#ifdef CONFIG_SECURE_BOOT
-/* Secure boot enabled */
-#define CONFIG_SYS_FSL_PBL_PBI \
-	$(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_nand_secure_pbi.cfg
+/* We have to specify all the PBL and RCW since they are used without being 
+ * proccessed by the preprocessor */
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_NAND_FLASH_BOOT)
+/* Secure boot from NAND flash */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_nand_secure_pbi.cfg
+#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_NOR_FLASH_BOOT)
+/* Secure boot from NOR flash */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_nor_secure_pbi.cfg
+#elif defined(CONFIG_NAND_FLASH_BOOT)
+/* normal boot from NAND flash */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_nand_pbi.cfg
+#elif defined(CONFIG_NOR_FLASH_BOOT)
+/* normal boot from NOR flash */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_nor_pbi.cfg
+#elif defined(CONFIG_SPI_FLASH_BOOT)
+/* normal boot frop SPI flash */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_spi_pbi.cfg
+#elif defined(CONFIG_SDHC_FLASH_BOOT)
+/* normal boot fro sdhc flash */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_sdhc_pbi.cfg
 #else
-/* Secure boot disabled */
-#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t10xx/simc-t10xx_pbi.cfg
+/* unknown configuration, this should not happen */
+#error Invalid Boot configuration
 #endif
 
-
-
-
 /* Set the RCW config depending on the CPU type */
+#if   ( defined(CONFIG_PPC_T1022) || defined(CONFIG_PPC_T1042)) && \
+	defined(CONFIG_SECURE_BOOT) && defined(CONFIG_NAND_FLASH_BOOT)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x2_nand_secure_rcw.cfg
+#elif ( defined(CONFIG_PPC_T1022) || defined(CONFIG_PPC_T1042)) && \
+	defined(CONFIG_SECURE_BOOT) && defined(CONFIG_NOR_FLASH_BOOT)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x2_nor_secure_rcw.cfg
+#elif ( defined(CONFIG_PPC_T1022) || defined(CONFIG_PPC_T1042)) && \
+	defined(CONFIG_NAND_FLASH_BOOT)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x2_nand_rcw.cfg
+#elif ( defined(CONFIG_PPC_T1022) || defined(CONFIG_PPC_T1042)) && \
+	defined(CONFIG_NOR_FLASH_BOOT)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x2_nor_rcw.cfg
+#elif ( defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1040)) && \
+	defined(CONFIG_SECURE_BOOT) && defined(CONFIG_NAND_FLASH_BOOT)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x0_nand_secure_rcw.cfg
+#elif ( defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1040)) && \
+	defined(CONFIG_SECURE_BOOT) && defined(CONFIG_NOR_FLASH_BOOT)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x0_nor_secure_rcw.cfg
+#elif ( defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1040)) && \
+	defined(CONFIG_NAND_FLASH_BOOT)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x0_nand_rcw.cfg
+#elif ( defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1040)) && \
+	defined(CONFIG_NOR_FLASH_BOOT)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x0_nor_rcw.cfg
+#elif ( defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1040)) && \
+	defined(CONFIG_SPI_FLASH_BOOT)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x0_spi_rcw.cfg
+#elif ( defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1040)) && \
+	defined(CONFIG_SDHC_FLASH_BOOT)
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t10x0_sdhc_rcw.cfg
+#else
+/* unknown configuration, this should not happen */
+#error Invalid Boot configuration
+#endif
+
+#if 0
 #if defined(CONFIG_PPC_T1022)
 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1022_rcw.cfg
 #elif defined(CONFIG_PPC_T1040)
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1040_nand_secure_rcw.cfg
 #else
-#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1040_rcw.cfg
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1040_nor_rcw.cfg
+/*#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t10xx/simc-t1040_rcw.cfg*/
 #endif
 #endif
+#endif 
 
 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 #define CONFIG_SPL_ENV_SUPPORT
@@ -72,7 +119,6 @@
 #define CONFIG_SPL_I2C_SUPPORT
 
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
-#define CONFIG_FSL_LAW                  /* Use common FSL init code */
 #define CONFIG_SYS_TEXT_BASE            0x30001000
 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
 #define CONFIG_SPL_PAD_TO               0x40000
@@ -89,10 +135,9 @@
 
 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 
-#ifdef CONFIG_NAND
+#ifdef CONFIG_NAND_FLASH
 #define CONFIG_SPL_NAND_SUPPORT
 
-
 #define CONFIG_SYS_NAND_U_BOOT_SIZE	( (2048-256) *1024)
 #define CONFIG_U_BOOT_HDR_SIZE		(16 << 10)
 
@@ -100,10 +145,16 @@
 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
+#ifndef CONFIG_SDHC_FLASH_BOOT 
 #define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
 #define CONFIG_SPL_NAND_BOOT
+#endif
 #endif /* CONFIG_NAND */
 
+#ifdef CONFIG_SDHC_FLASH_BOOT
+#define CONFIG_SDCARD
+#endif
+
 #ifdef CONFIG_SDCARD
 #define	CONFIG_RESET_VECTOR_ADDRESS	0x30000FFC
 #define CONFIG_SPL_MMC_SUPPORT
@@ -122,10 +173,7 @@
 #endif /* CONFIG_RAMBOOT_PBL */
 
 /* High Level Configuration Options */
-#define CONFIG_E500                     /* BOOKE e500 family */
 #include <asm/config_mpc85xx.h>
-#define CONFIG_BOOKE
-#define CONFIG_E500MC                   /* BOOKE e500mc family */
 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
 #define CONFIG_MP                       /* support multiple processors */
 
@@ -138,15 +186,11 @@
 #endif /* CONFIG_RESET_VECTOR_ADDRESS */
 
 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
-#define CONFIG_FSL_IFC                  /* Enable IFC Support */
+#define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
 
-
-#define CONFIG_PCI                      /* Enable PCI/PCIE */
 #define CONFIG_PCI_INDIRECT_BRIDGE
 
-
 /* The number of available PCI controllers depends on the RCW */
 #define CONFIG_PCIE1                    /* PCIE controler 1 */
 #define CONFIG_PCIE2                    /* PCIE controler 2 */
@@ -156,10 +200,16 @@
 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
 
-#define CONFIG_FSL_LAW                  /* Use common FSL init code */
-
 #define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SIZE                 0x2000
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET               0x200000 /* Refer to mtdparts */
+/* 
+ *  CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|SATA|SPI_FLASH|NVRAM|MMC|FAT|EXT4|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
+ */
 
+#if 0
+/* TODO: move env to boot source */
 #if defined(CONFIG_SDCARD)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_MMC
@@ -177,6 +227,7 @@
 #define CONFIG_ENV_SIZE                 0x2000
 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 #endif /* CONFIG_SPIFLASH */
+#endif 
 
 /*
  * These can be toggled for performance analysis, otherwise use default.
@@ -198,7 +249,8 @@
 #define CONFIG_SYS_NUM_ADDR_MAP         64  /* number of TLB1 entries */
 
 /* #define CONFIG_SYS_DRAM_TEST         Executes a memoty test at U-Boot start */
-#define CONFIG_SYS_MEMTEST_START        0x00200000  /* memtest works on */
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START        0x00200000
 #define CONFIG_SYS_MEMTEST_END          0x00400000
 #define CONFIG_SYS_ALT_MEMTEST
 
@@ -244,16 +296,16 @@
 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4)
 
 #define CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_FSL_DDR3
 
 #define CONFIG_SYS_SDRAM_SIZE           8192    /* In MByte, for fixed parameter use */
 
 /*
  * IFC Definitions
  */
+#ifdef CONFIG_NOR_FLASH
 #define CONFIG_SYS_FLASH_BASE           0xe8000000
 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-
+#endif
 
 /* NAND Flash on IFC */
 #define CONFIG_NAND_FSL_IFC
@@ -274,11 +326,11 @@
 					 CSOR_NAND_RAL_3 |	/* RAL = 3Byes */ \
 					 CSOR_NAND_PGS_2K |	/* Page Size = 2K */ \
 					 CSOR_NAND_SPRZ_128 |	/* Spare size = 128 */ \
-					 CSOR_NAND_PB(64))	/* Pages Per Block = 64 */
+					 CSOR_NAND_PB(64) |	/* Pages Per Block = 64 */ \
+					 CSOR_NAND_BCTLD)	/* Buffer control disable */
 
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 
-/* ONFI NAND Flash mode0 Timing Params */
 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
                                         FTIM0_NAND_TWP(0x18)   | \
                                         FTIM0_NAND_TWCHT(0x07) | \
@@ -293,43 +345,59 @@
                                         FTIM2_NAND_TREH(0x0a) | \
                                         FTIM2_NAND_TWHRE(0x1e))
                                         
-#define CONFIG_SYS_NAND_FTIM3           0x0
+#define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0xa)
 
 #define CONFIG_SYS_NAND_DDR_LAW         11
 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 /*#define CONFIG_CMD_NAND*/
 
+
+/* NOR configuation */
+/*#define CONFIG_SYS_NO_FLASH*/
+#define CONFIG_MTD
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH    FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_PROTECTION
+/*#define CONFIG_SYS_NOR_BASE		(0xe8000000)
+#define CONFIG_SYS_NOR_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NOR_BASE)
+*/
+#define CONFIG_SYS_FLASH_BASE           0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 #define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
 
-#if defined(CONFIG_NAND)
-#define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
-#else
-#define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR_CSPR_EXT
-#define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
-#define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
-#define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
-#define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
-#define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
-#define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
-#define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
-#define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
-#define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
-#define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
-#define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
-#define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
-#define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
-#define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
-#define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
-#endif
+
+#define CONFIG_SYS_NOR_CSPR_EXT        (0xf)
+#define CONFIG_SYS_NOR_CSPR            (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+					CSPR_PORT_SIZE_16 | \
+					CSPR_MSEL_NOR | \
+					CSPR_V)
+
+#define CONFIG_SYS_NOR_AMASK           IFC_AMASK(32*1024*1024)
+
+#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_AVD_TGL_PGM_EN |	/* AVD Toggle Enable during Burst Program */ \
+					 CSOR_NOR_ADM_SHIFT(7) |	/* Address Data Multiplexing Shift */ \
+					 CSOR_NOR_TRHZ_80) |		/* Time for Read Enable High to Output High Impedance */ \
+					 CSOR_NAND_BCTLD		/* Buffer control disable */
+
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
 
 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
@@ -473,13 +541,12 @@
 #define CONFIG_SYS_PCIE4_IO_SIZE    0x00010000  /* 64k */
 #endif
 
-#define CONFIG_PCI_PNP          /* do pci plug-and-play */
 #define CONFIG_E1000
 #define CONFIG_E1000_SPI
 #define CONFIG_CMD_E1000
 
 #define CONFIG_PCI_SCAN_SHOW        /* show pci devices on startup */
-#define CONFIG_DOS_PARTITION
+/* #define CONFIG_DOS_PARTITION */
 #endif  /* CONFIG_PCI */
 
 /* SATA */
@@ -499,9 +566,10 @@
 #define CONFIG_SYS_SATA2_FLAGS      FLAGS_DMA
 
 #define CONFIG_LBA48
-#define CONFIG_DOS_PARTITION
+/* #define CONFIG_DOS_PARTITION */
 #endif
 
+#define CONFIG_SPI_FLASH_MTD
 
 #define CONFIG_USB_EHCI_FSL
 #define CONFIG_HAS_FSL_DR_USB
@@ -510,17 +578,15 @@
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 #endif /* CONFIG_USB_EHCI*/ 
 
-#define CONFIG_MMC
-
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 #define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
+/* #define CONFIG_GENERIC_MMC */
 #define CONFIG_CMD_EXT2
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
+/*#define CONFIG_CMD_FAT*/
+/* #define CONFIG_DOS_PARTITION */
 #endif
 
 /* Qman/Bman */
@@ -556,8 +622,9 @@
 
 #define CONFIG_QE
 #define CONFIG_U_QE
-#define CONFIG_SYS_QE_FW_ADDR  __stringify(CONFIG_LOADADDR)
 
+#if 0
+/* TODO: move FMAN/QE ucode to boot source */
 /* Default address of microcode for the Linux Fman driver */
 #if defined(CONFIG_SDCARD)
 /*
@@ -567,22 +634,34 @@
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
-#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FW_ADDR			(512 * 0x920)
+
+
+#el
+#endif
+#endif
+#if defined(CONFIG_NAND_FLASH_BOOT)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR		(0x240000)	/* Refer to mtdparts: fman_ucode */
+
+/* #define CONFIG_SYS_QE_FW_IN_NAND
+#define CONFIG_SYS_QE_FW_LENGTH		(0x10000) */
+#define CONFIG_SYS_QE_FW_ADDR		(0x280000)	/* Refer to mtdparts: qe_ucode */
+
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
-#define CONFIG_SYS_FMAN_FW_ADDR		0xEFF00000
+#define CONFIG_SYS_FMAN_FW_ADDR		0xe8240000	/* Refer to mtdparts: fman_ucode */
+#define CONFIG_SYS_QE_FW_ADDR  		0xe8280000	/* Refer to mtdparts: qe_ucode */
+/* __stringify(CONFIG_LOADADDR) */
 #endif
 
-
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 #define CONFIG_SYS_FDT_PAD      (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif /* CONFIG_NOBQFMAN */
 
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_FMAN_ENET
-#define CONFIG_PHY_MARVELL
+/*#define CONFIG_PHY_MARVELL*/
 #endif
 
 #ifdef CONFIG_FMAN_ENET
@@ -603,20 +682,20 @@
 /*
  * Command line configuration.
  */
-#define CONFIG_CMD_ERRATA
+/*#define CONFIG_CMD_ERRATA*/
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_IRQ
+/*#define CONFIG_CMD_IRQ*/
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
+/*#define CONFIG_CMD_REGINFO*/
 
 #ifdef CONFIG_PCI
-#define CONFIG_CMD_PCI
+/*#define CONFIG_CMD_PCI*/
 #endif
 
 /* Hash command with SHA acceleration supported in hardware */
 #ifdef CONFIG_FSL_CAAM
-#define CONFIG_CMD_HASH
+/*#define CONFIG_CMD_HASH*/
 #define CONFIG_SHA_HW_ACCEL
 #endif
 
@@ -652,11 +731,12 @@
 /*
  * Dynamic MTD Partition support with mtdparts
  */
-#define CONFIG_CMD_MTDPARTS
+/*#define CONFIG_CMD_MTDPARTS*/
 #define CONFIG_MTD_DEVICE
 #define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_NOR_FLASH
 
-#define CONFIG_SYS_NO_FLASH
+/*#define CONFIG_SYS_NO_FLASH*/
 
 
 #ifdef CONFIG_SECURE_BOOT
@@ -673,7 +753,7 @@
 /*
  * eSPI - Enhanced SPI
  */
-#define CONFIG_SPI_FLASH
+#if defined(CONFIG_SPI_FLASH)
 #define CONFIG_FSL_ESPI
 
 #define CONFIG_SPI_FLASH_STMICRO
@@ -683,104 +763,196 @@
 #define CONFIG_SPI_FLASH_BAR
 #define CONFIG_SF_DEFAULT_SPEED	10000000
 #define CONFIG_SF_DEFAULT_MODE	0
+#endif
 
 #define MTDIDS_DEFAULT \
-	"nor0=fe8000000.nor," \
 	"nand0=fff800000.flash," \
-	"spi0=spife110000.0"
+	"nor0=fe8000000.nor"
 
-#define MTDPARTS_DEFAULT    \
-	"mtdparts=fff800000.flash:" \
+#define MTDPART_DEFAULT_PARTITIONS \
 	"2M@0x0(u-boot)," \
 	"256k(env)," \
 	"256k(fman_ucode)," \
-	"256k(qe_ucode)," \
-	"0x3fc80000(ubipart)," \
-	"1M@0x3ff00000(bbt)ro"
+	"256k(qe_ucode),"
 
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		1000000
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* Also check for boot interruption, when bootdelay is zero */
-#define CONFIG_BAUDRATE		115200
 
+#ifdef CONFIG_NAND_FLASH
 
-#define __USB_PHY_TYPE  utmi
+#endif
+#ifdef CONFIG_NOR_FLASH
+	
+#endif
+#define MTDPARTS_DEFAULT    \
+	"mtdparts=fff800000.flash:" \
+		MTDPART_DEFAULT_PARTITIONS \
+		"0x3fc80000(ubipart_nand)," \
+		"1M@0x3ff00000(bbt)ro;" \
+	"fe8000000.nor:" \
+		MTDPART_DEFAULT_PARTITIONS \
+		"-(ubipart_nor)"
+
+#ifdef CONFIG_NOR_FLASH
+#define NOR_ENV	\
+	"update-uboot-nor-nw=" \
+		"dhcp; tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin.nor;" \
+		"if test $? = \"0\"; then " \
+			"protect off 0xe8000000 0xe81fffff;" \
+			"erase 0xe8000000 0xe81fffff;" \
+			"cp.w ${loadaddr} 0xe8000000 ${filesize};" \
+		"fi\0" \
+	"update-uboot-nor-usb=" \
+		"usb start;" \
+		"fatload usb 0 ${loadaddr} u-boot-with-spl-pbl.bin.nor;" \
+		"if test $? = \"0\"; then " \
+			"protect off 0xe8000000 0xe81fffff;" \
+			"erase 0xe8000000 0xe81fffff;" \
+			"cp.w ${loadaddr} 0xe8000000 ${filesize};" \
+		"fi\0" \
+	\
+	"update-fman-ucode-nor-usb=" \
+		"usb start;" \
+		"fatload usb 0 ${loadaddr} fsl_fman_ucode_t1040_r1.1_106_4_17.bin;" \
+		"if test $? = \"0\"; then " \
+			"protect off 0xe8240000 0xe827ffff;" \
+			"erase 0xe8240000 0xe827ffff;" \
+			"cp.w ${loadaddr} 0xe8240000 ${filesize};" \
+		"fi\0" \
+	"update-qe-ucode-nor-usb=" \
+		"usb start;" \
+		"fatload usb 0 ${loadaddr} iram_Type_A_T1040_r1.0.bin;" \
+		"if test $? = \"0\"; then " \
+			"protect off 0xe8280000 0xe82bffff;" \
+			"erase 0xe8280000 0xe82bffff;" \
+			"cp.w ${loadaddr} 0xe8280000 ${filesize};" \
+		"fi\0" \
+	"update-ubi-rootfs-nor="\
+		"dhcp;" \
+		"ubi part ubipart_nor;" \
+		"if test $? = \"0\"; then " \
+			"tftp ${TFTP_PATH}/ubi_rootfs_image.nor.ubifs;" \
+			"if test $? = \"0\"; then " \
+				"ubi write ${loadaddr} rootfs ${filesize};" \
+			"fi;" \
+		"fi;" \
+		"\0" \
+	\
+	"ubiboot-nor=" \
+		"ubi part ubipart_nor;" \
+		"ubifsmount ubi0:rootfs;" \
+		"ubifsload ${fitaddr} /boot/fitImage.itb;" \
+		"run set_ubiboot_args_nor;" \
+		"bootm ${fitaddr}#conf@1" \
+		"\0" \
+	\
+	"set_ubiboot_args_nor=setenv bootargs ${bootargs} ${mtdparts} ubi.mtd=ubipart_nor ubi.fm_autoconvert=1 root=ubi0:rootfs rw rootfstype=ubifs \0"
+#else
+#define NOR_ENV
+#endif
 
-#define CONFIG_EXTRA_ENV_SETTINGS \
-    "hwconfig=" \
-        "fsl_ddr:bank_intlv=null;"\
-        "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
-        "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
-    \
-    "l2switchaddr=02:00:00:ba:be:00\0" \
-    "ethaddr=02:00:00:ba:be:01\0" \
-    "eth1addr=02:00:00:ba:be:02\0" \
-    "eth2addr=02:00:00:ba:be:03\0" \
-    "eth3addr=02:00:00:ba:be:04\0" \
-    "eth4addr=02:00:00:ba:be:05\0" \
-    \
-    "autoload=no\0" \
-    "fitaddr="__stringify(CONFIG_LOADADDR)"\0" \
-    "TFTP_PATH=\0" \
-    \
-    "mtdids=" MTDIDS_DEFAULT "\0" \
-    "mtdparts=" MTDPARTS_DEFAULT "\0" \
-    \
-    "setfans=i2c dev 0; i2c mw 0x2e 0x40 1;i2c mw 0x2e 0x7d 0x2;" \
-        "i2c mw 0x2e 0x5c 0xe0;i2c mw 0x2e 0x5d 0xe0;i2c mw 0x2e 0x5e 0xe0;" \
-        "i2c mw 0x2e 0x5f 0xc8;i2c mw 0x2e 0x60 0xc8;i2c mw 0x2e 0x61 0xc8;" \
-        "i2c mw 0x2e 0x30 0x20;i2c mw 0x2e 0x31 0x20;i2c mw 0x2e 0x32 0x20;\0"\
-    \
-    "update-uboot=dhcp; tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin; if test $? = \"0\"; then nand erase.part u-boot; nand write ${loadaddr} 0 ${filesize};fi\0" \
-    "update-uboot-usb=" \
+#ifdef CONFIG_NAND_FLASH
+#define NAND_ENV \
+    "update-uboot-nand-nw=" \
+        "dhcp;" \
+        "tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin.nand;" \
+        "if test $? = \"0\"; then " \
+            "nand erase.part u-boot;" \
+            "nand write ${loadaddr} 0 ${filesize}; "\
+        "fi\0" \
+    "update-uboot-nand-usb=" \
         "usb start;" \
-        "fatload usb 0 ${loadaddr} u-boot-with-spl-pbl.bin;" \
+        "fatload usb 0 ${loadaddr} u-boot-with-spl-pbl.bin.nand;" \
         "nand erase.part u-boot;" \
         "nand write ${loadaddr} u-boot ${filesize};" \
         "\0" \
     \
-    "update-fman-ucode-usb=" \
+    "update-fman-ucode-nand-usb=" \
         "usb start;" \
         "fatload usb 0 ${loadaddr} fsl_fman_ucode_t1040_r1.1_106_4_17.bin;" \
         "nand erase.part fman_ucode;" \
         "nand write ${loadaddr} fman_ucode ${filesize};" \
         "\0" \
     \
-    "update-qe-ucode-usb=" \
+    "update-qe-ucode-nand-usb=" \
         "usb start;" \
         "fatload usb 0 ${loadaddr} iram_Type_A_T1040_r1.0.bin;" \
         "nand erase.part qe_ucode;" \
         "nand write ${loadaddr} qe_ucode ${filesize};" \
         "\0" \
-    "load_qe_ucode="\
-        "nand read ${loadaddr} qe_ucode;" \
-        "qe fw ${loadaddr};" \
-        "\0" \
-    \
-    "update-ubi-rootfs="\
+    "update-ubi-rootfs-nand="\
         "dhcp;" \
-        "ubi part ubipart;" \
+        "ubi part ubipart_nand;" \
         "if test $? = \"0\"; then " \
-            "tftp ${TFTP_PATH}/fsl-image-core-simc-t1022-tcb-02.ubifs;" \
+            "tftp ${TFTP_PATH}/ubi_rootfs_image.nand.ubifs;" \
             "if test $? = \"0\"; then " \
                 "ubi write ${loadaddr} rootfs ${filesize};" \
             "fi;" \
         "fi;" \
     "\0" \
     \
-    "ubiboot=" \
-        "ubi part ubipart;" \
+    "ubiboot-nand=" \
+        "ubi part ubipart_nand;" \
         "ubifsmount ubi0:rootfs;" \
         "ubifsload ${fitaddr} /boot/fitImage.itb;" \
-        "run set_ubiboot_args;" \
+        "run set_ubiboot_args_nand;" \
         "bootm ${fitaddr}#conf@1" \
         "\0" \
     \
-    "set_ubiboot_args=setenv bootargs ${bootargs} ${mtdparts} ubi.mtd=3 ubi.fm_autoconvert=1 root=ubi0:rootfs rw rootfstype=ubifs \0" \
+    "set_ubiboot_args_nand=setenv bootargs ${bootargs} ${mtdparts} ubi.mtd=ubipart_nand ubi.fm_autoconvert=1 root=ubi0:rootfs rw rootfstype=ubifs \0"
+#else
+#define NAND_ENV
+#endif
+
+#ifdef CONFIG_NAND_FLASH_BOOT
+#define BOOTCMD "ubiboot-nand"
+#elif defined(CONFIG_NOR_FLASH_BOOT)
+#define BOOTCMD "ubiboot-nor"
+#else
+#define BOOTCMD ""
+#endif
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+#define CONFIG_BAUDRATE		115200
+
+
+#define __USB_PHY_TYPE  utmi
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+    "hwconfig=" \
+        "fsl_ddr:bank_intlv=null;"\
+        "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+        "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+    \
+    "l2switchaddr=02:00:00:ba:be:00\0" \
+    "ethaddr=02:00:00:ba:be:01\0" \
+    "eth1addr=02:00:00:ba:be:02\0" \
+    "eth2addr=02:00:00:ba:be:03\0" \
+    "eth3addr=02:00:00:ba:be:04\0" \
+    "eth4addr=02:00:00:ba:be:05\0" \
+    \
+    "autoload=no\0" \
+    "fitaddr="__stringify(CONFIG_LOADADDR)"\0" \
+    "TFTP_PATH=\0" \
+    \
+    "mtdids=" MTDIDS_DEFAULT "\0" \
+    "mtdparts=" MTDPARTS_DEFAULT "\0" \
+    \
+    NOR_ENV \
+    NAND_ENV \
+    \
+    "setfans=i2c dev 0; i2c mw 0x2e 0x40 1;i2c mw 0x2e 0x7d 0x2;" \
+        "i2c mw 0x2e 0x5c 0xe0;i2c mw 0x2e 0x5d 0xe0;i2c mw 0x2e 0x5e 0xe0;" \
+        "i2c mw 0x2e 0x5f 0xc8;i2c mw 0x2e 0x60 0xc8;i2c mw 0x2e 0x61 0xc8;" \
+        "i2c mw 0x2e 0x30 0x20;i2c mw 0x2e 0x31 0x20;i2c mw 0x2e 0x32 0x20;\0"\
+    \
+    "probe-spi-flash=sf probe 0; if test $? = \"0\"; then " \
+	"setenv mtdids \"${mtdids}\",nor1=fe110000.spi;" \
+	"setenv mtdparts \"${mtdparts};\"fe110000.spi:" MTDPART_DEFAULT_PARTITIONS "-(storage);"\
+	";fi\0" \
     \
     "netboot=dhcp; tftp ${fitaddr} ${TFTP_PATH}/fitImage.itb; bootm ${fitaddr}#conf@1\0" \
     \
-    "bootcmd=run setfans; usb start; run ubiboot\0" \
+    "bootcmd=run setfans; run "BOOTCMD"\0" \
     \
     "bootargs_sata=rootfstype=ext3 root=/dev/sda1\0" \
     "bootargs=console=ttyS0,115200 rootwait panic=10\0" \
diff --git a/include/configs/simc-t2081.h b/include/configs/simc-t2081.h
new file mode 100644
index 0000000..0e3908f
--- /dev/null
+++ b/include/configs/simc-t2081.h
@@ -0,0 +1,882 @@
+/*
+ * Copyright 2017 Scalys B.V.
+ * 
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+/* TODO:
+ * Update uboot environment variables.
+ * U-boot without spl? (fails when building).
+ * Add other boot options.
+ * 
+ */
+
+#ifndef __SIMC_T2081_H
+#define __SIMC_T2081_H
+
+#define CONFIG_FSL_SATA_V2
+
+#include <generated/autoconf.h>
+
+#define CONFIG_MTD_UBI_WL_THRESHOLD	4096
+#define CONFIG_MTD_UBI_BEB_LIMIT	20
+
+#define MPC85XX_GPIO_NR(port, pin)     ((((port)-1)*32)+((pin)&31))
+
+/*
+ * SIMC-t2081 board configuration file
+ */
+#define CONFIG_SYS_NAND_BLOCK_SIZE      (256 * 1024)    /* MT29F8G08ABBCAH4*/
+
+/*
+ * System and DDR clock
+ */
+#define CONFIG_SYS_CLK_FREQ		100000000	/* 100 MHz */
+#define CONFIG_DDR_CLK_FREQ		133333333	/* 133.33MHz */
+
+#ifdef CONFIG_RAMBOOT_PBL
+
+/* Todo boot sources */
+#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/scalys/simc-t2081/simc-t2081_nand_pbi.cfg
+
+#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
+/* Todo boot sources */
+
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+
+#define CONFIG_SPL_I2C_SUPPORT
+
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SYS_TEXT_BASE            0x30001000
+#define CONFIG_SPL_TEXT_BASE            0xFFFD8000
+#define CONFIG_SPL_PAD_TO               0x40000
+#define CONFIG_SPL_MAX_SIZE             0x28000
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#endif /* CONFIG_SPL_BUILD */
+
+#define RESET_VECTOR_OFFSET             0x27FFC
+#define BOOT_PAGE_OFFSET                0x27000
+
+#define CONFIG_SYS_MAX_FLASH_BANKS      1
+
+#ifdef CONFIG_NAND_FLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	( (2048-256) *1024)
+#define CONFIG_U_BOOT_HDR_SIZE		(16 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
+#define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
+#define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif /* CONFIG_NAND */
+
+#ifdef CONFIG_SDCARD
+#define	CONFIG_RESET_VECTOR_ADDRESS	0x30000FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST	(0x30000000)
+#define CONFIG_SYS_MMC_U_BOOT_START	(0x30000000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS	(260 << 10)
+#define CONFIG_SYS_LDSCRIPT		"arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define	CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#endif /* CONFIG_RAMBOOT_PBL */
+
+/* High Level Configuration Options */
+#include <asm/config_mpc85xx.h>
+#define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
+#define CONFIG_MP                       /* support multiple processors */
+
+/* #define CONFIG_DEEP_SLEEP */    /* support deep sleep */
+#define CONFIG_SILENT_CONSOLE
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
+#endif /* CONFIG_RESET_VECTOR_ADDRESS */
+
+#define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
+/* #define CONFIG_FSL_IFC                 TODO re-enable? Enable IFC Support */
+#define CONFIG_FSL_CAAM			/* Enable SEC/CAAM */
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_ENV_SIZE                 0x2000
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET               0x200000 /* Refer to mtdparts */
+/* 
+ *  CONFIG_ENV_IS_IN_{EEPROM|FLASH|DATAFLASH|ONENAND|SATA|SPI_FLASH|NVRAM|MMC|FAT|EXT4|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
+ */
+
+#if 0
+#if defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE                 0x2000
+#define CONFIG_ENV_OFFSET               (512 * 0x800)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE                 0x2000
+#define CONFIG_ENV_OFFSET               0x200000 /* Refer to mtdparts */
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE                 0x2000
+#define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
+#endif /* CONFIG_SPIFLASH */
+#endif 
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+/*#define CONFIG_BACKSIDE_L2_CACHE*/
+/*#define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E*/
+#define CONFIG_BTB                      /* toggle branch predition */
+#define CONFIG_DDR_ECC
+
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE           0x0BADC0DE
+#endif /* CONFIG_DDR_ECC */
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP         64  /* number of TLB1 entries */
+
+/* #define CONFIG_SYS_DRAM_TEST         Executes a memoty test at U-Boot start */
+#define CONFIG_CMD_MEMTEST         
+#define CONFIG_SYS_MEMTEST_START        0x00200000
+#define CONFIG_SYS_MEMTEST_END          0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+
+#define CONFIG_PANIC_HANG               /* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
+#define CONFIG_SYS_L3_SIZE              512 << 10
+#define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif /* CONFIG_RAMBOOT_PBL */
+
+#ifdef CONFIG_SECURE_BOOT
+/*
+ * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
+ * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
+ * (CONFIG_SYS_INIT_L3_VADDR) will be different.
+ */
+#define CONFIG_SYS_INIT_L3_VADDR	0xFFFC0000
+#undef CONFIG_SPL_GD_ADDR
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
+#endif /* CONFIG_SECURE_BOOT */
+
+#define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
+#define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
+
+#define CONFIG_SYS_DCSRBAR              0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
+#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR      (2)
+#define CONFIG_CHIP_SELECTS_PER_CTRL    (4)
+
+#define CONFIG_SYS_DDR_RAW_TIMING
+
+#define CONFIG_SYS_SDRAM_SIZE           8192    /* In MByte, for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#ifdef CONFIG_NOR_FLASH
+#define CONFIG_SYS_FLASH_BASE           0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#endif
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE            0xff800000
+#define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
+
+#define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
+#define CONFIG_SYS_NAND_CSPR            (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+                                        | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+                                        | CSPR_MSEL_NAND    /* MSEL = NAND */ \
+                                        | CSPR_V)
+
+#define CONFIG_SYS_NAND_AMASK           IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR		(CSOR_NAND_ECC_ENC_EN |	/* ECC on encode */ \
+					 CSOR_NAND_ECC_DEC_EN |	/* ECC on decode */ \
+					 CSOR_NAND_ECC_MODE_4 |	/* 4-bit ECC */ \
+					 CSOR_NAND_RAL_3 |	/* RAL = 3Byes */ \
+					 CSOR_NAND_PGS_2K |	/* Page Size = 2K */ \
+					 CSOR_NAND_SPRZ_128 |	/* Spare size = 128 */ \
+					 CSOR_NAND_PB(64) |	/* Pages Per Block = 64 */ \
+					 CSOR_NAND_BCTLD)	/* Buffer control disable */
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
+                                        FTIM0_NAND_TWP(0x18)   | \
+                                        FTIM0_NAND_TWCHT(0x07) | \
+                                        FTIM0_NAND_TWH(0x0a))
+
+#define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
+                                        FTIM1_NAND_TWBE(0x39)  | \
+                                        FTIM1_NAND_TRR(0x0e)   | \
+                                        FTIM1_NAND_TRP(0x18))
+
+#define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
+                                        FTIM2_NAND_TREH(0x0a) | \
+                                        FTIM2_NAND_TWHRE(0x1e))
+
+#define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0xa)
+
+#define CONFIG_SYS_NAND_DDR_LAW         11
+#define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE      1
+/*#define CONFIG_CMD_NAND*/
+
+/* NOR configuation */
+/*#define CONFIG_SYS_NO_FLASH*/
+#define CONFIG_MTD
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH    FLASH_CFI_16BIT
+#define CONFIG_SYS_FLASH_PROTECTION
+/*#define CONFIG_SYS_NOR_BASE		(0xe8000000)
+ #define CONFIG_SYS_NOR_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NOR_BASE)
+ */
+#define CONFIG_SYS_FLASH_BASE           0xe8000000
+#define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_SYS_NOR_CSPR_EXT        (0xf)
+#define CONFIG_SYS_NOR_CSPR            (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+					CSPR_PORT_SIZE_16 | \
+					CSPR_MSEL_NOR | \
+					CSPR_V)
+
+#define CONFIG_SYS_NOR_AMASK           IFC_AMASK(32*1024*1024)
+
+#define CONFIG_SYS_NOR_CSOR		(CSOR_NOR_AVD_TGL_PGM_EN |	/* AVD Toggle Enable during Burst Program */ \
+					 CSOR_NOR_ADM_SHIFT(7) |	/* Address Data Multiplexing Shift */ \
+					 CSOR_NOR_TRHZ_80) |		/* Time for Read Enable High to Output High Impedance */ \
+					 CSOR_NAND_BCTLD		/* Buffer control disable */
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x4) | \
+				FTIM0_NOR_TEADC(0x5) | \
+				FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x4) | \
+				FTIM2_NOR_TCH(0x4) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#endif
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_HWCONFIG
+
+#define CONFIG_SPL_GPIO_SUPPORT
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS       ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+                                            CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+
+#define CONFIG_SYS_INIT_RAM_SIZE            0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET          (CONFIG_SYS_INIT_RAM_SIZE - \
+                                            GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_INIT_SP_OFFSET           CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN              (768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN               (4 * 1024 * 1024)
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX                   1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE         1
+#define CONFIG_SYS_NS16550_CLK              (get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE           {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1             (CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2             (CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3             (CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4             (CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SERIAL_MULTI                 /* Enable both serial ports */
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV        /* determine from environment */
+#endif
+
+/* Use the HUSH parser */
+/*#define CONFIG_SYS_HUSH_PARSER*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+
+/* new uImage format support */
+#if 0
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE  /* enable fit_format_{error,warning}() */
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL      /* Use FSL common I2C driver */
+#define CONFIG_SYS_FSL_I2C_SPEED    400000  /* I2C speed in Hz */
+#define CONFIG_SYS_FSL_I2C2_SPEED   400000
+#define CONFIG_SYS_FSL_I2C3_SPEED   400000
+#define CONFIG_SYS_FSL_I2C4_SPEED   400000
+#define CONFIG_SYS_FSL_I2C_SLAVE    0x7F
+#define CONFIG_SYS_FSL_I2C2_SLAVE   0x7F
+#define CONFIG_SYS_FSL_I2C3_SLAVE   0x7F
+#define CONFIG_SYS_FSL_I2C4_SLAVE   0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET   0x118000
+#define CONFIG_SYS_FSL_I2C2_OFFSET  0x118100
+#define CONFIG_SYS_FSL_I2C3_OFFSET  0x119000
+#define CONFIG_SYS_FSL_I2C4_OFFSET  0x119100
+#if 0
+#define I2C_MUX_PCA_ADDR_PRI	0x77 /* I2C bus multiplexer,primary */
+#define I2C_MUX_PCA_ADDR_SEC1	0x75 /* I2C bus multiplexer,secondary 1 */
+#define I2C_MUX_PCA_ADDR_SEC2	0x76 /* I2C bus multiplexer,secondary 2 */
+#define I2C_MUX_CH_DEFAULT	0x8
+
+#define I2C_MUX_CH_VOL_MONITOR	0xa
+#endif
+
+#define CONFIG_VID_FLS_ENV		"t208xrdb_vdd_mv"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_VID
+#endif
+#define CONFIG_VOL_MONITOR_IR36021_SET
+#define CONFIG_VOL_MONITOR_IR36021_READ
+/* The lowest and highest voltage allowed for T208xRDB */
+#define VDD_MV_MIN			819
+#define VDD_MV_MAX			1212
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+#define CONFIG_PCIE3		/* PCIE controller 3 */
+#define CONFIG_PCIE4		/* PCIE controller 4 */
+#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 4, Base address 203000 */
+#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
+#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
+#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
+#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
+
+#ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
+
+#define CONFIG_E1000
+#define CONFIG_E1000_SPI
+#define CONFIG_CMD_E1000
+
+#define CONFIG_PCI_SCAN_SHOW        /* show pci devices on startup */
+/* #define CONFIG_DOS_PARTITION  */
+#endif  /* CONFIG_PCI */
+
+/*
+ * SATA
+ */
+#define CONFIG_FSL_SATA_V2
+#ifdef CONFIG_FSL_SATA_V2
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+#define CONFIG_SYS_SATA_MAX_DEVICE  2
+#define CONFIG_SATA1
+#define CONFIG_SYS_SATA1            CONFIG_SYS_MPC85xx_SATA1_ADDR
+#define CONFIG_SYS_SATA1_FLAGS      FLAGS_DMA
+#define CONFIG_SATA2
+#define CONFIG_SYS_SATA2            CONFIG_SYS_MPC85xx_SATA2_ADDR
+#define CONFIG_SYS_SATA2_FLAGS      FLAGS_DMA
+#define CONFIG_LBA48
+/* #define CONFIG_DOS_PARTITION */
+#endif
+
+/*#define CONFIG_SPI_FLASH_MTD*/
+
+/*
+ * USB
+ */
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_HAS_FSL_DR_USB
+#endif /* CONFIG_USB_EHCI*/ 
+
+/*
+ * SDHC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+#define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_CMD_MMC
+/* #define CONFIG_GENERIC_MMC */
+#define CONFIG_CMD_EXT2
+/*#define CONFIG_CMD_FAT*/
+/* #define CONFIG_DOS_PARTITION */
+#endif
+
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	18
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_QMAN_NUM_PORTALS	18
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0xE08
+
+#define CONFIG_SYS_DPAA_FMAN
+#define CONFIG_SYS_DPAA_PME
+#define CONFIG_SYS_PMAN
+#define CONFIG_SYS_DPAA_DCE
+/* #define CONFIG_SYS_DPAA_RMAN */
+#define CONFIG_SYS_INTERLAKEN
+
+/*TODO: QE not supported on T2081???
+ #define CONFIG_QE
+ #define CONFIG_U_QE */
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_FMAN_FW_ADDR         (512 * 0x820)
+#elif defined(CONFIG_NAND_FLASH_BOOT)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_FMAN_FW_ADDR		(0x240000)	/* Refer to mtdparts: fman_ucode */
+
+/* #define CONFIG_SYS_QE_FW_IN_NAND This define has been moved out of this file in this u-boot version */
+/* #define CONFIG_SYS_QE_FW_LENGTH		(0x10000) This define has been moved out of this file in this u-boot version */
+#define CONFIG_SYS_QE_FW_ADDR		(0x280000)	/* Refer to mtdparts: qe_ucode */
+
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_FMAN_FW_ADDR		0xe8240000	/* Refer to mtdparts: fman_ucode */
+#define CONFIG_SYS_QE_FW_ADDR  		0xe8280000	/* Refer to mtdparts: qe_ucode */
+/* __stringify(CONFIG_LOADADDR) */
+#endif
+
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
+#define CONFIG_SYS_FDT_PAD      (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+/*#define CONFIG_PHY_MARVELL*/
+#endif
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_RGMII1_PHY_ADDR      0x00
+#define CONFIG_SYS_RGMII2_PHY_ADDR      0x01
+
+#define FM1_10GEC1_PHY_ADDR	0x00  /* Todo implement further and test!! */
+#define FM1_10GEC2_PHY_ADDR	0x01
+
+#define CONFIG_MII          /* MII PHY management */
+#define CONFIG_ETHPRIME     "FM1@DTSEC3"
+/* #define CONFIG_PHY_GIGE     Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO               /* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+/*#define CONFIG_CMD_ERRATA*/
+#define CONFIG_CMD_GREPENV
+/*#define CONFIG_CMD_IRQ*/
+#define CONFIG_CMD_MII /* Todo set instead in Kconfig */
+#define CONFIG_CMD_PING /* Todo set instead in Kconfig */
+/*#define CONFIG_CMD_REGINFO*/
+
+#ifdef CONFIG_PCI
+/*#define CONFIG_CMD_PCI*/
+#endif
+
+/* Hash command with SHA acceleration supported in hardware */
+#ifdef CONFIG_FSL_CAAM
+/*#define CONFIG_CMD_HASH*/
+#define CONFIG_SHA_HW_ACCEL
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP                     /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	1000000		/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "           /* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	32		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ    (64 << 20)  /* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN    (64 << 20)  /* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
+#endif
+
+/*
+ * Dynamic MTD Partition support with mtdparts
+ */
+/*#define CONFIG_CMD_MTDPARTS*/
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_NOR_FLASH
+
+/*#define CONFIG_SYS_NO_FLASH*/
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#define CONFIG_CMD_BLOB
+#endif
+
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+/* #define CONFIG_UBI_SILENCE_MSG */
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#ifdef CONFIG_SPI_FLASH
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_SPANSION
+
+/*#define CONFIG_CMD_SF*/
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SF_DEFAULT_SPEED	10000000
+#define CONFIG_SF_DEFAULT_MODE	0
+#endif
+
+#define MTDIDS_DEFAULT \
+	"nand0=fff800000.flash," \
+	"nor0=fe8000000.nor"
+
+#define MTDPART_DEFAULT_PARTITIONS \
+	"2M@0x0(u-boot)," \
+	"256k(env)," \
+	"256k(fman_ucode)," \
+	"256k(qe_ucode),"
+
+#ifdef CONFIG_NAND_FLASH
+
+#endif
+#ifdef CONFIG_NOR_FLASH
+
+#endif
+#define MTDPARTS_DEFAULT    \
+	"mtdparts=fff800000.flash:" \
+		MTDPART_DEFAULT_PARTITIONS \
+		"0x3fc80000(ubipart_nand)," \
+		"1M@0x3ff00000(bbt)ro;" \
+	"fe8000000.nor:" \
+		MTDPART_DEFAULT_PARTITIONS \
+		"-(ubipart_nor)"
+
+#ifdef CONFIG_NOR_FLASH
+#define NOR_ENV	\
+	"update-uboot-nor-nw=" \
+		"dhcp; tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin.nor;" \
+		"if test $? = \"0\"; then " \
+			"protect off 0xe8000000 0xe81fffff;" \
+			"erase 0xe8000000 0xe81fffff;" \
+			"cp.w ${loadaddr} 0xe8000000 ${filesize};" \
+		"fi\0" \
+	"update-uboot-nor-usb=" \
+		"usb start;" \
+		"fatload usb 0 ${loadaddr} u-boot-with-spl-pbl.bin.nor;" \
+		"if test $? = \"0\"; then " \
+			"protect off 0xe8000000 0xe81fffff;" \
+			"erase 0xe8000000 0xe81fffff;" \
+			"cp.w ${loadaddr} 0xe8000000 ${filesize};" \
+		"fi\0" \
+	\
+	"update-fman-ucode-nor-usb=" \
+		"usb start;" \
+		"fatload usb 0 ${loadaddr} fsl_fman_ucode_t2080_r1.1_106_4_17.bin;" \
+		"if test $? = \"0\"; then " \
+			"protect off 0xe8240000 0xe827ffff;" \
+			"erase 0xe8240000 0xe827ffff;" \
+			"cp.w ${loadaddr} 0xe8240000 ${filesize};" \
+		"fi\0" \
+	"update-qe-ucode-nor-usb=" \
+		"usb start;" \
+		"fatload usb 0 ${loadaddr} iram_Type_A_T2080_r1.0.bin;" \
+		"if test $? = \"0\"; then " \
+			"protect off 0xe8280000 0xe82bffff;" \
+			"erase 0xe8280000 0xe82bffff;" \
+			"cp.w ${loadaddr} 0xe8280000 ${filesize};" \
+		"fi\0" \
+	"update-ubi-rootfs-nor="\
+		"dhcp;" \
+		"ubi part ubipart_nor;" \
+		"if test $? = \"0\"; then " \
+			"tftp ${TFTP_PATH}/ubi_rootfs_image.nor.ubifs;" \
+			"if test $? = \"0\"; then " \
+				"ubi write ${loadaddr} rootfs ${filesize};" \
+			"fi;" \
+		"fi;" \
+		"\0" \
+	\
+	"ubiboot-nor=" \
+		"ubi part ubipart_nor;" \
+		"ubifsmount ubi0:rootfs;" \
+		"ubifsload ${fitaddr} /boot/fitImage.itb;" \
+		"run set_ubiboot_args_nor;" \
+		"bootm ${fitaddr}#conf@1" \
+		"\0" \
+	\
+	"set_ubiboot_args_nor=setenv bootargs ${bootargs} ${mtdparts} ubi.mtd=ubipart_nor ubi.fm_autoconvert=1 root=ubi0:rootfs rw rootfstype=ubifs \0"
+#else
+#define NOR_ENV
+#endif
+
+#ifdef CONFIG_NAND_FLASH
+#define NAND_ENV \
+    "update-uboot-nand-nw=" \
+        "dhcp;" \
+        "tftp ${TFTP_PATH}/u-boot-with-spl-pbl.bin.nand;" \
+        "if test $? = \"0\"; then " \
+            "nand erase.part u-boot;" \
+            "nand write ${loadaddr} 0 ${filesize}; "\
+        "fi\0" \
+    "update-uboot-nand-usb=" \
+        "usb start;" \
+        "fatload usb 0 ${loadaddr} u-boot-with-spl-pbl.bin.nand;" \
+        "nand erase.part u-boot;" \
+        "nand write ${loadaddr} u-boot ${filesize};" \
+        "\0" \
+    \
+    "update-fman-ucode-nand-usb=" \
+        "usb start;" \
+        "fatload usb 0 ${loadaddr} fsl_fman_ucode_t2080_r1.1_106_4_17.bin;" \
+        "nand erase.part fman_ucode;" \
+        "nand write ${loadaddr} fman_ucode ${filesize};" \
+        "\0" \
+    \
+    "update-qe-ucode-nand-usb=" \
+        "usb start;" \
+        "fatload usb 0 ${loadaddr} iram_Type_A_T2080_r1.0.bin;" \
+        "nand erase.part qe_ucode;" \
+        "nand write ${loadaddr} qe_ucode ${filesize};" \
+        "\0" \
+    "update-ubi-rootfs-nand="\
+        "dhcp;" \
+        "ubi part ubipart_nand;" \
+        "if test $? = \"0\"; then " \
+            "tftp ${TFTP_PATH}/ubi_rootfs_image.nand.ubifs;" \
+            "if test $? = \"0\"; then " \
+                "ubi write ${loadaddr} rootfs ${filesize};" \
+            "fi;" \
+        "fi;" \
+    "\0" \
+    \
+    "ubiboot-nand=" \
+        "ubi part ubipart_nand;" \
+        "ubifsmount ubi0:rootfs;" \
+        "ubifsload ${fitaddr} /boot/fitImage.itb;" \
+        "run set_ubiboot_args_nand;" \
+        "bootm ${fitaddr}#conf@1" \
+        "\0" \
+    \
+    "set_ubiboot_args_nand=setenv bootargs ${bootargs} ${mtdparts} ubi.mtd=ubipart_nand ubi.fm_autoconvert=1 root=ubi0:rootfs rw rootfstype=ubifs \0"
+#else
+#define NAND_ENV
+#endif
+
+#ifdef CONFIG_NAND_FLASH_BOOT
+#define BOOTCMD "ubiboot-nand"
+#elif defined(CONFIG_NOR_FLASH_BOOT)
+#define BOOTCMD "ubiboot-nor"
+#else
+#define BOOTCMD ""
+#endif
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+#define CONFIG_BAUDRATE		115200
+
+#define __USB_PHY_TYPE  utmi
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+    "hwconfig=" \
+        "fsl_ddr:bank_intlv=null;"\
+        "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
+        "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
+    \
+    "ethaddr=02:00:00:ba:be:01\0" \
+    "eth1addr=02:00:00:ba:be:02\0" \
+    "eth2addr=02:00:00:ba:be:03\0" \
+    "eth3addr=02:00:00:ba:be:04\0" \
+    "eth4addr=02:00:00:ba:be:05\0" \
+    \
+    "autoload=no\0" \
+    "fitaddr="__stringify(CONFIG_LOADADDR)"\0" \
+    "TFTP_PATH=\0" \
+    \
+    "mtdids=" MTDIDS_DEFAULT "\0" \
+    "mtdparts=" MTDPARTS_DEFAULT "\0" \
+    \
+    NOR_ENV \
+    NAND_ENV \
+    \
+    "setfans=i2c dev 0; i2c mw 0x2e 0x40 1;i2c mw 0x2e 0x7d 0x2;" \
+        "i2c mw 0x2e 0x5c 0xe0;i2c mw 0x2e 0x5d 0xe0;i2c mw 0x2e 0x5e 0xe0;" \
+        "i2c mw 0x2e 0x5f 0xc8;i2c mw 0x2e 0x60 0xc8;i2c mw 0x2e 0x61 0xc8;" \
+        "i2c mw 0x2e 0x30 0x20;i2c mw 0x2e 0x31 0x20;i2c mw 0x2e 0x32 0x20;\0"\
+    \
+    "probe-spi-flash=sf probe 0; if test $? = \"0\"; then " \
+	"setenv mtdids \"${mtdids}\",nor1=fe110000.spi;" \
+	"setenv mtdparts \"${mtdparts};\"fe110000.spi:" MTDPART_DEFAULT_PARTITIONS "-(storage);"\
+	";fi\0" \
+    \
+    "netboot=dhcp; tftp ${fitaddr} ${TFTP_PATH}/fitImage.itb; bootm ${fitaddr}#conf@1\0" \
+    \
+    "bootcmd=run setfans; run "BOOTCMD"\0" \
+    \
+    "bootargs_sata=rootfstype=ext3 root=/dev/sda1\0" \
+    "bootargs=console=ttyS0,115200 rootwait panic=10\0" \
+
+#endif	/* SIMC_T2081_H */