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| author | Chunhe Lan <Chunhe.Lan@freescale.com> | 2014-05-07 02:56:18 (GMT) |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-05-16 21:24:26 (GMT) |
| commit | 1a344456a95b28f28e47f66aa4ec4ac88f703f35 (patch) | |
| tree | c363d7a3940cf3e434445b6f40f8963c5155c2fd | |
| parent | f1a96ec1a9920854c3308a062caca0b339bd1e3b (diff) | |
| download | u-boot-fsl-qoriq-1a344456a95b28f28e47f66aa4ec4ac88f703f35.tar.xz | |
powerpc/85xx: Add T4160RDB board support
T4160RDB shares the same platform as T4240RDB. T4160 is
a low power version of T4240, with the eight e6500 cores,
two DDR3 controllers, and same peripheral bus interfaces.
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
| -rw-r--r-- | boards.cfg | 1 | ||||
| -rw-r--r-- | include/configs/T4240RDB.h | 4 |
2 files changed, 5 insertions, 0 deletions
@@ -983,6 +983,7 @@ Active powerpc mpc85xx - freescale t4qds Active powerpc mpc85xx - freescale t4qds T4240QDS_SECURE_BOOT T4240QDS:PPC_T4240,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com> Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4rdb T4160RDB T4240RDB:PPC_T4160 Chunhe Lan <Chunhe.Lan@freescale.com> Active powerpc mpc85xx - freescale t4rdb T4240RDB T4240RDB:PPC_T4240 Chunhe Lan <Chunhe.Lan@freescale.com> Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de> Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de> diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index b1a8053..183255d 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -678,7 +678,11 @@ unsigned long get_board_ddr_clk(void); * interleaving. It can be cacheline, page, bank, superbank. * See doc/README.fsl-ddr for details. */ +#ifdef CONFIG_PPC_T4240 #define CTRL_INTLV_PREFERED 3way_4KB +#else +#define CTRL_INTLV_PREFERED cacheline +#endif #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:" \ |