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authorBin Meng <bmeng.cn@gmail.com>2017-07-31 02:24:02 (GMT)
committerBin Meng <bmeng.cn@gmail.com>2017-08-01 12:17:02 (GMT)
commit24357dfd2aec4118b9178d8bf639fb8fc02e1859 (patch)
tree662e726937addfe3701c355df3460b903a7c426b
parentb7c6baef2891ce8978cbfddb66e944943473ac21 (diff)
downloadu-boot-fsl-qoriq-24357dfd2aec4118b9178d8bf639fb8fc02e1859.tar.xz
x86: Switch all boards to use DM SCSI
After MMC is converted to DM, convert to use DM SCSI as well for all x86 boards and imply BLK for both MMC and SCSI drivers. CONFIG_SCSI_DEV_LIST is no longer used. Clean them up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Diffstat
-rw-r--r--arch/Kconfig2
-rw-r--r--arch/x86/cpu/baytrail/Kconfig1
-rw-r--r--arch/x86/cpu/broadwell/Kconfig1
-rw-r--r--arch/x86/cpu/coreboot/Kconfig1
-rw-r--r--arch/x86/cpu/ivybridge/Kconfig1
-rw-r--r--arch/x86/cpu/qemu/Kconfig1
-rw-r--r--arch/x86/cpu/queensbay/Kconfig1
-rw-r--r--configs/chromebook_link64_defconfig2
-rw-r--r--configs/chromebook_link_defconfig2
-rw-r--r--configs/chromebox_panther_defconfig2
-rw-r--r--include/configs/bayleybay.h4
-rw-r--r--include/configs/conga-qeval20-qa3-e3845.h4
-rw-r--r--include/configs/cougarcanyon2.h3
-rw-r--r--include/configs/crownbay.h3
-rw-r--r--include/configs/dfi-bt700.h4
-rw-r--r--include/configs/minnowmax.h4
-rw-r--r--include/configs/qemu-x86.h10
-rw-r--r--include/configs/som-6896.h3
-rw-r--r--include/configs/som-db5800-som-6867.h4
-rw-r--r--include/configs/x86-chromebook.h8
20 files changed, 8 insertions, 53 deletions
diff --git a/arch/Kconfig b/arch/Kconfig
index fdcf7cd..e063ee0 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -95,12 +95,14 @@ config X86
select PCI
select TIMER
select X86_TSC_TIMER
+ imply BLK
imply DM_ETH
imply DM_GPIO
imply DM_KEYBOARD
imply DM_MMC
imply DM_RTC
imply DM_SERIAL
+ imply DM_SCSI
imply DM_SPI
imply DM_SPI_FLASH
imply DM_USB
diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig
index 052d77f..9374c12 100644
--- a/arch/x86/cpu/baytrail/Kconfig
+++ b/arch/x86/cpu/baytrail/Kconfig
@@ -11,6 +11,7 @@ config INTEL_BAYTRAIL
imply HAVE_INTEL_ME if !EFI
imply ENABLE_MRC_CACHE
imply ENV_IS_IN_SPI_FLASH
+ imply AHCI_PCI
imply ICH_SPI
imply INTEL_ICH6_GPIO
imply MMC
diff --git a/arch/x86/cpu/broadwell/Kconfig b/arch/x86/cpu/broadwell/Kconfig
index 7e71325..b421f18 100644
--- a/arch/x86/cpu/broadwell/Kconfig
+++ b/arch/x86/cpu/broadwell/Kconfig
@@ -10,6 +10,7 @@ config INTEL_BROADWELL
imply HAVE_INTEL_ME
imply ENABLE_MRC_CACHE
imply ENV_IS_IN_SPI_FLASH
+ imply AHCI_PCI
imply ICH_SPI
imply INTEL_BROADWELL_GPIO
imply SCSI
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index 07d3fb8..d4e0587 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -4,6 +4,7 @@ config SYS_COREBOOT
bool
default y
imply ENV_IS_NOWHERE
+ imply AHCI_PCI
imply E1000
imply ICH_SPI
imply MMC
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index 7bac4c5..00f99d6 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -11,6 +11,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE
imply HAVE_INTEL_ME
imply ENABLE_MRC_CACHE
imply ENV_IS_IN_SPI_FLASH
+ imply AHCI_PCI
imply ICH_SPI
imply INTEL_ICH6_GPIO
imply SCSI
diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig
index b6297f7..fdf5ae3 100644
--- a/arch/x86/cpu/qemu/Kconfig
+++ b/arch/x86/cpu/qemu/Kconfig
@@ -8,6 +8,7 @@ config QEMU
bool
select ARCH_EARLY_INIT_R
imply ENV_IS_NOWHERE
+ imply AHCI_PCI
imply E1000
imply SYS_NS16550
imply USB
diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
index 80b6bc5..d1b04c9 100644
--- a/arch/x86/cpu/queensbay/Kconfig
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -10,6 +10,7 @@ config INTEL_QUEENSBAY
select HAVE_CMC
select ARCH_EARLY_INIT_R
imply ENV_IS_IN_SPI_FLASH
+ imply AHCI_PCI
imply ICH_SPI
imply INTEL_ICH6_GPIO
imply MMC
diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
index 8da05cd..3655a64 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -56,8 +56,6 @@ CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
-CONFIG_DM_SCSI=y
-CONFIG_BLK=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_INTEL=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 69cdc6c..e2bc9f7 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -38,8 +38,6 @@ CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_DM_SCSI=y
-CONFIG_BLK=y
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_INTEL=y
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index f325ba4..34f57ad 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -34,8 +34,6 @@ CONFIG_ISO_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_DM_SCSI=y
-CONFIG_BLK=y
CONFIG_CROS_EC=y
CONFIG_CROS_EC_LPC=y
CONFIG_RTL8169=y
diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h
index 3efdbd2..f9ea907 100644
--- a/include/configs/bayleybay.h
+++ b/include/configs/bayleybay.h
@@ -19,10 +19,6 @@
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-
/* Environment configuration */
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x006ff000
diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h
index b4ea184..0c37407 100644
--- a/include/configs/conga-qeval20-qa3-e3845.h
+++ b/include/configs/conga-qeval20-qa3-e3845.h
@@ -19,10 +19,6 @@
"stdout=serial\0" \
"stderr=serial\0"
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h
index 5f4800b..66e8006 100644
--- a/include/configs/cougarcanyon2.h
+++ b/include/configs/cougarcanyon2.h
@@ -17,9 +17,6 @@
"stdout=serial,vga\0" \
"stderr=serial,vga\0"
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
-
/* Environment configuration */
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0x5ff000
diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h
index 5ec09ba..4181c06 100644
--- a/include/configs/crownbay.h
+++ b/include/configs/crownbay.h
@@ -21,9 +21,6 @@
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
-
/* Environment configuration */
#define CONFIG_ENV_SECT_SIZE 0x1000
#define CONFIG_ENV_OFFSET 0
diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h
index 6748b9c..949a581 100644
--- a/include/configs/dfi-bt700.h
+++ b/include/configs/dfi-bt700.h
@@ -24,10 +24,6 @@
"stdout=serial\0" \
"stderr=serial\0"
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_USB_ETHER_SMSC95XX
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h
index 5b24c2b..5b1660c 100644
--- a/include/configs/minnowmax.h
+++ b/include/configs/minnowmax.h
@@ -22,10 +22,6 @@
"stderr=vidconsole,serial\0" \
"usb_pgood_delay=40\0"
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
index 033b5e2..01072f8 100644
--- a/include/configs/qemu-x86.h
+++ b/include/configs/qemu-x86.h
@@ -23,11 +23,7 @@
* ATA/SATA support for QEMU x86 targets
* - Only legacy IDE controller is supported for QEMU '-M pc' target
* - AHCI controller is supported for QEMU '-M q35' target
- *
- * Default configuraion is to support the QEMU default x86 target
- * Undefine CONFIG_IDE to support q35 target
*/
-#ifdef CONFIG_IDE
#define CONFIG_SYS_IDE_MAXBUS 2
#define CONFIG_SYS_IDE_MAXDEVICE 4
#define CONFIG_SYS_ATA_BASE_ADDR 0
@@ -38,12 +34,6 @@
#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
#define CONFIG_ATAPI
-#undef CONFIG_SCSI_AHCI
-#else
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_AHCI}
-#endif
-
/* SPI is not supported */
#define CONFIG_SPL_FRAMEWORK
diff --git a/include/configs/som-6896.h b/include/configs/som-6896.h
index af51c2a..509f23a 100644
--- a/include/configs/som-6896.h
+++ b/include/configs/som-6896.h
@@ -16,9 +16,6 @@
#define CONFIG_MISC_INIT_R
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI}
-
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h
index 17adf7e..927e1b6 100644
--- a/include/configs/som-db5800-som-6867.h
+++ b/include/configs/som-db5800-som-6867.h
@@ -19,10 +19,6 @@
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0"
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
-
#define VIDEO_IO_OFFSET 0
#define CONFIG_X86EMU_RAW_IO
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h
index 4d02cd4..27ba9ee 100644
--- a/include/configs/x86-chromebook.h
+++ b/include/configs/x86-chromebook.h
@@ -15,14 +15,6 @@
#define CONFIG_X86_REFCODE_ADDR 0xffea0000
#define CONFIG_X86_REFCODE_RUN_ADDR 0
-#define CONFIG_SCSI_DEV_LIST \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}, \
- {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI}
-
#define CONFIG_PCI_MEM_BUS 0xe0000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
generated by cgit v0.10.2 at 2024-06-29 18:32:09 (GMT)