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| author | Roger Quadros <rogerq@ti.com> | 2013-11-11 14:56:43 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-12-04 13:12:09 (GMT) |
| commit | 5afded6a4c49edce971aca8e1a1df5dda7eeed01 (patch) | |
| tree | abf405bebc4bd18471a8ea4e2f8754f1504b3300 | |
| parent | afdc6321316ca5a6bfc7b916328f45ab4720007e (diff) | |
| download | u-boot-fsl-qoriq-5afded6a4c49edce971aca8e1a1df5dda7eeed01.tar.xz | |
ARM: DRA7xx: Add PRCM and Control information for SATA
Adds the necessary PRCM and Control register information for
SATA on DRA7xx.
Signed-off-by: Roger Quadros <rogerq@ti.com>
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/prcm-regs.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 5c60d74..77c428b 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -376,6 +376,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_status = 0x4A002134, + .control_phy_power_sata = 0x4A002374, .control_core_mac_id_0_lo = 0x4A002514, .control_core_mac_id_0_hi = 0x4A002518, .control_core_mac_id_1_lo = 0x4A00251C, @@ -895,9 +896,11 @@ struct prcm_regs const dra7xx_prcm = { .cm_l3init_hsusbhost_clkctrl = 0x4a009340, .cm_l3init_hsusbotg_clkctrl = 0x4a009348, .cm_l3init_hsusbtll_clkctrl = 0x4a009350, + .cm_l3init_sata_clkctrl = 0x4a009388, .cm_gmac_clkstctrl = 0x4a0093c0, .cm_gmac_gmac_clkctrl = 0x4a0093d0, .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, + .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, /* cm2.l4per */ .cm_l4per_clkstctrl = 0x4a009700, |