diff options
| author | Chin Liang See <clsee@altera.com> | 2014-06-10 06:26:52 (GMT) |
|---|---|---|
| committer | Pantelis Antoniou <panto@antoniou-consulting.com> | 2014-08-01 16:45:32 (GMT) |
| commit | 6ace153d130f528b88117b1edcfe017ea1852d67 (patch) | |
| tree | ad1f6527943f089fa6e7f90a7d35fcd78675cbf6 | |
| parent | dae0f5c644c0f76e67306bd49c09d95373b7357a (diff) | |
| download | u-boot-fsl-qoriq-6ace153d130f528b88117b1edcfe017ea1852d67.tar.xz | |
mmc/dw_mmc: Fix clock divider calculation error for bypass mode
To fix the clock divider calculation error when the controller
clock same as the operating frequency. This is known as bypass
mode. In this mode, the divider should be 0.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Mischa Jonker <mjonker@synopsys.com>
| -rw-r--r-- | drivers/mmc/dw_mmc.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index 5bf36a0..0df30bc 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -245,7 +245,10 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) return -EINVAL; } - div = DIV_ROUND_UP(sclk, 2 * freq); + if (sclk == freq) + div = 0; /* bypass mode */ + else + div = DIV_ROUND_UP(sclk, 2 * freq); dwmci_writel(host, DWMCI_CLKENA, 0); dwmci_writel(host, DWMCI_CLKSRC, 0); |