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| author | Andy Fleming <afleming@freescale.com> | 2007-02-24 07:16:45 (GMT) |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2007-04-24 00:58:28 (GMT) |
| commit | 9343dbf85bc03033f2102d8e8543567c2c1ad2d2 (patch) | |
| tree | 94edfc80e63eb36793f6feed2c46339e0cfb9cce | |
| parent | 85e7c7a45e3dd9c7ce3e722352ba60f8df1a7a4b (diff) | |
| download | u-boot-fsl-qoriq-9343dbf85bc03033f2102d8e8543567c2c1ad2d2.tar.xz | |
Tweak DDR ECC error counter
Enable single-bit error counter when memory was cleared by ddr controller.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
| -rw-r--r-- | cpu/mpc85xx/spd_sdram.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index 6da5367..4b3c4eb 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -786,14 +786,17 @@ spd_sdram(void) * Is this an ECC DDR chip? * But don't mess with it if the DDR controller will init mem. */ -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) +#ifdef CONFIG_DDR_ECC if (spd.config == 0x02) { +#ifndef CONFIG_ECC_INIT_VIA_DDRCONTROLLER ddr->err_disable = 0x0000000d; +#endif ddr->err_sbe = 0x00ff0000; } + debug("DDR: err_disable = 0x%08x\n", ddr->err_disable); debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe); -#endif +#endif /* CONFIG_DDR_ECC */ asm("sync;isync;msync"); udelay(500); |