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authorVikas Manocha <vikas.manocha@st.com>2017-02-12 18:25:48 (GMT)
committerTom Rini <trini@konsulko.com>2017-03-17 18:15:14 (GMT)
commitb5be8f5ea8d9b0ffc46f818ce0cb38cd16f99e4d (patch)
tree97556c8a9b47ea996828a6f82be552ecc54fd08e
parent84bfdc17b54198a869ad91341c26eec5f9c96169 (diff)
downloadu-boot-fsl-qoriq-b5be8f5ea8d9b0ffc46f818ce0cb38cd16f99e4d.tar.xz
stm32f7: clk: remove usart1 clock enable from board init
Before clock driver availability it was required to enable usart1 clock for serial init but now with clock driver is taking care of usart1 clock. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
-rw-r--r--board/st/stm32f746-disco/stm32f746-disco.c1
-rw-r--r--drivers/clk/clk_stm32f7.c3
2 files changed, 0 insertions, 4 deletions
diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
index 72212f4..ee1deb5 100644
--- a/board/st/stm32f746-disco/stm32f746-disco.c
+++ b/board/st/stm32f746-disco/stm32f746-disco.c
@@ -380,7 +380,6 @@ int board_early_init_f(void)
int res;
res = uart_setup_gpio();
- clock_setup(USART1_CLOCK_CFG);
if (res)
return res;
diff --git a/drivers/clk/clk_stm32f7.c b/drivers/clk/clk_stm32f7.c
index 4c5388a..0d86395 100644
--- a/drivers/clk/clk_stm32f7.c
+++ b/drivers/clk/clk_stm32f7.c
@@ -228,9 +228,6 @@ static int stm32_clk_enable(struct clk *clk)
void clock_setup(int peripheral)
{
switch (peripheral) {
- case USART1_CLOCK_CFG:
- setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_USART1EN);
- break;
case GPIO_A_CLOCK_CFG:
setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_A_EN);
break;