diff options
| author | Albert ARIBAUD \(3ADEV\) <albert.aribaud@3adev.fr> | 2017-02-01 13:46:00 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-02-08 21:24:25 (GMT) |
| commit | db74cbfc090f05bbfe31ea05ca7e04bd8f364c9f (patch) | |
| tree | db068bbd8b629c10ea6c4a7da30dcf010f9a71bd | |
| parent | e9ced147bced4fb6b9b2563bc177af7c7b680753 (diff) | |
| download | u-boot-fsl-qoriq-db74cbfc090f05bbfe31ea05ca7e04bd8f364c9f.tar.xz | |
pcm052: fix DDR initialization sequence
The sequence erroneously launched the DDR controller
initialization before the pad muxing was done, causing
DRAM size computation to hang.
Configuring the pads first then launching DDR controller
initialization prevents the DRAM hanging.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| -rw-r--r-- | board/phytec/pcm052/pcm052.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/board/phytec/pcm052/pcm052.c b/board/phytec/pcm052/pcm052.c index e75ff4f..54a4e4f 100644 --- a/board/phytec/pcm052/pcm052.c +++ b/board/phytec/pcm052/pcm052.c @@ -258,8 +258,7 @@ int dram_init(void) .wldqsen = 25, }; - ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, - pcm052_phy_settings, 1, 2); + const int row_diff = 2; #elif defined(CONFIG_TARGET_BK4R1) @@ -314,8 +313,7 @@ int dram_init(void) .wldqsen = 25, }; - ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, - pcm052_phy_settings, 1, 1); + const int row_diff = 1; #else /* Unknown PCM052 variant */ @@ -325,6 +323,9 @@ int dram_init(void) imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); + ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, + pcm052_phy_settings, 1, row_diff); + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; |