T2081 pci update for PCI SAS/SATA configuration

11 files changed, 233 insertions, 204 deletions

diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h
index cad341e..8edad88 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -23,7 +23,12 @@
 #define FSL_PROG_IF_AGENT	0x1
 
 #define PCI_LTSSM	0x404   /* PCIe Link Training, Status State Machine */
+
+#if defined (CONFIG_ARCH_T2081) || defined (CONFIG_ARCH_T2080)
+#define  PCI_LTSSM_L0  0x11		/* L0 state */
+#else
 #define  PCI_LTSSM_L0	0x16    /* L0 state */
+#endif
 
 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
 int fsl_is_pci_agent(struct pci_controller *hose);
diff --git a/board/scalys/simc-t10xx/dragonfruit.c b/board/scalys/simc-t10xx/dragonfruit.c
index 80235fe..12accc0 100644
--- a/board/scalys/simc-t10xx/dragonfruit.c
+++ b/board/scalys/simc-t10xx/dragonfruit.c
@@ -8,23 +8,18 @@
 
 #include <common.h>
 #include <asm-generic/gpio.h>
-
 #include "dragonfruit.h"
 
-uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
-uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
-uint32_t regval;
-
 /*
  * SERDER MUX Configuration pins:
  * IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL
  * IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL
  * IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL
  */
-#define MUX_SER0_1_SEL (0x80000000 >> 25)
-#define MUX_SER2_3_SEL (0x80000000 >> 26)
-#define MUX_SER5_6_SEL (0x80000000 >> 27)
-#define SERDES_CLK_OE  (0x80000000 >> 29)
+#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
+#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
+#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
+#define SERDES_CLK_OE  MPC85XX_GPIO_NR(2, 29)
 
 /* 
  * MUX_SER0_1_SEL
@@ -153,46 +148,34 @@ int scalys_carrier_setup_muxing(int serdes_config)
 	
 	printf("-----------------------------------------------------\n");
 	printf("Serdes lane configuration:\n");
-	if ((mux_config & 1) > 0) {
-		regval = in_be32(gpio2_gpdat);
-		regval |= MUX_SER0_1_SEL;
-		out_be32(gpio2_gpdat, regval);
+	if ((mux_config & 1) != 0) {
+		gpio_direction_output(MUX_SER0_1_SEL, 1);
 		printf("A: SFP slot 0 (T2081 only)\n");
-		printf("B: SFP slot 1\n");
+		printf("B: SFP slot 1 (T2081 only)\n");
 	} else {
-		regval = in_be32(gpio2_gpdat);
-		regval &= ~MUX_SER0_1_SEL;
-		out_be32(gpio2_gpdat, regval);
+		gpio_direction_output(MUX_SER0_1_SEL, 0);
 		printf("A: PCIe slot 1 on lane 0\n");
 		printf("B: PCIe slot 1 on lane 1\n");
 	}
 	
-	if ((mux_config & 2) > 0) {
-		regval = in_be32(gpio2_gpdat);
-		regval |= MUX_SER2_3_SEL;
-		out_be32(gpio2_gpdat, regval);
+	if ((mux_config & 2) != 0) {
+		gpio_direction_output(MUX_SER2_3_SEL, 1);
 		printf("C: SFP slot 2\n");
 		printf("D: SFP slot 3\n");
 	} else {
-		regval = in_be32(gpio2_gpdat);
-		regval &= ~MUX_SER2_3_SEL;
-		out_be32(gpio2_gpdat, regval);
+		gpio_direction_output(MUX_SER2_3_SEL, 0);
 		printf("C: PCIe slot 1 on lane 2\n");
 		printf("D: PCIe slot 1 on lane 3\n");
 	}
 	
 	printf("E: PCIe slot 4 on lane 0\n");
 	
-	if ((mux_config & 4) > 0) {
-		regval = in_be32(gpio2_gpdat);
-		regval |= MUX_SER5_6_SEL;
-		out_be32(gpio2_gpdat, regval);
+	if ((mux_config & 4) != 0) {
+		gpio_direction_output(MUX_SER5_6_SEL, 1);
 		printf("F: PCIe slot 2 on lane 0\n");
 		printf("G: PCIe slot 3 on lane 0\n");
 	} else {
-		regval = in_be32(gpio2_gpdat);
-		regval &= ~MUX_SER5_6_SEL;
-		out_be32(gpio2_gpdat, regval);
+		gpio_direction_output(MUX_SER5_6_SEL, 0);
 		printf("F: PCIe slot 4 on lane 1\n");
 		printf("G: PCIe slot 4 on lane 2\n");
 	}
@@ -201,14 +184,7 @@ int scalys_carrier_setup_muxing(int serdes_config)
 	printf("-----------------------------------------------------\n");
 
 	/* Enable serdes clock */
-	regval = in_be32(gpio2_gpdat);
-	regval |= SERDES_CLK_OE;
-	out_be32(gpio2_gpdat, regval);
+	gpio_direction_output(SERDES_CLK_OE, 1);
 	
-	/* Set outputs to output mode */
-	regval = in_be32(gpio2_gpdir);
-	regval |= (MUX_SER0_1_SEL | MUX_SER2_3_SEL | MUX_SER5_6_SEL | SERDES_CLK_OE);
-	out_be32(gpio2_gpdir, regval);
-
 	return ret;
 }
diff --git a/board/scalys/simc-t2081/dragonfruit.c b/board/scalys/simc-t2081/dragonfruit.c
index a2d6653..e3f1641 100644
--- a/board/scalys/simc-t2081/dragonfruit.c
+++ b/board/scalys/simc-t2081/dragonfruit.c
@@ -6,23 +6,19 @@
  */
 
 #include <common.h>
-#include <asm/gpio.h>
+#include <asm-generic/gpio.h>
 #include "dragonfruit.h"
 
-uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
-uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
-uint32_t regval;
-
 /*
  * SERDER MUX Configuration pins:
  * IFC_A25 : GPIO2_25 : SERDES_CLK_ MUX_SER0_1_SEL
  * IFC_A26 : GPIO2_26 : SERDES_CLK_ MUX_SER2_3_SEL
  * IFC_A27 : GPIO2_27 : SERDES_CLK_ MUX_SER5_6_SEL
  */
-#define MUX_SER0_1_SEL (0x80000000 >> 25)
-#define MUX_SER2_3_SEL (0x80000000 >> 26)
-#define MUX_SER5_6_SEL (0x80000000 >> 27)
-#define SERDES_CLK_OE  (0x80000000 >> 29)
+#define MUX_SER0_1_SEL MPC85XX_GPIO_NR(2, 25)
+#define MUX_SER2_3_SEL MPC85XX_GPIO_NR(2, 26)
+#define MUX_SER5_6_SEL MPC85XX_GPIO_NR(2, 27)
+#define SERDES_CLK_OE  MPC85XX_GPIO_NR(2, 29)
 
 /* 
  * MUX_SER0_1_SEL
@@ -57,8 +53,7 @@ uint32_t regval;
 #define SER_5_6_SLOT4	0
 #define SER_5_6_SLOT23	4
 
-
-/*
+/* 
  * SERDES H => Slot 4, lane 3
  */
 
@@ -66,14 +61,17 @@ int scalys_carrier_setup_muxing(int serdes_config)
 {
 	int ret = 0;
 	int mux_config = 0;
+	
+		
+	mdelay(100);
 
-	ret = gpio_request(MUX_SER0_1_SEL, "mux_ser0_1_sel");
+	ret += gpio_request(MUX_SER0_1_SEL, "mux_ser0_1_sel");
+	ret += gpio_request(MUX_SER2_3_SEL, "mux_ser2_3_sel");
+	ret += gpio_request(MUX_SER5_6_SEL, "mux_ser5_6_sel");
+	ret += gpio_request(SERDES_CLK_OE, "serdes_clk_oe");
 	if (ret != 0) {
 		printf("gpio request failed(%i)\n", ret);
 	}
-	gpio_request(MUX_SER2_3_SEL, "mux_ser2_3_sel");
-	gpio_request(MUX_SER5_6_SEL, "mux_ser5_6_sel");
-	gpio_request(SERDES_CLK_OE, "serdes_clk_oe");
 	
 	
 	/* 
@@ -123,46 +121,34 @@ int scalys_carrier_setup_muxing(int serdes_config)
 	
 	printf("-----------------------------------------------------\n");
 	printf("Serdes lane configuration:\n");
-	if ((mux_config & 1) > 0) {
-		regval = in_be32(gpio2_gpdat);
-		regval |= MUX_SER0_1_SEL;
-		out_be32(gpio2_gpdat, regval);
+	if ((mux_config & 1) != 0) {
+		gpio_direction_output(MUX_SER0_1_SEL, 1);
 		printf("A: SFP slot 0 (T2081 only)\n");
-		printf("B: SFP slot 1\n");
+		printf("B: SFP slot 1 (T2081 only)\n");
 	} else {
-		regval = in_be32(gpio2_gpdat);
-		regval &= ~MUX_SER0_1_SEL;
-		out_be32(gpio2_gpdat, regval);
+		gpio_direction_output(MUX_SER0_1_SEL, 0);
 		printf("A: PCIe slot 1 on lane 0\n");
 		printf("B: PCIe slot 1 on lane 1\n");
 	}
 	
-	if ((mux_config & 2) > 0) {
-		regval = in_be32(gpio2_gpdat);
-		regval |= MUX_SER2_3_SEL;
-		out_be32(gpio2_gpdat, regval);
+	if ((mux_config & 2) != 0) {
+		gpio_direction_output(MUX_SER2_3_SEL, 1);
 		printf("C: SFP slot 2\n");
 		printf("D: SFP slot 3\n");
 	} else {
-		regval = in_be32(gpio2_gpdat);
-		regval &= ~MUX_SER2_3_SEL;
-		out_be32(gpio2_gpdat, regval);
+		gpio_direction_output(MUX_SER2_3_SEL, 0);
 		printf("C: PCIe slot 1 on lane 2\n");
 		printf("D: PCIe slot 1 on lane 3\n");
 	}
 	
 	printf("E: PCIe slot 4 on lane 0\n");
 	
-	if ((mux_config & 4) > 0) {
-		regval = in_be32(gpio2_gpdat);
-		regval |= MUX_SER5_6_SEL;
-		out_be32(gpio2_gpdat, regval);
+	if ((mux_config & 4) != 0) {
+		gpio_direction_output(MUX_SER5_6_SEL, 1);
 		printf("F: PCIe slot 2 on lane 0\n");
 		printf("G: PCIe slot 3 on lane 0\n");
 	} else {
-		regval = in_be32(gpio2_gpdat);
-		regval &= ~MUX_SER5_6_SEL;
-		out_be32(gpio2_gpdat, regval);
+		gpio_direction_output(MUX_SER5_6_SEL, 0);
 		printf("F: PCIe slot 4 on lane 1\n");
 		printf("G: PCIe slot 4 on lane 2\n");
 	}
@@ -171,14 +157,9 @@ int scalys_carrier_setup_muxing(int serdes_config)
 	printf("-----------------------------------------------------\n");
 
 	/* Enable serdes clock */
-	regval = in_be32(gpio2_gpdat);
-	regval |= SERDES_CLK_OE;
-	out_be32(gpio2_gpdat, regval);
+	gpio_direction_output(SERDES_CLK_OE, 1);
+	
+	mdelay(100);
 	
-	/* Set outputs to output mode */
-	regval = in_be32(gpio2_gpdir);
-	regval |= (MUX_SER0_1_SEL | MUX_SER2_3_SEL | MUX_SER5_6_SEL | SERDES_CLK_OE);
-	out_be32(gpio2_gpdir, regval);
-
 	return ret;
 }
diff --git a/board/scalys/simc-t2081/eth.c b/board/scalys/simc-t2081/eth.c
index 10c59f8..82703d4 100644
--- a/board/scalys/simc-t2081/eth.c
+++ b/board/scalys/simc-t2081/eth.c
@@ -15,9 +15,13 @@
 #include <fsl_dtsec.h>
 #include <vsc9953.h>
 #include <i2c.h>
+#include <phy.h>
+#include <cortina.h>
 
 #include "../../freescale/common/fman.h"
 
+#define VILLA_EEPROM_LOADER_STATUS 0xc01
+
 uint8_t sfp_phy_config[][2] = {
 	{ 0x1b, 0x90 },
 	{ 0x1b, 0x84 },
@@ -32,18 +36,21 @@ int board_eth_init(bd_t *bis)
 #ifdef CONFIG_FMAN_ENET
 	struct memac_mdio_info dtsec_mdio_info;
 	struct memac_mdio_info tgec_mdio_info;
+	/*struct phy_driver *cortina_10G_phy;*/
 	unsigned int i;
 	uint8_t i2c_data;
 	int ret;
 	int phy_addr = 0;
 	
+	/*uint32_t *gpio1_gpdir = (uint32_t *) 0xffe130000;
+	uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008;*/
 	uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
 	uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
 	uint32_t *gpio4_gpdir = (uint32_t *) 0xffe133000;
 	uint32_t *gpio4_gpdat = (uint32_t *) 0xffe133008;
 	uint32_t regval;
 	
-	/* Try to read a byte from te carrier eeprom te determine if were on the correct carrier */
+	/* Try to read a byte from the carrier eeprom the determine if were on the correct carrier */
 	ret = i2c_read(0x54, 0, 2, &i2c_data, 1 );
 	if (ret != 0) {
 		printf("No dragonfruit carrier detected\n");
@@ -71,27 +78,30 @@ int board_eth_init(bd_t *bis)
 	* Remove reset from Ethernet PHY's 
 	* 
 	* Carrier board v1.x:
-	* IFC_PERR_B : GPIO2_15 : eth1_reset
-	* IFC_CS_N2  : GPIO2_11 : eth2_reset 
+	* IFC_PERR_B : GPIO2_15 : eth1_reset_n
+	* IFC_CS_N2  : GPIO2_11 : eth2_reset_n
 	*
 	* Carrier board v2.x:
-	* IFC_PERR_B : GPIO2_15 : eth1_reset
-	* IFC_CS_N2  : GPIO4_09 : eth2_reset
+	* IFC_PERR_B : GPIO2_15 : eth1_reset_n
+	* N_DMA2_DDONE0_B : GPIO4_09 : eth2_reset_n
 	* 
 	* Note: make sure gpio pins are configured as gpio in RCW! 
 	*/
 
 #if 0 
+
+#define ETH1_RESET_N (0x80000000 >> 15)
+#define ETH2_RESET_N (0x80000000 >> 11)
 	/* TODO: use EEPROM data to chose carrier board version */
 	/* Carrier board v1.x */
 	/* Clear outputs to activate reset */
 	regval = in_be32(gpio2_gpdat);
-	regval &= ~((0x80000000 >> 11 ) | (0x80000000 >> 15));
+	regval &= ~(ETH1_RESET_N | ETH2_RESET_N);
 	out_be32(gpio2_gpdat, regval);
 	
 	/* Set outputs to output mode */
 	regval = in_be32(gpio2_gpdir);
-	regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15));
+	regval |= (ETH1_RESET_N | ETH2_RESET_N);
 	out_be32(gpio2_gpdir, regval);
 	
 	/* Wait for 10 ms to to meet reset timing */
@@ -99,24 +109,27 @@ int board_eth_init(bd_t *bis)
 	
 	/* Set outputs to de-activate reset */
 	regval = in_be32(gpio2_gpdat);
-	regval |= ((0x80000000 >> 11 ) | (0x80000000 >> 15));
+	regval |= (ETH1_RESET_N | ETH2_RESET_N);
 	out_be32(gpio2_gpdat, regval);
 #else
+
+#define ETH1_RESET_N (0x80000000 >> 15)
+#define ETH2_RESET_N (0x80000000 >> 9)
 	/* Carrier board v2.x */
 	/* Clear outputs to activate reset */
 	regval = in_be32(gpio2_gpdat);
-	regval &= ~(0x80000000 >> 15);
+	regval &= ~(ETH1_RESET_N);
 	out_be32(gpio2_gpdat, regval);
 	regval = in_be32(gpio4_gpdat);
-	regval &= ~(0x80000000 >> 9);
+	regval &= ~(ETH2_RESET_N);
 	out_be32(gpio4_gpdat, regval);
 	
 	/* Set outputs to output mode */
 	regval = in_be32(gpio2_gpdir);
-	regval |= (0x80000000 >> 15);
+	regval |= (ETH1_RESET_N);
 	out_be32(gpio2_gpdir, regval);
 	regval = in_be32(gpio4_gpdir);
-	regval |= (0x80000000 >> 9);
+	regval |= (ETH2_RESET_N);
 	out_be32(gpio4_gpdir, regval);
 	
 	/* Wait for 10 ms to to meet reset timing */
@@ -124,10 +137,10 @@ int board_eth_init(bd_t *bis)
 	
 	/* Set outputs to de-activate reset */
 	regval = in_be32(gpio2_gpdat);
-	regval |= (0x80000000 >> 15);
+	regval |= (ETH1_RESET_N);
 	out_be32(gpio2_gpdat, regval);
 	regval = in_be32(gpio4_gpdat);
-	regval |= (0x80000000 >> 9);
+	regval |= (ETH2_RESET_N);
 	out_be32(gpio4_gpdat, regval);
 #endif
 	
@@ -199,13 +212,55 @@ int board_eth_init(bd_t *bis)
 		}
 		fm_info_set_mdio(i, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
 	}
-
+	
+	/* 10G XFI interface initialization (TODO)*/
+#if 0
+	/* Reset phy */
+	/* N_DMA2_DDONE0_B : GPIO1_09 : EDC_RST_N */
+#define EDC_RST_N (0x80000000 >> 9)
+	/* Clear outputs to activate reset */
+	regval = in_be32(gpio1_gpdat);
+	regval &= ~(EDC_RST_N);
+	out_be32(gpio1_gpdat, regval);
+	
+	/* Set outputs to output mode */
+	regval = in_be32(gpio1_gpdir);
+	regval |= (EDC_RST_N);
+	out_be32(gpio1_gpdir, regval);
+	
+	/* Wait for 10 ms to to meet reset timing */
+	mdelay(10);
+	
+	/* Set outputs to de-activate reset */
+	regval = in_be32(gpio1_gpdat);
+	regval |= (EDC_RST_N);
+	out_be32(gpio1_gpdat, regval);
+	
+	/* Wait 10ms to let phy set the load_failed bit */
+	mdelay(10);
+	
+	/* get cs4315 phy */
+	cortina_10G_phy = phy_find_by_mask(tgec_mdio_info, 0xfffffff0, PHY_INTERFACE_MODE_XGMII);
+	
+	/* Check load_failed == 1 (else skip initialization) */
+	mii_data = miiphy_read("FM_TGEC_MDIO",0,VILLA_EEPROM_LOADER_STATUS);
+	
+	if ((mii_data & 0x02) != 0) {
+		/* TODO: upload microcode */
+		cortina_10G_phy->config();
+	}
+	
+	/* TODO: insert additional configuration */
+	
+	/* Start phy */
+	cortina_10G_phy->startup();
+#endif
 	
 	for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 		switch (fm_info_get_enet_if(i)) {
 		case PHY_INTERFACE_MODE_XGMII:
-			fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
-			fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
+			fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
+			fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
 			break;
 		case PHY_INTERFACE_MODE_NONE:
 			fm_info_set_phy_address(i, 0);
diff --git a/board/scalys/simc-t2081/pci.c b/board/scalys/simc-t2081/pci.c
index 9a02f90..f3473f8 100644
--- a/board/scalys/simc-t2081/pci.c
+++ b/board/scalys/simc-t2081/pci.c
@@ -14,30 +14,49 @@
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <asm/fsl_serdes.h>
+#include <asm-generic/gpio.h>
+#include "dragonfruit.h"
+
+#define SLOT1_REFCLK_OE_N MPC85XX_GPIO_NR(1, 9)
+#define SLOT2_REFCLK_OE_N MPC85XX_GPIO_NR(1, 10)
+#define SLOT3_REFCLK_OE_N MPC85XX_GPIO_NR(1, 11)
+#define SLOT4_REFCLK_OE_N MPC85XX_GPIO_NR(1, 12)
+	
+#define SLOT1_PRSNT2_N MPC85XX_GPIO_NR(1, 23)
+#define SLOT2_PRSNT2_N MPC85XX_GPIO_NR(1, 24)
+#define SLOT3_PRSNT2_N MPC85XX_GPIO_NR(1, 25)
+#define SLOT4_PRSNT2_N MPC85XX_GPIO_NR(1, 30)
+	
+#define PEX_REFCLK_SEL MPC85XX_GPIO_NR(2, 14)
+#define PEX_PERST_N MPC85XX_GPIO_NR(2, 13)
+
 
 void pci_init_board(void)
 {
+	int ret = 0;
+	int serdes_config;
+	ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	
-	uint32_t *gpio1_gpdir = (uint32_t *) 0xffe130000;
-	uint32_t *gpio1_gpdat = (uint32_t *) 0xffe130008;
-	uint32_t *gpio2_gpdir = (uint32_t *) 0xffe131000;
-	uint32_t *gpio2_gpdat = (uint32_t *) 0xffe131008;
-	uint32_t regval;	
-	
-	/*debug("%s\n", __FUNCTION__);*/
+	/* SERDES configuration is determined boot time through the RCW config.
+	 * It is located in the fourth RCW word (bit 128-135 of the RCW). */
+	serdes_config = ( in_be32(&gur->rcwsr[4]) >> 24);
+	scalys_carrier_setup_muxing(serdes_config);
 	
-	/*TODO, when present pins are available on the board, use them to enable only active slots*/
+	ret += gpio_request(SLOT4_REFCLK_OE_N, "c19");
+	ret += gpio_request(PEX_REFCLK_SEL, "c14");
+	ret += gpio_request(PEX_PERST_N, "c15");
+	if (ret != 0)
+		printf("A gpio request failed(%i)\n", ret);
 	
 #if 0
 	/* Dragonfruit Carrier board 1.x */
 
-
 	/* 
 	 * IRQ[0-3] : PCIe present detect signals
-	 * IRQ[0] : SLOT1_PRSNT2_N : XXX
-	 * IRQ[1] : SLOT2_PRSNT2_N : XXX
-	 * IRQ[2] : SLOT3_PRSNT2_N : XXX
-	 * IRQ[3] : SLOT4_PRSNT2_N : XXX
+	 * IRQ[3] : GPIO1_23 : SLOT1_PRSNT2_N
+	 * IRQ[4] : GPIO1_24 : SLOT2_PRSNT2_N
+	 * IRQ[5] : GPIO1_25 : SLOT3_PRSNT2_N
+	 * IRQ[10] : GPIO1_30 : SLOT4_PRSNT2_N
 	 * 
 	 * Clock enable of PCIe Slots 1-4: IFC_CS_N4-IFC_CS_N7 
 	 * IFC_CS_N4 : GPIO1_IO09 : PCIe SLOT1_REFCLK_OE_N
@@ -71,44 +90,18 @@ void pci_init_board(void)
 	 */
 	
 	/* Set output to 0 to enable reference clocks */
-	regval = in_be32(gpio1_gpdat);
-	regval &= ~( 0x80000000 >> 12 );
-	out_be32(gpio1_gpdat, regval);
-	
-	/* Set Enable outputs */
-	regval = in_be32(gpio1_gpdir);
-	regval |= ( 0x80000000 >> 12 );
-	out_be32(gpio1_gpdir, regval);
+	gpio_direction_output(SLOT4_REFCLK_OE_N, 0);
 	
 	/* Set PEX_REFCLK_SEL to 0 to select CLK0  */
-
-	/* Set IFC_PAR1 to output mode */
-	regval = in_be32(gpio2_gpdir);
-	regval |= ( 0x80000000 >> 14 );
-	out_be32(gpio2_gpdir, regval);
-
-	/* Set output to 0 to select clock source 0 */
-	regval = in_be32(gpio2_gpdat);
-	regval &= ~( 0x80000000 >> 14 );
-	out_be32(gpio2_gpdat, regval);
-
-#endif
+	gpio_direction_output(PEX_REFCLK_SEL, 0);
+#endif 
 	
 	/*
 	 * IFC_PAR0 : GPIO2_13 : PEX_PERST_N
 	 */
 
 	/* Remove reset from PCIe devices */
-
-	/* Set IFC_PAR0 to output mode */
-	regval = in_be32(gpio2_gpdir);
-	regval |= ( 0x80000000 >> 13 );
-	out_be32(gpio2_gpdir, regval);
-
-	/* Set output to 1 to clear reset */
-	regval = in_be32(gpio2_gpdat);
-	regval |= ( 0x80000000 >> 13 );
-	out_be32(gpio2_gpdat, regval);
+	gpio_direction_output(PEX_PERST_N, 1);
 
 	/* Wait for 100 ms to allow the PCIe device to become ready */
 	mdelay(100);
diff --git a/board/scalys/simc-t2081/simc-t2081.c b/board/scalys/simc-t2081/simc-t2081.c
index f07a36f..0569d88 100644
--- a/board/scalys/simc-t2081/simc-t2081.c
+++ b/board/scalys/simc-t2081/simc-t2081.c
@@ -23,7 +23,6 @@
 #include <asm/gpio.h>
 #include <fsl_esdhc.h>
 #include <dm.h>
-#include "dragonfruit.h"
 #include <board_configuration_data.h>
 
 
@@ -38,8 +37,6 @@ int checkboard(void)
 int misc_init_r(void)
 {
 	const void* bcd_dtc_blob;
-	int serdes_config;
-	ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	int ret;
 	
 	debug("t2081: misc_init_r\n");
@@ -56,11 +53,6 @@ int misc_init_r(void)
 	gpio_direction_output(MODULE_LED_RED, 0);
 	gpio_direction_output(MODULE_LED_GREEN, 1);
 	
-	/* SERDES configuration is determined boot time through the RCW config.
-	 * It is located in the fourth RCW word (bit 128-135 of the RCW). */
-	serdes_config = ( in_be32(&gur->rcwsr[4]) >> 24);
-	scalys_carrier_setup_muxing(serdes_config);
-	
 	bcd_dtc_blob = get_boardinfo_eeprom();
 	if (bcd_dtc_blob != NULL) {
 		/* Board Configuration Data is intact, ready for parsing */
diff --git a/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg b/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
index 88dc8ab..afef4e0 100644
--- a/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
+++ b/board/scalys/simc-t2081/simc-t2081_nand_rcw.cfg
@@ -23,7 +23,13 @@ AA55AA55 010E0100
 # 00000314 80000009 00000000 00000004
 
 ## PCI SATA + Virtualization demo 
+# 0c06000e 12000000 00000000 40000000
+# aa000002 40004000 e8105000 41000000
+# 00000000 cafebabe 00000000 00030ffc
+# 00000314 80000009 00000000 00000004
+
+## SERDES PLL2 disabled
 0c06000e 12000000 00000000 40000000
-aa000002 40004000 e8105000 41000000
+aa000002 00404000 e8105000 41000000
 00000000 cafebabe 00000000 00030ffc
 00000314 80000009 00000000 00000004
diff --git a/board/scalys/simc-t2081/tlb.c b/board/scalys/simc-t2081/tlb.c
index ddaa10e..b16b682 100644
--- a/board/scalys/simc-t2081/tlb.c
+++ b/board/scalys/simc-t2081/tlb.c
@@ -134,11 +134,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 19, BOOKE_PAGESZ_1G, 1),
+		      0, 17, BOOKE_PAGESZ_1G, 1),
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 20, BOOKE_PAGESZ_1G, 1)
+		      0, 18, BOOKE_PAGESZ_1G, 1)
 #endif
 
 };
diff --git a/configs/T2_simc-t2081_nand_defconfig b/configs/T2_simc-t2081_nand_defconfig
index 8012171..91fcd05 100644
--- a/configs/T2_simc-t2081_nand_defconfig
+++ b/configs/T2_simc-t2081_nand_defconfig
@@ -23,6 +23,8 @@ CONFIG_CMD_MMC=y
 
 CONFIG_PHYLIB=y
 CONFIG_PHY_MARVELL=y
+#CONFIG_PHYLIB_10G=y
+#CONFIG_PHY_CORTINA=y
 
 CONFIG_USB=y
 CONFIG_USB_EHCI=y
@@ -45,3 +47,9 @@ CONFIG_MPC85XX_GPIO=y
 
 CONFIG_SYS_MALLOC_F=n
 
+CONFIG_PCI=y
+CONFIG_PCI_SCAN_SHOW=y
+CONFIG_CONFIG_PCI_PNP=y
+
+CONFIG_CMD_PCI=y
+
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index af20cf0..1139d83 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -361,7 +361,11 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 	debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
 
 	/* setup PCSRBAR/PEXCSRBAR */
+#if defined (CONFIG_ARCH_T2081) || defined (CONFIG_ARCH_T2080) /* T208x has writable bits at [3..0] that shouldn't be accessed here (right?) */
+	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xfffffff0);
+#else
 	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
+#endif
 	pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
 	pcicsrbar_sz = ~pcicsrbar_sz + 1;
 
@@ -443,7 +447,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 #define PEX_CSR0_LTSSM_SHIFT	2
 			ltssm = (in_be32(&pci->pex_csr0)
 				& PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
-			enabled = (ltssm == 0x11) ? 1 : 0;
+			enabled = (ltssm == PCI_LTSSM_L0) ? 1 : 0;
 #ifdef CONFIG_FSL_PCIE_RESET
 			int i;
 			/* assert PCIe reset */
@@ -454,10 +458,17 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 			clrbits_be32(&pci->pdb_stat, 0x08000000);
 			asm("sync;isync");
 			for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
-				pci_hose_read_config_word(hose, dev, PCI_LTSSM,
-							  &ltssm);
+				ltssm = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
 				udelay(1000);
+				/*debug("....PCIe link error. LTSSM=0x%02x.\n", ltssm);*/
 			}
+			enabled = ltssm >= PCI_LTSSM_L0;
+			
+			/* we need to re-write the bar0 since a reset will
+			 * clear it
+			 */
+			pci_hose_write_config_dword(hose, dev,
+					PCI_BASE_ADDRESS_0, pcicsrbar);
 #endif
 		} else {
 		/* pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm); */
diff --git a/include/configs/simc-t2081.h b/include/configs/simc-t2081.h
index 90a84ef..7a9d1c5 100644
--- a/include/configs/simc-t2081.h
+++ b/include/configs/simc-t2081.h
@@ -16,6 +16,23 @@
 
 #include <generated/autoconf.h>
 
+/* High Level Configuration Options */
+#define CONFIG_SYS_BOOK3E_HV	/* Category E.HV supported */
+#define CONFIG_MP		/* support multiple processors */
+
+#ifdef CONFIG_PHYS_64BIT
+/*#define CONFIG_ADDR_MAP 1*/
+#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_FSL_CPC	/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC	CONFIG_SYS_NUM_DDR_CTLRS
+#define CONFIG_ENV_OVERWRITE
+
+/* Errata */
+#define CONFIG_SYS_FSL_ERRATUM_A007815
+#define CONFIG_SYS_FSL_ERRATUM_A007907
+
 #define CONFIG_MTD_UBI_WL_THRESHOLD	4096
 #define CONFIG_MTD_UBI_BEB_LIMIT	20
 
@@ -442,19 +459,20 @@
 #define VDD_MV_MIN			819
 #define VDD_MV_MAX			1212
 
-
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-/* #define CONFIG_PCI */		/* Enable PCI/PCIE */
-#define CONFIG_PCIE1		/* PCIE controler 1 */
-#define CONFIG_PCIE2		/* PCIE controler 2 */
-#define CONFIG_PCIE3		/* PCIE controler 3 */
-#define CONFIG_PCIE4		/* PCIE controler 4 */
+#ifndef CONFIG_PCI
+#define CONFIG_PCI
+#endif
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE2		/* PCIE controller 2 */
+#define CONFIG_PCIE3		/* PCIE controller 3 */
+#define CONFIG_PCIE4		/* PCIE controller 4 */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+/* controller 1 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
@@ -464,7 +482,7 @@
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
 
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
+/* controller 2 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
@@ -474,7 +492,7 @@
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
 
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
+/* controller 3 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc30000000ull
@@ -484,8 +502,8 @@
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
 
-/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
+/* controller 4 */
+#define CONFIG_SYS_PCIE4_MEM_VIRT   0xc0000000
 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc40000000ull
 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
@@ -496,32 +514,10 @@
 
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata LSZ ADD */
+/*#define CONFIG_FSL_PCIE_RESET*/	   /* need PCIe reset errata (TODO: really needed? (disabled for pci sas demo)) */
 #define CONFIG_NET_MULTI
 #define CONFIG_E1000
-/*#define CONFIG_PCI_PNP*/		/* do pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-/* #define CONFIG_DOS_PARTITION */
-#endif
-
-#if 0 /* T2081 has no SATA */
-/*
- * SATA
- */
-#define CONFIG_FSL_SATA_V2
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_LIBATA
-#define CONFIG_FSL_SATA
-#define CONFIG_SYS_SATA_MAX_DEVICE  2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1            CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS      FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2            CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS      FLAGS_DMA
-#define CONFIG_LBA48
-/* #define CONFIG_DOS_PARTITION */
-#endif
 #endif
 
 /*#define CONFIG_SPI_FLASH_MTD*/
@@ -587,10 +583,6 @@
 /* #define CONFIG_SYS_DPAA_RMAN */
 #define CONFIG_SYS_INTERLAKEN
 
-/*TODO: QE not supported on T2081
- #define CONFIG_QE
- #define CONFIG_U_QE */
-
 /* Default address of microcode for the Linux Fman driver */
 /* TODO: move FMAN/QE ucode to boot source */
 
@@ -605,17 +597,26 @@
 #define CONFIG_SYS_QE_FW_ADDR			(512 * 0x920)*/
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR		(0x240000)	/* Refer to mtdparts: fman_ucode */
-#define CONFIG_SYS_QE_FW_ADDR		(0x280000)	/* Refer to mtdparts: qe_ucode */
+/*#define CONFIG_SYS_QE_FW_ADDR		(0x280000)*/	/* Refer to mtdparts: qe_ucode */
+/*#define CONFIG_SYS_CORTINA_FW_IN_NAND
+#define CONFIG_CORTINA_FW_ADDR		(0x2a0000)
+#define CONFIG_CORTINA_FW_LENGTH	0x28000*/
 
 #elif defined(CONFIG_NAND_FLASH_BOOT)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR		(0x240000)	/* Refer to mtdparts: fman_ucode */
-#define CONFIG_SYS_QE_FW_ADDR		(0x280000)	/* Refer to mtdparts: qe_ucode */
+/*#define CONFIG_SYS_QE_FW_ADDR		(0x280000)*/	/* Refer to mtdparts: qe_ucode */
+/*#define CONFIG_SYS_CORTINA_FW_IN_NAND
+#define CONFIG_CORTINA_FW_ADDR		(0x2a0000)
+#define CONFIG_CORTINA_FW_LENGTH	0x28000*/
 
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 #define CONFIG_SYS_FMAN_FW_ADDR		0xe8240000	/* Refer to mtdparts: fman_ucode */
-#define CONFIG_SYS_QE_FW_ADDR  		0xe8280000	/* Refer to mtdparts: qe_ucode */
+/*#define CONFIG_SYS_QE_FW_ADDR  		0xe8280000*/	/* Refer to mtdparts: qe_ucode */
+/* TODO: #define CONFIG_SYS_CORTINA_FW_IN_NOR
+#define CONFIG_CORTINA_FW_ADDR		0xe82a0000
+#define CONFIG_CORTINA_FW_LENGTH */
 /* __stringify(CONFIG_LOADADDR) */
 #endif
 
@@ -632,8 +633,8 @@
 #define CONFIG_SYS_RGMII1_PHY_ADDR      0x00
 #define CONFIG_SYS_RGMII2_PHY_ADDR      0x01
 
-#define FM1_10GEC1_PHY_ADDR	0x00
-#define FM1_10GEC2_PHY_ADDR	0x01
+#define CORTINA_PHY_ADDR1	0x00
+#define CORTINA_PHY_ADDR2	0x01
 
 #define CONFIG_MII          /* MII PHY management */
 #define CONFIG_ETHPRIME     "FM1@DTSEC3"
@@ -738,6 +739,7 @@
 	"2M@0x0(u-boot)," \
 	"256k(env)," \
 	"256k(fman_ucode),"
+	/*"256k(cs_ucode),"*/
 
 #ifdef CONFIG_NAND_FLASH
 
@@ -900,7 +902,7 @@
     "setfans=i2c dev 0; i2c mw 0x2e 0x40 1;i2c mw 0x2e 0x7d 0x2;" \
         "i2c mw 0x2e 0x5c 0xe0;i2c mw 0x2e 0x5d 0xe0;i2c mw 0x2e 0x5e 0xe0;" \
         "i2c mw 0x2e 0x5f 0xc8;i2c mw 0x2e 0x60 0xc8;i2c mw 0x2e 0x61 0xc8;" \
-        "i2c mw 0x2e 0x30 0x20;i2c mw 0x2e 0x31 0x20;i2c mw 0x2e 0x32 0x20;\0"\
+        "i2c mw 0x2e 0x30 0x40;i2c mw 0x2e 0x31 0x40;i2c mw 0x2e 0x32 0x40;\0"\
     \
     "probe-spi-flash=sf probe 0; if test $? = \"0\"; then " \
 	"setenv mtdids \"${mtdids}\",nor1=fe110000.spi;" \
@@ -911,7 +913,7 @@
     \
     "bootcmd=run setfans; run "BOOTCMD"\0" \
     \
-    "bootargs_sata=rootfstype=ext4 root=/dev/sda1 rw\0" \
-    "bootargs=console=ttyS0,115200 rootwait panic=10\0" \
+    "bootargs_sata=rootfstype=ext2 root=/dev/sda1 rw\0" \
+    "bootargs=console=ttyS0,115200 rootwait panic=10 pci=realloc\0" \
 
 #endif	/* SIMC_T2081_H */