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| author | Bin Meng <bmeng.cn@gmail.com> | 2015-11-26 01:46:07 (GMT) |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2015-12-09 09:44:52 (GMT) |
| commit | efe2d80cca4822ce6c435993e01467eeee8babfb (patch) | |
| tree | 99c6eda9521d220bb1a5e434a2a21e0c6d3a957a | |
| parent | 9bf76c21e0248d06ad7e804b1a95d6cd0bc5f14f (diff) | |
| download | u-boot-fsl-qoriq-efe2d80cca4822ce6c435993e01467eeee8babfb.tar.xz | |
x86: Clean up ivybridge/chrome Kconfig options
There are some options which are never used, and also some options
which are selected by others but have never been a Kconfg option.
Clean these up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
| -rw-r--r-- | arch/x86/cpu/ivybridge/Kconfig | 30 | ||||
| -rw-r--r-- | board/google/chromebook_link/Kconfig | 1 | ||||
| -rw-r--r-- | board/google/chromebox_panther/Kconfig | 1 | ||||
| -rw-r--r-- | include/configs/x86-chromebook.h | 1 |
4 files changed, 0 insertions, 33 deletions
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index d20c038..0970382 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -8,18 +8,9 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE bool select CACHE_MRC_BIN - select CPU_INTEL_MODEL_306AX if NORTHBRIDGE_INTEL_IVYBRIDGE -config VGA_BIOS_ID - string - default "8086,0166" - -config EXTERNAL_MRC_BLOB - bool - default n - config CACHE_MRC_SIZE_KB int default 512 @@ -50,24 +41,9 @@ config DCACHE_RAM_MRC_VAR_SIZE memory reference code. This should be set to 16KB (0x4000 hex) so that MRC has enough space to run. -config MRC_FILE - string "Intel System Agent path and filename" - depends on HAVE_MRC - default "systemagent-ivybridge.bin" - help - The path and filename of the file to use as System Agent - binary. - config CPU_SPECIFIC_OPTIONS def_bool y select SMM_TSEG - select ARCH_BOOTBLOCK_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SSE2 - select UDELAY_LAPIC - select CPU_MICROCODE_IN_CBFS - select TSC_SYNC_MFENCE select HAVE_INTEL_ME select X86_RAMTEST @@ -99,12 +75,6 @@ config CPU_INTEL_SOCKET_RPGA989 if CPU_INTEL_SOCKET_RPGA989 -config SOCKET_SPECIFIC_OPTIONS # dummy - def_bool y - select MMX - select SSE - select CACHE_AS_RAM - config CACHE_MRC_BIN bool default n diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index d3644a9..3843517 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SOUTHBRIDGE_INTEL_C216 select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_8192 diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig index d56d903..88afff3 100644 --- a/board/google/chromebox_panther/Kconfig +++ b/board/google/chromebox_panther/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select X86_RESET_VECTOR select CPU_INTEL_SOCKET_RPGA989 select NORTHBRIDGE_INTEL_IVYBRIDGE - select SOUTHBRIDGE_INTEL_C216 select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_8192 diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 9fb1a7a..c575dab 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -14,7 +14,6 @@ #define CONFIG_MISC_INIT_R #define CONFIG_X86_MRC_ADDR 0xfffa0000 -#define CONFIG_CACHE_MRC_SIZE_KB 512 #define CONFIG_SCSI_DEV_LIST \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ |