x86: baytrail: Configure FSP UPD from device tree

Allow for configuration of FSP UPD from the device tree which will
override any settings which the FSP was built with itself.

Modify the MinnowMax and BayleyBay boards to transfer sensible UPD
settings from the Intel FSPv4 Gold release to the respective dts files,
with the condition that the memory-down parameters for MinnowMax are
also used.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Removed fsp,mrc-debug-msg and fsp,enable-xhci for minnowmax, bayleybay
Fixed lines >80col
Signed-off-by: Simon Glass <sjg@chromium.org>

6 files changed, 388 insertions, 30 deletions

diff --git a/arch/x86/cpu/baytrail/fsp_configs.c b/arch/x86/cpu/baytrail/fsp_configs.c
index 86b6926..a72d615 100644
--- a/arch/x86/cpu/baytrail/fsp_configs.c
+++ b/arch/x86/cpu/baytrail/fsp_configs.c
@@ -1,14 +1,18 @@
 /*
  * Copyright (C) 2013, Intel Corporation
  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2015, Kodak Alaris, Inc
  *
  * SPDX-License-Identifier:	Intel
  */
 
 #include <common.h>
+#include <fdtdec.h>
 #include <asm/arch/fsp/azalia.h>
 #include <asm/fsp/fsp_support.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* ALC262 Verb Table - 10EC0262 */
 static const uint32_t verb_table_data13[] = {
 	/* Pin Complex (NID 0x11) */
@@ -116,41 +120,139 @@ const struct pch_azalia_config azalia_config = {
 	.reset_wait_timer_us = 300
 };
 
+/**
+ * Override the FSP's UPD.
+ * If the device tree does not specify an integer setting, use the default
+ * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file.
+ */
 void update_fsp_upd(struct upd_region *fsp_upd)
 {
 	struct memory_down_data *mem;
+	const void *blob = gd->fdt_blob;
+	int node;
 
-	/*
-	 * Configure everything here to avoid the poor hard-pressed user
-	 * needing to run Intel's binary configuration tool. It may also allow
-	 * us to support the 1GB single core variant easily.
-	 *
-	 * TODO(sjg@chromium.org): Move to device tree
-	 */
-	fsp_upd->mrc_init_tseg_size = 8;
-	fsp_upd->mrc_init_mmio_size = 0x800;
-	fsp_upd->emmc_boot_mode = 0xff;
-	fsp_upd->enable_sdio = 1;
-	fsp_upd->enable_sdcard = 1;
-	fsp_upd->enable_hsuart0 = 1;
 	fsp_upd->azalia_config_ptr = (uint32_t)&azalia_config;
-	fsp_upd->enable_i2_c0 = 0;
-	fsp_upd->enable_i2_c2 = 0;
-	fsp_upd->enable_i2_c3 = 0;
-	fsp_upd->enable_i2_c4 = 0;
-	fsp_upd->enable_xhci = 0;
-	fsp_upd->igd_render_standby = 1;
+
+	node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP);
+	if (node < 0) {
+		debug("%s: Cannot find FSP node\n", __func__);
+		return;
+	}
+
+	fsp_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node,
+						     "fsp,mrc-init-tseg-size",
+						     0);
+	fsp_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node,
+						     "fsp,mrc-init-mmio-size",
+						     0x800);
+	fsp_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
+						     "fsp,mrc-init-spd-addr1",
+						     0xa0);
+	fsp_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node,
+						     "fsp,mrc-init-spd-addr2",
+						     0xa2);
+	fsp_upd->emmc_boot_mode = fdtdec_get_int(blob, node,
+						 "fsp,emmc-boot-mode", 2);
+	fsp_upd->enable_sdio = fdtdec_get_bool(blob, node, "fsp,enable-sdio");
+	fsp_upd->enable_sdcard = fdtdec_get_bool(blob, node,
+						 "fsp,enable-sdcard");
+	fsp_upd->enable_hsuart0 = fdtdec_get_bool(blob, node,
+						  "fsp,enable-hsuart0");
+	fsp_upd->enable_hsuart1 = fdtdec_get_bool(blob, node,
+						  "fsp,enable-hsuart1");
+	fsp_upd->enable_spi = fdtdec_get_bool(blob, node, "fsp,enable-spi");
+	fsp_upd->enable_sata = fdtdec_get_bool(blob, node, "fsp,enable-sata");
+	fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode", 1);
+	fsp_upd->enable_azalia = fdtdec_get_bool(blob, node,
+						 "fsp,enable-azalia");
+	fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci");
+	fsp_upd->enable_lpe = fdtdec_get_bool(blob, node, "fsp,enable-lpe");
+	fsp_upd->lpss_sio_enable_pci_mode = fdtdec_get_bool(blob, node,
+			"fsp,lpss-sio-enable-pci-mode");
+	fsp_upd->enable_dma0 = fdtdec_get_bool(blob, node, "fsp,enable-dma0");
+	fsp_upd->enable_dma1 = fdtdec_get_bool(blob, node, "fsp,enable-dma1");
+	fsp_upd->enable_i2_c0 = fdtdec_get_bool(blob, node, "fsp,enable-i2c0");
+	fsp_upd->enable_i2_c1 = fdtdec_get_bool(blob, node, "fsp,enable-i2c1");
+	fsp_upd->enable_i2_c2 = fdtdec_get_bool(blob, node, "fsp,enable-i2c2");
+	fsp_upd->enable_i2_c3 = fdtdec_get_bool(blob, node, "fsp,enable-i2c3");
+	fsp_upd->enable_i2_c4 = fdtdec_get_bool(blob, node, "fsp,enable-i2c4");
+	fsp_upd->enable_i2_c5 = fdtdec_get_bool(blob, node, "fsp,enable-i2c5");
+	fsp_upd->enable_i2_c6 = fdtdec_get_bool(blob, node, "fsp,enable-i2c6");
+	fsp_upd->enable_pwm0 = fdtdec_get_bool(blob, node, "fsp,enable-pwm0");
+	fsp_upd->enable_pwm1 = fdtdec_get_bool(blob, node, "fsp,enable-pwm1");
+	fsp_upd->enable_hsi = fdtdec_get_bool(blob, node, "fsp,enable-hsi");
+	fsp_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node,
+			"fsp,igd-dvmt50-pre-alloc", 2);
+	fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size",
+						2);
+	fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", 2);
+	fsp_upd->serial_debug_port_address = fdtdec_get_int(blob, node,
+			"fsp,serial-debug-port-address", 0x3f8);
+	fsp_upd->serial_debug_port_type = fdtdec_get_int(blob, node,
+			"fsp,serial-debug-port-type", 1);
+	fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node,
+						 "fsp,mrc-debug-msg");
+	fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable");
+	fsp_upd->scc_enable_pci_mode = fdtdec_get_bool(blob, node,
+			"fsp,scc-enable-pci-mode");
+	fsp_upd->igd_render_standby = fdtdec_get_bool(blob, node,
+						      "fsp,igd-render-standby");
+	fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node,
+						  "fsp,txe-uma-enable");
+	fsp_upd->os_selection = fdtdec_get_int(blob, node, "fsp,os-selection",
+					       4);
+	fsp_upd->emmc45_ddr50_enabled = fdtdec_get_bool(blob, node,
+			"fsp,emmc45-ddr50-enabled");
+	fsp_upd->emmc45_hs200_enabled = fdtdec_get_bool(blob, node,
+			"fsp,emmc45-hs200-enabled");
+	fsp_upd->emmc45_retune_timer_value = fdtdec_get_int(blob, node,
+			"fsp,emmc45-retune-timer-value", 8);
+	fsp_upd->enable_igd = fdtdec_get_bool(blob, node, "fsp,enable-igd");
 
 	mem = &fsp_upd->memory_params;
-	mem->enable_memory_down = 1;
-	mem->dram_speed = 1;
-	mem->dimm_width = 1;
-	mem->dimm_density = 2;
-	mem->dimm_tcl = 0xb;
-	mem->dimm_trpt_rcd = 0xb;
-	mem->dimm_twr = 0xc;
-	mem->dimm_twtr = 6;
-	mem->dimm_trrd = 6;
-	mem->dimm_trtp = 6;
-	mem->dimm_tfaw = 0x14;
+	mem->enable_memory_down = fdtdec_get_bool(blob, node,
+						  "fsp,enable-memory-down");
+	if (mem->enable_memory_down) {
+		node = fdtdec_next_compatible(blob, node,
+					      COMPAT_INTEL_BAYTRAIL_FSP_MDP);
+		if (node < 0) {
+			debug("%s: Cannot find FSP memory-down-params node\n",
+			      __func__);
+		} else {
+			mem->dram_speed = fdtdec_get_int(blob, node,
+							 "fsp,dram-speed",
+							 0x02);
+			mem->dram_type = fdtdec_get_int(blob, node,
+							"fsp,dram-type", 0x01);
+			mem->dimm_0_enable = fdtdec_get_bool(blob, node,
+					"fsp,dimm-0-enable");
+			mem->dimm_1_enable = fdtdec_get_bool(blob, node,
+					"fsp,dimm-1-enable");
+			mem->dimm_width = fdtdec_get_int(blob, node,
+							 "fsp,dimm-width",
+							 0x00);
+			mem->dimm_density = fdtdec_get_int(blob, node,
+							   "fsp,dimm-density",
+							   0x01);
+			mem->dimm_bus_width = fdtdec_get_int(blob, node,
+					"fsp,dimm-bus-width", 0x03);
+			mem->dimm_sides = fdtdec_get_int(blob, node,
+							 "fsp,dimm-sides",
+							 0x00);
+			mem->dimm_tcl = fdtdec_get_int(blob, node,
+						       "fsp,dimm-tcl", 0x09);
+			mem->dimm_trpt_rcd = fdtdec_get_int(blob, node,
+					"fsp,dimm-trpt-rcd", 0x09);
+			mem->dimm_twr = fdtdec_get_int(blob, node,
+						       "fsp,dimm-twr", 0x0A);
+			mem->dimm_twtr = fdtdec_get_int(blob, node,
+							"fsp,dimm-twtr", 0x05);
+			mem->dimm_trrd = fdtdec_get_int(blob, node,
+							"fsp,dimm-trrd", 0x04);
+			mem->dimm_trtp = fdtdec_get_int(blob, node,
+							"fsp,dimm-trtp", 0x05);
+			mem->dimm_tfaw = fdtdec_get_int(blob, node,
+							"fsp,dimm-tfaw", 0x14);
+		}
+	}
 }
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 9f8fa70..8f0e192 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -188,6 +188,44 @@
 		};
 	};
 
+	fsp {
+		compatible = "intel,baytrail-fsp";
+		fsp,mrc-init-tseg-size = <0>;
+		fsp,mrc-init-mmio-size = <0x800>;
+		fsp,mrc-init-spd-addr1 = <0xa0>;
+		fsp,mrc-init-spd-addr2 = <0xa2>;
+		fsp,emmc-boot-mode = <2>;
+		fsp,enable-sdio;
+		fsp,enable-sdcard;
+		fsp,enable-hsuart1;
+		fsp,enable-spi;
+		fsp,enable-sata;
+		fsp,sata-mode = <1>;
+		fsp,enable-lpe;
+		fsp,lpss-sio-enable-pci-mode;
+		fsp,enable-dma0;
+		fsp,enable-dma1;
+		fsp,enable-i2c0;
+		fsp,enable-i2c1;
+		fsp,enable-i2c2;
+		fsp,enable-i2c3;
+		fsp,enable-i2c4;
+		fsp,enable-i2c5;
+		fsp,enable-i2c6;
+		fsp,enable-pwm0;
+		fsp,enable-pwm1;
+		fsp,igd-dvmt50-pre-alloc = <2>;
+		fsp,aperture-size = <2>;
+		fsp,gtt-size = <2>;
+		fsp,serial-debug-port-address = <0x3f8>;
+		fsp,serial-debug-port-type = <1>;
+		fsp,scc-enable-pci-mode;
+		fsp,os-selection = <4>;
+		fsp,emmc45-ddr50-enabled;
+		fsp,emmc45-retune-timer-value = <8>;
+		fsp,enable-igd;
+	};
+
 	microcode {
 		update@0 {
 #include "microcode/m0230671117.dtsi"
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index 9527233..d0c0fe6 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -122,6 +122,62 @@
 			0x01000000 0x0 0x2000 0x2000 0 0xe000>;
 	};
 
+	fsp {
+		compatible = "intel,baytrail-fsp";
+		fsp,mrc-init-tseg-size = <0>;
+		fsp,mrc-init-mmio-size = <0x800>;
+		fsp,mrc-init-spd-addr1 = <0xa0>;
+		fsp,mrc-init-spd-addr2 = <0xa2>;
+		fsp,emmc-boot-mode = <2>;
+		fsp,enable-sdio;
+		fsp,enable-sdcard;
+		fsp,enable-hsuart1;
+		fsp,enable-spi;
+		fsp,enable-sata;
+		fsp,sata-mode = <1>;
+		fsp,enable-lpe;
+		fsp,lpss-sio-enable-pci-mode;
+		fsp,enable-dma0;
+		fsp,enable-dma1;
+		fsp,enable-i2c0;
+		fsp,enable-i2c1;
+		fsp,enable-i2c2;
+		fsp,enable-i2c3;
+		fsp,enable-i2c4;
+		fsp,enable-i2c5;
+		fsp,enable-i2c6;
+		fsp,enable-pwm0;
+		fsp,enable-pwm1;
+		fsp,igd-dvmt50-pre-alloc = <2>;
+		fsp,aperture-size = <2>;
+		fsp,gtt-size = <2>;
+		fsp,serial-debug-port-address = <0x3f8>;
+		fsp,serial-debug-port-type = <1>;
+		fsp,scc-enable-pci-mode;
+		fsp,os-selection = <4>;
+		fsp,emmc45-ddr50-enabled;
+		fsp,emmc45-retune-timer-value = <8>;
+		fsp,enable-igd;
+		fsp,enable-memory-down;
+		fsp,memory-down-params {
+			compatible = "intel,baytrail-fsp-mdp";
+			fsp,dram-speed = <1>;
+			fsp,dram-type = <1>;
+			fsp,dimm-0-enable;
+			fsp,dimm-width = <1>;
+			fsp,dimm-density = <2>;
+			fsp,dimm-bus-width = <3>;
+			fsp,dimm-sides = <0>;
+			fsp,dimm-tcl = <0xb>;
+			fsp,dimm-trpt-rcd = <0xb>;
+			fsp,dimm-twr = <0xc>;
+			fsp,dimm-twtr = <6>;
+			fsp,dimm-trrd = <6>;
+			fsp,dimm-trtp = <6>;
+			fsp,dimm-tfaw = <0x14>;
+		};
+	};
+
 	spi {
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt
new file mode 100644
index 0000000..b44b5b5
--- /dev/null
+++ b/doc/device-tree-bindings/misc/intel,baytrail-fsp.txt
@@ -0,0 +1,158 @@
+Intel Bay Trail FSP UPD Binding
+===============================
+
+The device tree node which describes the overriding of the Intel Bay Trail FSP
+UPD data for configuring the SoC.
+
+All properties can be found within the `upd-region` struct in
+arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h, under the same names, and in
+Intel's FSP Binary Configuration Tool for Bay Trail.  This list of properties is
+matched up to Intel's E3800 FSPv4 release.
+
+# Boolean properties:
+
+- fsp,enable-sdio
+- fsp,enable-sdcard
+- fsp,enable-hsuart0
+- fsp,enable-hsuart1
+- fsp,enable-spi
+- fsp,enable-sata
+- fsp,enable-azalia
+- fsp,enable-xhci
+- fsp,enable-lpe
+- fsp,lpss-sio-enable-pci-mode
+- fsp,enable-dma0
+- fsp,enable-dma1
+- fsp,enable-i2-c0
+- fsp,enable-i2-c1
+- fsp,enable-i2-c2
+- fsp,enable-i2-c3
+- fsp,enable-i2-c4
+- fsp,enable-i2-c5
+- fsp,enable-i2-c6
+- fsp,enable-pwm0
+- fsp,enable-pwm1
+- fsp,enable-hsi
+- fsp,mrc-debug-msg
+- fsp,isp-enable
+- fsp,scc-enable-pci-mode
+- fsp,igd-render-standby
+- fsp,txe-uma-enable
+- fsp,emmc45-ddr50-enabled
+- fsp,emmc45-hs200-enabled
+- fsp,enable-igd
+- fsp,enable-memory-down
+
+If you set "fsp,enable-memory-down" you are strongly encouraged to provide an
+"fsp,memory-down-params{};" to specify how your memory is configured.  If you do
+not set "fsp,enable-memory-down", then the DIMM SPD information will be
+discovered by the FSP and used to setup main memory.
+
+
+# Integer properties:
+
+- fsp,mrc-init-tseg-size
+- fsp,mrc-init-mmio-size
+- fsp,mrc-init-spd-addr1
+- fsp,mrc-init-spd-addr2
+- fsp,emmc-boot-mode
+- fsp,sata-mode
+- fsp,igd-dvmt50-pre-alloc
+- fsp,aperture-size
+- fsp,gtt-size
+- fsp,serial-debug-port-address
+- fsp,serial-debug-port-type
+- fsp,os-selection
+- fsp,emmc45-retune-timer-value
+
+- fsp,memory-down-params {
+
+	# Boolean properties:
+
+	- fsp,dimm-0-enable
+	- fsp,dimm-1-enable
+
+	# Integer properties:
+
+	- fsp,dram-speed
+	- fsp,dram-type
+	- fsp,dimm-width
+	- fsp,dimm-density
+	- fsp,dimm-bus-width
+	- fsp,dimm-sides
+	- fsp,dimm-tcl
+	- fsp,dimm-trpt-rcd
+	- fsp,dimm-twr
+	- fsp,dimm-twtr
+	- fsp,dimm-trrd
+	- fsp,dimm-trtp
+	- fsp,dimm-tfaw
+};
+
+
+Example (from MinnowMax Dual Core):
+-----------------------------------
+
+/ {
+	...
+
+	fsp {
+		compatible = "intel,baytrail-fsp";
+		fsp,mrc-init-tseg-size = <0>;
+		fsp,mrc-init-mmio-size = <0x800>;
+		fsp,mrc-init-spd-addr1 = <0xa0>;
+		fsp,mrc-init-spd-addr2 = <0xa2>;
+		fsp,emmc-boot-mode = <2>;
+		fsp,enable-sdio;
+		fsp,enable-sdcard;
+		fsp,enable-hsuart1;
+		fsp,enable-spi;
+		fsp,enable-sata;
+		fsp,sata-mode = <1>;
+		fsp,enable-xhci;
+		fsp,enable-lpe;
+		fsp,lpss-sio-enable-pci-mode;
+		fsp,enable-dma0;
+		fsp,enable-dma1;
+		fsp,enable-i2c0;
+		fsp,enable-i2c1;
+		fsp,enable-i2c2;
+		fsp,enable-i2c3;
+		fsp,enable-i2c4;
+		fsp,enable-i2c5;
+		fsp,enable-i2c6;
+		fsp,enable-pwm0;
+		fsp,enable-pwm1;
+		fsp,igd-dvmt50-pre-alloc = <2>;
+		fsp,aperture-size = <2>;
+		fsp,gtt-size = <2>;
+		fsp,serial-debug-port-address = <0x3f8>;
+		fsp,serial-debug-port-type = <1>;
+		fsp,mrc-debug-msg;
+		fsp,scc-enable-pci-mode;
+		fsp,os-selection = <4>;
+		fsp,emmc45-ddr50-enabled;
+		fsp,emmc45-retune-timer-value = <8>;
+		fsp,enable-igd;
+		fsp,enable-memory-down;
+		fsp,memory-down-params {
+			compatible = "intel,baytrail-fsp-mdp";
+			fsp,dram-speed = <1>;
+			fsp,dram-type = <1>;
+			fsp,dimm-0-enable;
+			fsp,dimm-width = <1>;
+			fsp,dimm-density = <2>;
+			fsp,dimm-bus-width = <3>;
+			fsp,dimm-sides = <0>;
+			fsp,dimm-tcl = <0xb>;
+			fsp,dimm-trpt-rcd = <0xb>;
+			fsp,dimm-twr = <0xc>;
+			fsp,dimm-twtr = <6>;
+			fsp,dimm-trrd = <6>;
+			fsp,dimm-trtp = <6>;
+			fsp,dimm-tfaw = <0x14>;
+		};
+	};
+
+	...
+};
diff --git a/include/fdtdec.h b/include/fdtdec.h
index eac679e..62acbd0 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -182,6 +182,8 @@ enum fdt_compat_id {
 	COMPAT_INTEL_PCH,		/* Intel PCH */
 	COMPAT_INTEL_IRQ_ROUTER,	/* Intel Interrupt Router */
 	COMPAT_ALTERA_SOCFPGA_DWMAC,	/* SoCFPGA Ethernet controller */
+	COMPAT_INTEL_BAYTRAIL_FSP,	/* Intel Bay Trail FSP */
+	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-down params */
 
 	COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index b201787..cdfc844 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -76,6 +76,8 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"),
 	COMPAT(COMPAT_INTEL_IRQ_ROUTER, "intel,irq-router"),
 	COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),
+	COMPAT(COMPAT_INTEL_BAYTRAIL_FSP, "intel,baytrail-fsp"),
+	COMPAT(COMPAT_INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)