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| author | Tom Rini <trini@ti.com> | 2013-08-13 13:14:02 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-08-13 13:14:02 (GMT) |
| commit | b98d934128bcd98106e764d2f492ac79c38ae53d (patch) | |
| tree | 5e078614fccb51f34fa8f7aa8d92c4f5f518b686 /README | |
| parent | 67cafc0861477bf19a587508ed13f4538c7a281e (diff) | |
| parent | 3aab0cd852d7c9565c2559a7983cbb73852bac28 (diff) | |
| download | u-boot-fsl-qoriq-b98d934128bcd98106e764d2f492ac79c38ae53d.tar.xz | |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'README')
| -rw-r--r-- | README | 12 |
1 files changed, 12 insertions, 0 deletions
@@ -406,13 +406,25 @@ The following options need to be configured: This is the value to write into CCSR offset 0x18600 according to the A004510 workaround. + CONFIG_SYS_FSL_DSP_DDR_ADDR + This value denotes start offset of DDR memory which is + connected exclusively to the DSP cores. + CONFIG_SYS_FSL_DSP_M2_RAM_ADDR This value denotes start offset of M2 memory which is directly connected to the DSP core. + CONFIG_SYS_FSL_DSP_M3_RAM_ADDR + This value denotes start offset of M3 memory which is directly + connected to the DSP core. + CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT This value denotes start offset of DSP CCSR space. + CONFIG_SYS_FSL_DDR_EMU + Specify emulator support for DDR. Some DDR features such as + deskew training are not available. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN |