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| author | Evert Pap <evert.pap@sintecs.nl> | 2016-09-14 11:10:56 (GMT) |
|---|---|---|
| committer | Evert Pap <evert.pap@sintecs.nl> | 2016-09-14 11:10:56 (GMT) |
| commit | 67e39eed5d590a9d29e2cb747b5eaa79a0f11a69 (patch) | |
| tree | 40422948d7909f8306f4425adca0d838ba81976b /arch/arm/cpu/arm11 | |
| parent | 6d249763300432a786ee03cdbb09dd3b065c5189 (diff) | |
| parent | ab01ef5fa617444fd95543ee04ea53ccda273269 (diff) | |
| download | u-boot-fsl-qoriq-67e39eed5d590a9d29e2cb747b5eaa79a0f11a69.tar.xz | |
Merge branch 'master' into scalys
Diffstat (limited to 'arch/arm/cpu/arm11')
| -rw-r--r-- | arch/arm/cpu/arm11/cpu.c | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c index 1e4c214..7244c2e 100644 --- a/arch/arm/cpu/arm11/cpu.c +++ b/arch/arm/cpu/arm11/cpu.c @@ -69,23 +69,6 @@ void flush_dcache_all(void) asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); } -static int check_cache_range(unsigned long start, unsigned long stop) -{ - int ok = 1; - - if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) - ok = 0; - - if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) - ok = 0; - - if (!ok) - debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", - start, stop); - - return ok; -} - void invalidate_dcache_range(unsigned long start, unsigned long stop) { if (!check_cache_range(start, stop)) |