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| author | Tim Harvey <tharvey@gateworks.com> | 2015-05-18 14:07:02 (GMT) |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2015-05-19 13:22:53 (GMT) |
| commit | 3625fd64ef929af4d158027aa5beee703f1294fc (patch) | |
| tree | 4f1ef23b3f45b8d187ac93f926b49432a875da73 /arch/arm/cpu/armv7/mx6 | |
| parent | 28420e780ab5b1bf4bd76ed04313b86ffc4ea17e (diff) | |
| download | u-boot-fsl-qoriq-3625fd64ef929af4d158027aa5beee703f1294fc.tar.xz | |
arm: mx6: ddr: set fast-exit on DDR3 if pd_fast_exit specified
Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support
to the MMDC however enabling it on the DDR3 got missed. Make sure we enable
it on the DDR3 as well.
Gateworks uses Micron memory as well as Winbond in MX6. We have found in
testing that we need to enable fast-exit for Winbond stability. Gateworks
boards are currently the only boards using the MX6 SPL and enabling
fast-exit mode.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/ddr.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 5d5bd0f..86c8354 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -521,7 +521,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, /* MR0 */ val = ((tcl - 1) << 4) | /* CAS */ (1 << 8) | /* DLL Reset */ - ((twr - 3) << 9); /* Write Recovery */ + ((twr - 3) << 9) | /* Write Recovery */ + (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */ debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs)); mmdc0->mdscr = MR(val, 0, 3, cs); /* ZQ calibration */ |