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| author | Tom Rini <trini@konsulko.com> | 2016-11-08 02:34:54 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-11-21 19:07:29 (GMT) |
| commit | 983e37007da506e8145f9b3a9e1dce5c11116fb0 (patch) | |
| tree | c1d5449e1c56e17f22bb4f75b6f11336abca41a4 /arch/arm/cpu/armv7/omap-common | |
| parent | 272686eb7576c02df4616bcf893fde993e7ba57e (diff) | |
| download | u-boot-fsl-qoriq-983e37007da506e8145f9b3a9e1dce5c11116fb0.tar.xz | |
arm: Introduce arch/arm/mach-omap2 for OMAP2 derivative platforms
This moves what was in arch/arm/cpu/armv7/omap-common in to
arch/arm/mach-omap2 and moves
arch/arm/cpu/armv7/{am33xx,omap3,omap4,omap5} in to arch/arm/mach-omap2
as subdirectories. All refernces to the former locations are updated to
the current locations. For the logic to decide what our outputs are,
consolidate the tests into a single config.mk rather than including 4.
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu/armv7/omap-common')
20 files changed, 0 insertions, 4528 deletions
diff --git a/arch/arm/cpu/armv7/omap-common/Kconfig b/arch/arm/cpu/armv7/omap-common/Kconfig deleted file mode 100644 index 4daccd9..0000000 --- a/arch/arm/cpu/armv7/omap-common/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -config TI_SECURE_DEVICE - bool "HS Device Type Support" - depends on OMAP54XX || AM43XX || AM33XX - help - If a high secure (HS) device type is being used, this config - must be set. This option impacts various aspects of the - build system (to create signed boot images that can be - authenticated) and the code. See the doc/README.ti-secure - file for further details. - -source "arch/arm/cpu/armv7/omap3/Kconfig" - -source "arch/arm/cpu/armv7/omap4/Kconfig" - -source "arch/arm/cpu/armv7/omap5/Kconfig" - -source "arch/arm/cpu/armv7/am33xx/Kconfig" diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile deleted file mode 100644 index 3172bae..0000000 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ /dev/null @@ -1,40 +0,0 @@ -# -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := reset.o -ifeq ($(CONFIG_TIMER),) -obj-y += timer.o -else -ifdef CONFIG_SPL_BUILD -obj-y += timer.o -endif -endif -obj-y += utils.o - -ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) -obj-y += hwinit-common.o -obj-y += clocks-common.o -obj-y += emif-common.o -obj-y += vc.o -obj-y += abb.o -endif - -ifneq ($(CONFIG_OMAP54XX),) -obj-y += pipe3-phy.o -obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o -endif - -ifeq ($(CONFIG_SYS_DCACHE_OFF),) -obj-y += omap-cache.o -endif - -obj-y += boot-common.o -obj-y += lowlevel_init.o - -obj-y += mem-common.o - -obj-$(CONFIG_TI_SECURE_DEVICE) += sec-common.o diff --git a/arch/arm/cpu/armv7/omap-common/abb.c b/arch/arm/cpu/armv7/omap-common/abb.c deleted file mode 100644 index a0add66..0000000 --- a/arch/arm/cpu/armv7/omap-common/abb.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Adaptive Body Bias programming sequence for OMAP family - * - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - * - * Andrii Tseglytskyi <andrii.tseglytskyi@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/omap_common.h> -#include <asm/arch/clock.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> - -__weak s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) -{ - return -1; -} - -static void abb_setup_timings(u32 setup) -{ - u32 sys_rate, sr2_cnt, clk_cycles; - - /* - * SR2_WTCNT_VALUE is the settling time for the ABB ldo after a - * transition and must be programmed with the correct time at boot. - * The value programmed into the register is the number of SYS_CLK - * clock cycles that match a given wall time profiled for the ldo. - * This value depends on: - * settling time of ldo in micro-seconds (varies per OMAP family), - * of clock cycles per SYS_CLK period (varies per OMAP family), - * the SYS_CLK frequency in MHz (varies per board) - * The formula is: - * - * ldo settling time (in micro-seconds) - * SR2_WTCNT_VALUE = ------------------------------------------ - * (# system clock cycles) * (sys_clk period) - * - * Put another way: - * - * SR2_WTCNT_VALUE = settling time / (# SYS_CLK cycles / SYS_CLK rate)) - * - * To avoid dividing by zero multiply both "# clock cycles" and - * "settling time" by 10 such that the final result is the one we want. - */ - - /* calculate SR2_WTCNT_VALUE */ - sys_rate = DIV_ROUND_CLOSEST(V_OSCK, 1000000); - clk_cycles = DIV_ROUND_CLOSEST(OMAP_ABB_CLOCK_CYCLES * 10, sys_rate); - sr2_cnt = DIV_ROUND_CLOSEST(OMAP_ABB_SETTLING_TIME * 10, clk_cycles); - - setbits_le32(setup, - sr2_cnt << (ffs(OMAP_ABB_SETUP_SR2_WTCNT_VALUE_MASK) - 1)); -} - -void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control, - u32 txdone, u32 txdone_mask, u32 opp) -{ - u32 abb_type_mask, opp_sel_mask; - - /* sanity check */ - if (!setup || !control || !txdone) - return; - - /* setup ABB only in case of Fast or Slow OPP */ - switch (opp) { - case OMAP_ABB_FAST_OPP: - abb_type_mask = OMAP_ABB_SETUP_ACTIVE_FBB_SEL_MASK; - opp_sel_mask = OMAP_ABB_CONTROL_FAST_OPP_SEL_MASK; - break; - case OMAP_ABB_SLOW_OPP: - abb_type_mask = OMAP_ABB_SETUP_ACTIVE_RBB_SEL_MASK; - opp_sel_mask = OMAP_ABB_CONTROL_SLOW_OPP_SEL_MASK; - break; - default: - return; - } - - /* - * For some OMAP silicons additional setup for LDOVBB register is - * required. This is determined by data retrieved from corresponding - * OPP EFUSE register. Data, which is retrieved from EFUSE - is - * ABB enable/disable flag and VSET value, which must be copied - * to LDOVBB register. If function call fails - return quietly, - * it means no ABB is required for such silicon. - * - * For silicons, which don't require LDOVBB setup "fuse" and - * "ldovbb" offsets are not defined. ABB will be initialized in - * the common way for them. - */ - if (fuse && ldovbb) { - if (abb_setup_ldovbb(fuse, ldovbb)) - return; - } - - /* clear ABB registers */ - writel(0, setup); - writel(0, control); - - /* configure timings, based on oscillator value */ - abb_setup_timings(setup); - - /* clear pending interrupts before setup */ - setbits_le32(txdone, txdone_mask); - - /* select ABB type */ - setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK); - - /* initiate ABB ldo change */ - setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK); - - /* wait until transition complete */ - if (!wait_on_value(txdone_mask, txdone_mask, (void *)txdone, LDELAY)) - puts("Error: ABB txdone is not set\n"); - - /* clear ABB tranxdone */ - setbits_le32(txdone, txdone_mask); -} diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c deleted file mode 100644 index 385310b..0000000 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ /dev/null @@ -1,252 +0,0 @@ -/* - * boot-common.c - * - * Common bootmode functions for omap based boards - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ahci.h> -#include <spl.h> -#include <asm/omap_common.h> -#include <asm/arch/omap.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/sys_proto.h> -#include <watchdog.h> -#include <scsi.h> -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -__weak u32 omap_sys_boot_device(void) -{ - return BOOT_DEVICE_NONE; -} - -void save_omap_boot_params(void) -{ - u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); - struct omap_boot_parameters *omap_boot_params; - int sys_boot_device = 0; - u32 boot_device; - u32 boot_mode; - - if ((boot_params < NON_SECURE_SRAM_START) || - (boot_params > NON_SECURE_SRAM_END)) - return; - - omap_boot_params = (struct omap_boot_parameters *)boot_params; - - boot_device = omap_boot_params->boot_device; - boot_mode = MMCSD_MODE_UNDEFINED; - - /* Boot device */ - -#ifdef BOOT_DEVICE_NAND_I2C - /* - * Re-map NAND&I2C boot-device to the "normal" NAND boot-device. - * Otherwise the SPL boot IF can't handle this device correctly. - * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens - * Draco leads to this boot-device passed to SPL from the BootROM. - */ - if (boot_device == BOOT_DEVICE_NAND_I2C) - boot_device = BOOT_DEVICE_NAND; -#endif -#ifdef BOOT_DEVICE_QSPI_4 - /* - * We get different values for QSPI_1 and QSPI_4 being used, but - * don't actually care about this difference. Rather than - * mangle the later code, if we're coming in as QSPI_4 just - * change to the QSPI_1 value. - */ - if (boot_device == BOOT_DEVICE_QSPI_4) - boot_device = BOOT_DEVICE_SPI; -#endif - /* - * When booting from peripheral booting, the boot device is not usable - * as-is (unless there is support for it), so the boot device is instead - * figured out using the SYS_BOOT pins. - */ - switch (boot_device) { -#if defined(BOOT_DEVICE_UART) && !defined(CONFIG_SPL_YMODEM_SUPPORT) - case BOOT_DEVICE_UART: - sys_boot_device = 1; - break; -#endif -#if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_SUPPORT) - case BOOT_DEVICE_USB: - sys_boot_device = 1; - break; -#endif -#if defined(BOOT_DEVICE_USBETH) && !defined(CONFIG_SPL_USBETH_SUPPORT) - case BOOT_DEVICE_USBETH: - sys_boot_device = 1; - break; -#endif -#if defined(BOOT_DEVICE_CPGMAC) && !defined(CONFIG_SPL_ETH_SUPPORT) - case BOOT_DEVICE_CPGMAC: - sys_boot_device = 1; - break; -#endif -#if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU_SUPPORT) - case BOOT_DEVICE_DFU: - sys_boot_device = 1; - break; -#endif - } - - if (sys_boot_device) { - boot_device = omap_sys_boot_device(); - - /* MMC raw mode will fallback to FS mode. */ - if ((boot_device >= MMC_BOOT_DEVICES_START) && - (boot_device <= MMC_BOOT_DEVICES_END)) - boot_mode = MMCSD_MODE_RAW; - } - - gd->arch.omap_boot_device = boot_device; - - /* Boot mode */ - -#ifdef CONFIG_OMAP34XX - if ((boot_device >= MMC_BOOT_DEVICES_START) && - (boot_device <= MMC_BOOT_DEVICES_END)) { - switch (boot_device) { - case BOOT_DEVICE_MMC1: - boot_mode = MMCSD_MODE_FS; - break; - case BOOT_DEVICE_MMC2: - boot_mode = MMCSD_MODE_RAW; - break; - } - } -#else - /* - * If the boot device was dynamically changed and doesn't match what - * the bootrom initially booted, we cannot use the boot device - * descriptor to figure out the boot mode. - */ - if ((boot_device == omap_boot_params->boot_device) && - (boot_device >= MMC_BOOT_DEVICES_START) && - (boot_device <= MMC_BOOT_DEVICES_END)) { - boot_params = omap_boot_params->boot_device_descriptor; - if ((boot_params < NON_SECURE_SRAM_START) || - (boot_params > NON_SECURE_SRAM_END)) - return; - - boot_params = *((u32 *)(boot_params + DEVICE_DATA_OFFSET)); - if ((boot_params < NON_SECURE_SRAM_START) || - (boot_params > NON_SECURE_SRAM_END)) - return; - - boot_mode = *((u32 *)(boot_params + BOOT_MODE_OFFSET)); - - if (boot_mode != MMCSD_MODE_FS && - boot_mode != MMCSD_MODE_RAW) -#ifdef CONFIG_SUPPORT_EMMC_BOOT - boot_mode = MMCSD_MODE_EMMCBOOT; -#else - boot_mode = MMCSD_MODE_UNDEFINED; -#endif - } -#endif - - gd->arch.omap_boot_mode = boot_mode; - -#if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \ - !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX) - - /* CH flags */ - - gd->arch.omap_ch_flags = omap_boot_params->ch_flags; -#endif -} - -#ifdef CONFIG_SPL_BUILD -u32 spl_boot_device(void) -{ - return gd->arch.omap_boot_device; -} - -u32 spl_boot_mode(const u32 boot_device) -{ - return gd->arch.omap_boot_mode; -} - -void spl_board_init(void) -{ - /* - * Save the boot parameters passed from romcode. - * We cannot delay the saving further than this, - * to prevent overwrites. - */ - save_omap_boot_params(); - - /* Prepare console output */ - preloader_console_init(); - -#if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT) - gpmc_init(); -#endif -#ifdef CONFIG_SPL_I2C_SUPPORT - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); -#endif -#if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) - arch_misc_init(); -#endif -#if defined(CONFIG_HW_WATCHDOG) - hw_watchdog_init(); -#endif -#ifdef CONFIG_AM33XX - am33xx_spl_board_init(); -#endif -} - -__weak int board_mmc_init(bd_t *bis) -{ - switch (spl_boot_device()) { - case BOOT_DEVICE_MMC1: - omap_mmc_init(0, 0, 0, -1, -1); - break; - case BOOT_DEVICE_MMC2: - case BOOT_DEVICE_MMC2_2: - omap_mmc_init(0, 0, 0, -1, -1); - omap_mmc_init(1, 0, 0, -1, -1); - break; - } - return 0; -} - -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) -{ - typedef void __noreturn (*image_entry_noargs_t)(u32 *); - image_entry_noargs_t image_entry = - (image_entry_noargs_t) spl_image->entry_point; - - u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); - - debug("image entry point: 0x%X\n", spl_image->entry_point); - /* Pass the saved boot_params from rom code */ - image_entry((u32 *)boot_params); -} -#endif - -#ifdef CONFIG_SCSI_AHCI_PLAT -void arch_preboot_os(void) -{ - ahci_reset((void __iomem *)DWC_AHSATA_BASE); -} -#endif - -#if defined(CONFIG_USB_FUNCTION_FASTBOOT) && !defined(CONFIG_ENV_IS_NOWHERE) -int fb_set_reboot_flag(void) -{ - printf("Setting reboot to fastboot flag ...\n"); - setenv("dofastboot", "1"); - saveenv(); - return 0; -} -#endif diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c deleted file mode 100644 index 9b97583..0000000 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ /dev/null @@ -1,892 +0,0 @@ -/* - * - * Clock initialization for OMAP4 - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Aneesh V <aneesh@ti.com> - * - * Based on previous work by: - * Santosh Shilimkar <santosh.shilimkar@ti.com> - * Rajendra Nayak <rnayak@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <i2c.h> -#include <asm/omap_common.h> -#include <asm/gpio.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <asm/utils.h> -#include <asm/omap_gpio.h> -#include <asm/emif.h> - -#ifndef CONFIG_SPL_BUILD -/* - * printing to console doesn't work unless - * this code is executed from SPL - */ -#define printf(fmt, args...) -#define puts(s) -#endif - -const u32 sys_clk_array[8] = { - 12000000, /* 12 MHz */ - 20000000, /* 20 MHz */ - 16800000, /* 16.8 MHz */ - 19200000, /* 19.2 MHz */ - 26000000, /* 26 MHz */ - 27000000, /* 27 MHz */ - 38400000, /* 38.4 MHz */ -}; - -static inline u32 __get_sys_clk_index(void) -{ - s8 ind; - /* - * For ES1 the ROM code calibration of sys clock is not reliable - * due to hw issue. So, use hard-coded value. If this value is not - * correct for any board over-ride this function in board file - * From ES2.0 onwards you will get this information from - * CM_SYS_CLKSEL - */ - if (omap_revision() == OMAP4430_ES1_0) - ind = OMAP_SYS_CLK_IND_38_4_MHZ; - else { - /* SYS_CLKSEL - 1 to match the dpll param array indices */ - ind = (readl((*prcm)->cm_sys_clksel) & - CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1; - } - return ind; -} - -u32 get_sys_clk_index(void) - __attribute__ ((weak, alias("__get_sys_clk_index"))); - -u32 get_sys_clk_freq(void) -{ - u8 index = get_sys_clk_index(); - return sys_clk_array[index]; -} - -void setup_post_dividers(u32 const base, const struct dpll_params *params) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - /* Setup post-dividers */ - if (params->m2 >= 0) - writel(params->m2, &dpll_regs->cm_div_m2_dpll); - if (params->m3 >= 0) - writel(params->m3, &dpll_regs->cm_div_m3_dpll); - if (params->m4_h11 >= 0) - writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll); - if (params->m5_h12 >= 0) - writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll); - if (params->m6_h13 >= 0) - writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll); - if (params->m7_h14 >= 0) - writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll); - if (params->h21 >= 0) - writel(params->h21, &dpll_regs->cm_div_h21_dpll); - if (params->h22 >= 0) - writel(params->h22, &dpll_regs->cm_div_h22_dpll); - if (params->h23 >= 0) - writel(params->h23, &dpll_regs->cm_div_h23_dpll); - if (params->h24 >= 0) - writel(params->h24, &dpll_regs->cm_div_h24_dpll); -} - -static inline void do_bypass_dpll(u32 const base) -{ - struct dpll_regs *dpll_regs = (struct dpll_regs *)base; - - clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, - CM_CLKMODE_DPLL_DPLL_EN_MASK, - DPLL_EN_FAST_RELOCK_BYPASS << - CM_CLKMODE_DPLL_EN_SHIFT); -} - -static inline void wait_for_bypass(u32 const base) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll, - LDELAY)) { - printf("Bypassing DPLL failed %x\n", base); - } -} - -static inline void do_lock_dpll(u32 const base) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - clrsetbits_le32(&dpll_regs->cm_clkmode_dpll, - CM_CLKMODE_DPLL_DPLL_EN_MASK, - DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); -} - -static inline void wait_for_lock(u32 const base) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK, - &dpll_regs->cm_idlest_dpll, LDELAY)) { - printf("DPLL locking failed for %x\n", base); - hang(); - } -} - -inline u32 check_for_lock(u32 const base) -{ - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK; - - return lock; -} - -const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &dpll_data->mpu[sysclk_ind]; -} - -const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &dpll_data->core[sysclk_ind]; -} - -const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &dpll_data->per[sysclk_ind]; -} - -const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &dpll_data->iva[sysclk_ind]; -} - -const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data) -{ - u32 sysclk_ind = get_sys_clk_index(); - return &dpll_data->usb[sysclk_ind]; -} - -const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data) -{ -#ifdef CONFIG_SYS_OMAP_ABE_SYSCK - u32 sysclk_ind = get_sys_clk_index(); - return &dpll_data->abe[sysclk_ind]; -#else - return dpll_data->abe; -#endif -} - -static const struct dpll_params *get_ddr_dpll_params - (struct dplls const *dpll_data) -{ - u32 sysclk_ind = get_sys_clk_index(); - - if (!dpll_data->ddr) - return NULL; - return &dpll_data->ddr[sysclk_ind]; -} - -#ifdef CONFIG_DRIVER_TI_CPSW -static const struct dpll_params *get_gmac_dpll_params - (struct dplls const *dpll_data) -{ - u32 sysclk_ind = get_sys_clk_index(); - - if (!dpll_data->gmac) - return NULL; - return &dpll_data->gmac[sysclk_ind]; -} -#endif - -static void do_setup_dpll(u32 const base, const struct dpll_params *params, - u8 lock, char *dpll) -{ - u32 temp, M, N; - struct dpll_regs *const dpll_regs = (struct dpll_regs *)base; - - if (!params) - return; - - temp = readl(&dpll_regs->cm_clksel_dpll); - - if (check_for_lock(base)) { - /* - * The Dpll has already been locked by rom code using CH. - * Check if M,N are matching with Ideal nominal opp values. - * If matches, skip the rest otherwise relock. - */ - M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT; - N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT; - if ((M != (params->m)) || (N != (params->n))) { - debug("\n %s Dpll locked, but not for ideal M = %d," - "N = %d values, current values are M = %d," - "N= %d" , dpll, params->m, params->n, - M, N); - } else { - /* Dpll locked with ideal values for nominal opps. */ - debug("\n %s Dpll already locked with ideal" - "nominal opp values", dpll); - - bypass_dpll(base); - goto setup_post_dividers; - } - } - - bypass_dpll(base); - - /* Set M & N */ - temp &= ~CM_CLKSEL_DPLL_M_MASK; - temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK; - - temp &= ~CM_CLKSEL_DPLL_N_MASK; - temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK; - - writel(temp, &dpll_regs->cm_clksel_dpll); - -setup_post_dividers: - setup_post_dividers(base, params); - - /* Lock */ - if (lock) - do_lock_dpll(base); - - /* Wait till the DPLL locks */ - if (lock) - wait_for_lock(base); -} - -u32 omap_ddr_clk(void) -{ - u32 ddr_clk, sys_clk_khz, omap_rev, divider; - const struct dpll_params *core_dpll_params; - - omap_rev = omap_revision(); - sys_clk_khz = get_sys_clk_freq() / 1000; - - core_dpll_params = get_core_dpll_params(*dplls_data); - - debug("sys_clk %d\n ", sys_clk_khz * 1000); - - /* Find Core DPLL locked frequency first */ - ddr_clk = sys_clk_khz * 2 * core_dpll_params->m / - (core_dpll_params->n + 1); - - if (omap_rev < OMAP5430_ES1_0) { - /* - * DDR frequency is PHY_ROOT_CLK/2 - * PHY_ROOT_CLK = Fdpll/2/M2 - */ - divider = 4; - } else { - /* - * DDR frequency is PHY_ROOT_CLK - * PHY_ROOT_CLK = Fdpll/2/M2 - */ - divider = 2; - } - - ddr_clk = ddr_clk / divider / core_dpll_params->m2; - ddr_clk *= 1000; /* convert to Hz */ - debug("ddr_clk %d\n ", ddr_clk); - - return ddr_clk; -} - -/* - * Lock MPU dpll - * - * Resulting MPU frequencies: - * 4430 ES1.0 : 600 MHz - * 4430 ES2.x : 792 MHz (OPP Turbo) - * 4460 : 920 MHz (OPP Turbo) - DCC disabled - */ -void configure_mpu_dpll(void) -{ - const struct dpll_params *params; - struct dpll_regs *mpu_dpll_regs; - u32 omap_rev; - omap_rev = omap_revision(); - - /* - * DCC and clock divider settings for 4460. - * DCC is required, if more than a certain frequency is required. - * For, 4460 > 1GHZ. - * 5430 > 1.4GHZ. - */ - if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) { - mpu_dpll_regs = - (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu); - bypass_dpll((*prcm)->cm_clkmode_dpll_mpu); - clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl, - MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK); - setbits_le32((*prcm)->cm_mpu_mpu_clkctrl, - MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK); - clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll, - CM_CLKSEL_DCC_EN_MASK); - } - - params = get_mpu_dpll_params(*dplls_data); - - do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu"); - debug("MPU DPLL locked\n"); -} - -#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \ - defined(CONFIG_USB_MUSB_OMAP2PLUS) -static void setup_usb_dpll(void) -{ - const struct dpll_params *params; - u32 sys_clk_khz, sd_div, num, den; - - sys_clk_khz = get_sys_clk_freq() / 1000; - /* - * USB: - * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction - * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) - * - where CLKINP is sys_clk in MHz - * Use CLKINP in KHz and adjust the denominator accordingly so - * that we have enough accuracy and at the same time no overflow - */ - params = get_usb_dpll_params(*dplls_data); - num = params->m * sys_clk_khz; - den = (params->n + 1) * 250 * 1000; - num += den - 1; - sd_div = num / den; - clrsetbits_le32((*prcm)->cm_clksel_dpll_usb, - CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, - sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); - - /* Now setup the dpll with the regular function */ - do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb"); -} -#endif - -static void setup_dplls(void) -{ - u32 temp; - const struct dpll_params *params; - struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; - - debug("setup_dplls\n"); - - /* CORE dpll */ - params = get_core_dpll_params(*dplls_data); /* default - safest */ - /* - * Do not lock the core DPLL now. Just set it up. - * Core DPLL will be locked after setting up EMIF - * using the FREQ_UPDATE method(freq_update_core()) - */ - if (emif_sdram_type(readl(&emif->emif_sdram_config)) == - EMIF_SDRAM_TYPE_LPDDR2) - do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, - DPLL_NO_LOCK, "core"); - else - do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params, - DPLL_LOCK, "core"); - /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ - temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | - (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | - (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT); - writel(temp, (*prcm)->cm_clksel_core); - debug("Core DPLL configured\n"); - - /* lock PER dpll */ - params = get_per_dpll_params(*dplls_data); - do_setup_dpll((*prcm)->cm_clkmode_dpll_per, - params, DPLL_LOCK, "per"); - debug("PER DPLL locked\n"); - - /* MPU dpll */ - configure_mpu_dpll(); - -#if defined(CONFIG_USB_EHCI_OMAP) || defined(CONFIG_USB_XHCI_OMAP) || \ - defined(CONFIG_USB_MUSB_OMAP2PLUS) - setup_usb_dpll(); -#endif - params = get_ddr_dpll_params(*dplls_data); - do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy, - params, DPLL_LOCK, "ddr"); - -#ifdef CONFIG_DRIVER_TI_CPSW - params = get_gmac_dpll_params(*dplls_data); - do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params, - DPLL_LOCK, "gmac"); -#endif -} - -u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic) -{ - u32 offset_code; - - volt_offset -= pmic->base_offset; - - offset_code = (volt_offset + pmic->step - 1) / pmic->step; - - /* - * Offset codes 1-6 all give the base voltage in Palmas - * Offset code 0 switches OFF the SMPS - */ - return offset_code + pmic->start_code; -} - -void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) -{ - u32 offset_code; - u32 offset = volt_mv; - int ret = 0; - - if (!volt_mv) - return; - - pmic->pmic_bus_init(); - /* See if we can first get the GPIO if needed */ - if (pmic->gpio_en) - ret = gpio_request(pmic->gpio, "PMIC_GPIO"); - - if (ret < 0) { - printf("%s: gpio %d request failed %d\n", __func__, - pmic->gpio, ret); - return; - } - - /* Pull the GPIO low to select SET0 register, while we program SET1 */ - if (pmic->gpio_en) - gpio_direction_output(pmic->gpio, 0); - - /* convert to uV for better accuracy in the calculations */ - offset *= 1000; - - offset_code = get_offset_code(offset, pmic); - - debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv, - offset_code); - - if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code)) - printf("Scaling voltage failed for 0x%x\n", vcore_reg); - if (pmic->gpio_en) - gpio_direction_output(pmic->gpio, 1); -} - -static u32 optimize_vcore_voltage(struct volts const *v) -{ - u32 val; - if (!v->value) - return 0; - if (!v->efuse.reg) - return v->value; - - switch (v->efuse.reg_bits) { - case 16: - val = readw(v->efuse.reg); - break; - case 32: - val = readl(v->efuse.reg); - break; - default: - printf("Error: efuse 0x%08x bits=%d unknown\n", - v->efuse.reg, v->efuse.reg_bits); - return v->value; - } - - if (!val) { - printf("Error: efuse 0x%08x bits=%d val=0, using %d\n", - v->efuse.reg, v->efuse.reg_bits, v->value); - return v->value; - } - - debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n", - __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val); - return val; -} - -#ifdef CONFIG_IODELAY_RECALIBRATION -void __weak recalibrate_iodelay(void) -{ -} -#endif - -/* - * Setup the voltages for the main SoC core power domains. - * We start with the maximum voltages allowed here, as set in the corresponding - * vcores_data struct, and then scale (usually down) to the fused values that - * are retrieved from the SoC. The scaling happens only if the efuse.reg fields - * are initialised. - * Rail grouping is supported for the DRA7xx SoCs only, therefore the code is - * compiled conditionally. Note that the new code writes the scaled (or zeroed) - * values back to the vcores_data struct for eventual reuse. Zero values mean - * that the corresponding rails are not controlled separately, and are not sent - * to the PMIC. - */ -void scale_vcores(struct vcores_data const *vcores) -{ - int i; - struct volts *pv = (struct volts *)vcores; - struct volts *px; - - for (i=0; i<(sizeof(struct vcores_data)/sizeof(struct volts)); i++) { - debug("%d -> ", pv->value); - if (pv->value) { - /* Handle non-empty members only */ - pv->value = optimize_vcore_voltage(pv); - px = (struct volts *)vcores; - while (px < pv) { - /* - * Scan already handled non-empty members to see - * if we have a group and find the max voltage, - * which is set to the first occurance of the - * particular SMPS; the other group voltages are - * zeroed. - */ - if (px->value) { - if ((pv->pmic->i2c_slave_addr == - px->pmic->i2c_slave_addr) && - (pv->addr == px->addr)) { - /* Same PMIC, same SMPS */ - if (pv->value > px->value) - px->value = pv->value; - - pv->value = 0; - } - } - px++; - } - } - debug("%d\n", pv->value); - pv++; - } - - debug("cor: %d\n", vcores->core.value); - do_scale_vcore(vcores->core.addr, vcores->core.value, vcores->core.pmic); - /* - * IO delay recalibration should be done immediately after - * adjusting AVS voltages for VDD_CORE_L. - * Respective boards should call __recalibrate_iodelay() - * with proper mux, virtual and manual mode configurations. - */ -#ifdef CONFIG_IODELAY_RECALIBRATION - recalibrate_iodelay(); -#endif - - debug("mpu: %d\n", vcores->mpu.value); - do_scale_vcore(vcores->mpu.addr, vcores->mpu.value, vcores->mpu.pmic); - /* Configure MPU ABB LDO after scale */ - abb_setup(vcores->mpu.efuse.reg, - (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl, - (*prcm)->prm_abbldo_mpu_setup, - (*prcm)->prm_abbldo_mpu_ctrl, - (*prcm)->prm_irqstatus_mpu_2, - vcores->mpu.abb_tx_done_mask, - OMAP_ABB_FAST_OPP); - - debug("mm: %d\n", vcores->mm.value); - do_scale_vcore(vcores->mm.addr, vcores->mm.value, vcores->mm.pmic); - /* Configure MM ABB LDO after scale */ - abb_setup(vcores->mm.efuse.reg, - (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl, - (*prcm)->prm_abbldo_mm_setup, - (*prcm)->prm_abbldo_mm_ctrl, - (*prcm)->prm_irqstatus_mpu, - vcores->mm.abb_tx_done_mask, - OMAP_ABB_FAST_OPP); - - debug("gpu: %d\n", vcores->gpu.value); - do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic); - /* Configure GPU ABB LDO after scale */ - abb_setup(vcores->gpu.efuse.reg, - (*ctrl)->control_wkup_ldovbb_gpu_voltage_ctrl, - (*prcm)->prm_abbldo_gpu_setup, - (*prcm)->prm_abbldo_gpu_ctrl, - (*prcm)->prm_irqstatus_mpu, - vcores->gpu.abb_tx_done_mask, - OMAP_ABB_FAST_OPP); - debug("eve: %d\n", vcores->eve.value); - do_scale_vcore(vcores->eve.addr, vcores->eve.value, vcores->eve.pmic); - /* Configure EVE ABB LDO after scale */ - abb_setup(vcores->eve.efuse.reg, - (*ctrl)->control_wkup_ldovbb_eve_voltage_ctrl, - (*prcm)->prm_abbldo_eve_setup, - (*prcm)->prm_abbldo_eve_ctrl, - (*prcm)->prm_irqstatus_mpu, - vcores->eve.abb_tx_done_mask, - OMAP_ABB_FAST_OPP); - debug("iva: %d\n", vcores->iva.value); - do_scale_vcore(vcores->iva.addr, vcores->iva.value, vcores->iva.pmic); - /* Configure IVA ABB LDO after scale */ - abb_setup(vcores->iva.efuse.reg, - (*ctrl)->control_wkup_ldovbb_iva_voltage_ctrl, - (*prcm)->prm_abbldo_iva_setup, - (*prcm)->prm_abbldo_iva_ctrl, - (*prcm)->prm_irqstatus_mpu, - vcores->iva.abb_tx_done_mask, - OMAP_ABB_FAST_OPP); -} - -static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode) -{ - clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, - enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); - debug("Enable clock domain - %x\n", clkctrl_reg); -} - -static inline void disable_clock_domain(u32 const clkctrl_reg) -{ - clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, - CD_CLKCTRL_CLKTRCTRL_SW_SLEEP << - CD_CLKCTRL_CLKTRCTRL_SHIFT); - debug("Disable clock domain - %x\n", clkctrl_reg); -} - -static inline void wait_for_clk_enable(u32 clkctrl_addr) -{ - u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; - u32 bound = LDELAY; - - while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || - (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { - - clkctrl = readl(clkctrl_addr); - idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> - MODULE_CLKCTRL_IDLEST_SHIFT; - if (--bound == 0) { - printf("Clock enable failed for 0x%x idlest 0x%x\n", - clkctrl_addr, clkctrl); - return; - } - } -} - -static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode, - u32 wait_for_enable) -{ - clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, - enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT); - debug("Enable clock module - %x\n", clkctrl_addr); - if (wait_for_enable) - wait_for_clk_enable(clkctrl_addr); -} - -static inline void wait_for_clk_disable(u32 clkctrl_addr) -{ - u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL; - u32 bound = LDELAY; - - while ((idlest != MODULE_CLKCTRL_IDLEST_DISABLED)) { - clkctrl = readl(clkctrl_addr); - idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> - MODULE_CLKCTRL_IDLEST_SHIFT; - if (--bound == 0) { - printf("Clock disable failed for 0x%x idlest 0x%x\n", - clkctrl_addr, clkctrl); - return; - } - } -} - -static inline void disable_clock_module(u32 const clkctrl_addr, - u32 wait_for_disable) -{ - clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_DISABLE << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - debug("Disable clock module - %x\n", clkctrl_addr); - if (wait_for_disable) - wait_for_clk_disable(clkctrl_addr); -} - -void freq_update_core(void) -{ - u32 freq_config1 = 0; - const struct dpll_params *core_dpll_params; - u32 omap_rev = omap_revision(); - - core_dpll_params = get_core_dpll_params(*dplls_data); - /* Put EMIF clock domain in sw wakeup mode */ - enable_clock_domain((*prcm)->cm_memif_clkstctrl, - CD_CLKCTRL_CLKTRCTRL_SW_WKUP); - wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl); - wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl); - - freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK | - SHADOW_FREQ_CONFIG1_DLL_RESET_MASK; - - freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) & - SHADOW_FREQ_CONFIG1_DPLL_EN_MASK; - - freq_config1 |= (core_dpll_params->m2 << - SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) & - SHADOW_FREQ_CONFIG1_M2_DIV_MASK; - - writel(freq_config1, (*prcm)->cm_shadow_freq_config1); - if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0, - (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) { - puts("FREQ UPDATE procedure failed!!"); - hang(); - } - - /* - * Putting EMIF in HW_AUTO is seen to be causing issues with - * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP - * in OMAP5430 ES1.0 silicon - */ - if (omap_rev != OMAP5430_ES1_0) { - /* Put EMIF clock domain back in hw auto mode */ - enable_clock_domain((*prcm)->cm_memif_clkstctrl, - CD_CLKCTRL_CLKTRCTRL_HW_AUTO); - wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl); - wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl); - } -} - -void bypass_dpll(u32 const base) -{ - do_bypass_dpll(base); - wait_for_bypass(base); -} - -void lock_dpll(u32 const base) -{ - do_lock_dpll(base); - wait_for_lock(base); -} - -static void setup_clocks_for_console(void) -{ - /* Do not add any spl_debug prints in this function */ - clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, - CD_CLKCTRL_CLKTRCTRL_SW_WKUP << - CD_CLKCTRL_CLKTRCTRL_SHIFT); - - /* Enable all UARTs - console will be on one of them */ - clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - - clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - - clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - - clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl, - MODULE_CLKCTRL_MODULEMODE_MASK, - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << - MODULE_CLKCTRL_MODULEMODE_SHIFT); - - clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, - CD_CLKCTRL_CLKTRCTRL_HW_AUTO << - CD_CLKCTRL_CLKTRCTRL_SHIFT); -} - -void do_enable_clocks(u32 const *clk_domains, - u32 const *clk_modules_hw_auto, - u32 const *clk_modules_explicit_en, - u8 wait_for_enable) -{ - u32 i, max = 100; - - /* Put the clock domains in SW_WKUP mode */ - for (i = 0; (i < max) && clk_domains[i]; i++) { - enable_clock_domain(clk_domains[i], - CD_CLKCTRL_CLKTRCTRL_SW_WKUP); - } - - /* Clock modules that need to be put in HW_AUTO */ - for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) { - enable_clock_module(clk_modules_hw_auto[i], - MODULE_CLKCTRL_MODULEMODE_HW_AUTO, - wait_for_enable); - }; - - /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ - for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) { - enable_clock_module(clk_modules_explicit_en[i], - MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, - wait_for_enable); - }; - - /* Put the clock domains in HW_AUTO mode now */ - for (i = 0; (i < max) && clk_domains[i]; i++) { - enable_clock_domain(clk_domains[i], - CD_CLKCTRL_CLKTRCTRL_HW_AUTO); - } -} - -void do_disable_clocks(u32 const *clk_domains, - u32 const *clk_modules_disable, - u8 wait_for_disable) -{ - u32 i, max = 100; - - - /* Clock modules that need to be put in SW_DISABLE */ - for (i = 0; (i < max) && clk_modules_disable[i]; i++) - disable_clock_module(clk_modules_disable[i], - wait_for_disable); - - /* Put the clock domains in SW_SLEEP mode */ - for (i = 0; (i < max) && clk_domains[i]; i++) - disable_clock_domain(clk_domains[i]); -} - -/** - * setup_early_clocks() - Setup early clocks needed for SoC - * - * Setup clocks for console, SPL basic initialization clocks and initialize - * the timer. This is invoked prior prcm_init. - */ -void setup_early_clocks(void) -{ - switch (omap_hw_init_context()) { - case OMAP_INIT_CONTEXT_SPL: - case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: - case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: - setup_clocks_for_console(); - enable_basic_clocks(); - timer_init(); - /* Fall through */ - } -} - -void prcm_init(void) -{ - switch (omap_hw_init_context()) { - case OMAP_INIT_CONTEXT_SPL: - case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: - case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: - scale_vcores(*omap_vcores); - setup_dplls(); - setup_warmreset_time(); - break; - default: - break; - } - - if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context()) - enable_basic_uboot_clocks(); -} - -void gpi2c_init(void) -{ - static int gpi2c = 1; - - if (gpi2c) { - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, - CONFIG_SYS_OMAP24_I2C_SLAVE); - gpi2c = 0; - } -} diff --git a/arch/arm/cpu/armv7/omap-common/config_secure.mk b/arch/arm/cpu/armv7/omap-common/config_secure.mk deleted file mode 100644 index 1122439..0000000 --- a/arch/arm/cpu/armv7/omap-common/config_secure.mk +++ /dev/null @@ -1,113 +0,0 @@ -# -# Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/ -# -# SPDX-License-Identifier: GPL-2.0+ -# -quiet_cmd_mkomapsecimg = MKIMAGE $@ -ifneq ($(TI_SECURE_DEV_PKG),) -ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),) -ifneq ($(CONFIG_SPL_BUILD),) -cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \ - $(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \ - $(if $(KBUILD_VERBOSE:1=), >/dev/null) -else -cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \ - $(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \ - $(if $(KBUILD_VERBOSE:1=), >/dev/null) -endif -else -cmd_mkomapsecimg = echo "WARNING:" \ - "$(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh not found." \ - "$@ was NOT created!" -endif -else -cmd_mkomapsecimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \ - "variable must be defined for TI secure devices. $@ was NOT created!" -endif - -ifdef CONFIG_SPL_LOAD_FIT -quiet_cmd_omapsecureimg = SECURE $@ -ifneq ($(TI_SECURE_DEV_PKG),) -ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh),) -cmd_omapsecureimg = $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh \ - $< $@ \ - $(if $(KBUILD_VERBOSE:1=), >/dev/null) -else -cmd_omapsecureimg = echo "WARNING:" \ - "$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh not found." \ - "$@ was NOT created!"; cp $< $@ -endif -else -cmd_omapsecureimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \ - "variable must be defined for TI secure devices." \ - "$@ was NOT created!"; cp $< $@ -endif -endif - - -# Standard X-LOADER target (QPSI, NOR flash) -u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin - $(call if_changed,mkomapsecimg) - -# For MLO targets (SD card boot) the final file name that is copied to the SD -# card FAT partition must be MLO, so we make a copy of the output file to a new -# file with that name -u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin - $(call if_changed,mkomapsecimg) - @if [ -f $@ ]; then \ - cp -f $@ MLO; \ - fi - -# Standard 2ND target (certain peripheral boot modes) -u-boot-spl_HS_2ND: $(obj)/u-boot-spl.bin - $(call if_changed,mkomapsecimg) - -# Standard ULO target (certain peripheral boot modes) -u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin - $(call if_changed,mkomapsecimg) - -# Standard ISSW target (certain devices, various boot modes) -u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin - $(call if_changed,mkomapsecimg) - -# For SPI flash on AM335x and AM43xx, these require special byte swap handling -# so we use the SPI_X-LOADER target instead of X-LOADER and let the -# create-boot-image.sh script handle that -u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin - $(call if_changed,mkomapsecimg) - -# For supporting single stage XiP QSPI on AM43xx, the image is a full u-boot -# file, not an SPL. In this case the mkomapsecimg command looks for a -# u-boot-HS_* prefix -u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin - $(call if_changed,mkomapsecimg) - -# For supporting the SPL loading and interpreting of FIT images whose -# components are pre-processed before being integrated into the FIT image in -# order to secure them in some way -ifdef CONFIG_SPL_LOAD_FIT - -MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ - -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ - -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ - $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) - -OF_LIST_TARGETS = $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) -$(OF_LIST_TARGETS): dtbs - -%_HS.dtb: %.dtb - $(call if_changed,omapsecureimg) - $(Q)if [ -f $@ ]; then \ - cp -f $@ $<; \ - fi - -u-boot-nodtb_HS.bin: u-boot-nodtb.bin - $(call if_changed,omapsecureimg) - -u-boot_HS.img: u-boot-nodtb_HS.bin u-boot.img $(patsubst %.dtb,%_HS.dtb,$(OF_LIST_TARGETS)) - $(call if_changed,mkimage) - $(Q)if [ -f $@ ]; then \ - cp -f $@ u-boot.img; \ - fi - -endif diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c deleted file mode 100644 index b26984e..0000000 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ /dev/null @@ -1,1504 +0,0 @@ -/* - * EMIF programming - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Aneesh V <aneesh@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/emif.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <asm/omap_common.h> -#include <asm/omap_sec_common.h> -#include <asm/utils.h> -#include <linux/compiler.h> - -static int emif1_enabled = -1, emif2_enabled = -1; - -void set_lpmode_selfrefresh(u32 base) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 reg; - - reg = readl(&emif->emif_pwr_mgmt_ctrl); - reg &= ~EMIF_REG_LP_MODE_MASK; - reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT; - reg &= ~EMIF_REG_SR_TIM_MASK; - writel(reg, &emif->emif_pwr_mgmt_ctrl); - - /* dummy read for the new SR_TIM to be loaded */ - readl(&emif->emif_pwr_mgmt_ctrl); -} - -void force_emif_self_refresh() -{ - set_lpmode_selfrefresh(EMIF1_BASE); - if (!is_dra72x()) - set_lpmode_selfrefresh(EMIF2_BASE); -} - -inline u32 emif_num(u32 base) -{ - if (base == EMIF1_BASE) - return 1; - else if (base == EMIF2_BASE) - return 2; - else - return 0; -} - -static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr) -{ - u32 mr; - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - mr_addr |= cs << EMIF_REG_CS_SHIFT; - writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); - if (omap_revision() == OMAP4430_ES2_0) - mr = readl(&emif->emif_lpddr2_mode_reg_data_es2); - else - mr = readl(&emif->emif_lpddr2_mode_reg_data); - debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base), - cs, mr_addr, mr); - if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && - ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && - ((mr & 0xff000000) >> 24) == (mr & 0xff)) - return mr & 0xff; - else - return mr; -} - -static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - mr_addr |= cs << EMIF_REG_CS_SHIFT; - writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg); - writel(mr_val, &emif->emif_lpddr2_mode_reg_data); -} - -void emif_reset_phy(u32 base) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 iodft; - - iodft = readl(&emif->emif_iodft_tlgc); - iodft |= EMIF_REG_RESET_PHY_MASK; - writel(iodft, &emif->emif_iodft_tlgc); -} - -static void do_lpddr2_init(u32 base, u32 cs) -{ - u32 mr_addr; - const struct lpddr2_mr_regs *mr_regs; - - get_lpddr2_mr_regs(&mr_regs); - /* Wait till device auto initialization is complete */ - while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK) - ; - set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10); - /* - * tZQINIT = 1 us - * Enough loops assuming a maximum of 2GHz - */ - - sdelay(2000); - - set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1); - set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16); - - /* - * Enable refresh along with writing MR2 - * Encoding of RL in MR2 is (RL - 2) - */ - mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK; - set_mr(base, cs, mr_addr, mr_regs->mr2); - - if (mr_regs->mr3 > 0) - set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3); -} - -static void lpddr2_init(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - /* Not NVM */ - clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK); - - /* - * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM - * when EMIF_SDRAM_CONFIG register is written - */ - setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); - - /* - * Set the SDRAM_CONFIG and PHY_CTRL for the - * un-locked frequency & default RL - */ - writel(regs->sdram_config_init, &emif->emif_sdram_config); - writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); - - do_ext_phy_settings(base, regs); - - do_lpddr2_init(base, CS0); - if (regs->sdram_config & EMIF_REG_EBANK_MASK) - do_lpddr2_init(base, CS1); - - writel(regs->sdram_config, &emif->emif_sdram_config); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); - - /* Enable refresh now */ - clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); - - } - -__weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs) -{ -} - -void emif_update_timings(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - if (!is_dra7xx()) - writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw); - else - writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw); - - writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw); - writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw); - writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw); - if (omap_revision() == OMAP4430_ES1_0) { - /* ES1 bug EMIF should be in force idle during freq_update */ - writel(0, &emif->emif_pwr_mgmt_ctrl); - } else { - writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl); - writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw); - } - writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw); - writel(regs->zq_config, &emif->emif_zq_config); - writel(regs->temp_alert_config, &emif->emif_temp_alert_config); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); - - if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) { - writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, - &emif->emif_l3_config); - } else if (omap_revision() >= OMAP4460_ES1_0) { - writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0, - &emif->emif_l3_config); - } else { - writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0, - &emif->emif_l3_config); - } -} - -#ifndef CONFIG_OMAP44XX -static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - /* keep sdram in self-refresh */ - writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT) - & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); - __udelay(130); - - /* - * Set invert_clkout (if activated)--DDR_PHYCTRL_1 - * Invert clock adds an additional half cycle delay on the - * command interface. The additional half cycle, is usually - * meant to enable leveling in the situation that DQS is later - * than CK on the board.It also helps provide some additional - * margin for leveling. - */ - writel(regs->emif_ddr_phy_ctlr_1, - &emif->emif_ddr_phy_ctrl_1); - - writel(regs->emif_ddr_phy_ctlr_1, - &emif->emif_ddr_phy_ctrl_1_shdw); - __udelay(130); - - writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT) - & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); - - /* Launch Full leveling */ - writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); - - /* Wait till full leveling is complete */ - readl(&emif->emif_rd_wr_lvl_ctl); - __udelay(130); - - /* Read data eye leveling no of samples */ - config_data_eye_leveling_samples(base); - - /* - * Launch 8 incremental WR_LVL- to compensate for - * PHY limitation. - */ - writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, - &emif->emif_rd_wr_lvl_ctl); - - __udelay(130); - - /* Launch Incremental leveling */ - writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl); - __udelay(130); -} - -static void update_hwleveling_output(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 *emif_ext_phy_ctrl_reg, *emif_phy_status; - u32 reg, i, phy; - - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7]; - phy = readl(&emif->emif_ddr_phy_ctrl_1); - - /* Update PHY_REG_RDDQS_RATIO */ - emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7; - if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)) - for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) { - reg = readl(emif_phy_status++); - writel(reg, emif_ext_phy_ctrl_reg++); - writel(reg, emif_ext_phy_ctrl_reg++); - } - - /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */ - emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12]; - if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)) - for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) { - reg = readl(emif_phy_status++); - writel(reg, emif_ext_phy_ctrl_reg++); - writel(reg, emif_ext_phy_ctrl_reg++); - } - - /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */ - emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12; - emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17]; - if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)) - for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) { - reg = readl(emif_phy_status++); - writel(reg, emif_ext_phy_ctrl_reg++); - writel(reg, emif_ext_phy_ctrl_reg++); - } - - /* Disable Leveling */ - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); - writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); - writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl); -} - -static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - /* Clear Error Status */ - clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36, - EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, - EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); - - clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw, - EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR, - EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR); - - /* Disable refreshed before leveling */ - clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK, - EMIF_REG_INITREF_DIS_MASK); - - /* Start Full leveling */ - writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); - - __udelay(300); - - /* Check for leveling timeout */ - if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) { - printf("Leveling timeout on EMIF%d\n", emif_num(base)); - return; - } - - /* Enable refreshes after leveling */ - clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK); - - debug("HW leveling success\n"); - /* - * Update slave ratios in EXT_PHY_CTRLx registers - * as per HW leveling output - */ - update_hwleveling_output(base, regs); -} - -static void dra7_ddr3_init(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - if (warm_reset()) { - emif_reset_phy(base); - writel(0x0, &emif->emif_pwr_mgmt_ctrl); - } - do_ext_phy_settings(base, regs); - - writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK, - &emif->emif_sdram_ref_ctrl); - /* Update timing registers */ - writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); - writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); - writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); - - writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); - writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); - writel(regs->zq_config, &emif->emif_zq_config); - writel(regs->temp_alert_config, &emif->emif_temp_alert_config); - writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); - writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl); - - writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); - writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh); - - writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); - - writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); - writel(regs->sdram_config_init, &emif->emif_sdram_config); - - __udelay(1000); - - writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); - - if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK) - dra7_ddr3_leveling(base, regs); -} - -static void omap5_ddr3_init(u32 base, const struct emif_regs *regs) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); - writel(regs->sdram_config_init, &emif->emif_sdram_config); - /* - * Set SDRAM_CONFIG and PHY control registers to locked frequency - * and RL =7. As the default values of the Mode Registers are not - * defined, contents of mode Registers must be fully initialized. - * H/W takes care of this initialization - */ - writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); - - /* Update timing registers */ - writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); - writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); - writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); - - writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); - - writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); - writel(regs->sdram_config_init, &emif->emif_sdram_config); - do_ext_phy_settings(base, regs); - - writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); - omap5_ddr3_leveling(base, regs); -} - -static void ddr3_init(u32 base, const struct emif_regs *regs) -{ - if (is_omap54xx()) - omap5_ddr3_init(base, regs); - else - dra7_ddr3_init(base, regs); -} -#endif - -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg)) - -/* - * Organization and refresh requirements for LPDDR2 devices of different - * types and densities. Derived from JESD209-2 section 2.4 - */ -const struct lpddr2_addressing addressing_table[] = { - /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */ - {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */ - {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */ - {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */ - {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */ - {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */ - {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */ - {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */ - {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */ - {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */ - {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */ -}; - -static const u32 lpddr2_density_2_size_in_mbytes[] = { - 8, /* 64Mb */ - 16, /* 128Mb */ - 32, /* 256Mb */ - 64, /* 512Mb */ - 128, /* 1Gb */ - 256, /* 2Gb */ - 512, /* 4Gb */ - 1024, /* 8Gb */ - 2048, /* 16Gb */ - 4096 /* 32Gb */ -}; - -/* - * Calculate the period of DDR clock from frequency value and set the - * denominator and numerator in global variables for easy access later - */ -static void set_ddr_clk_period(u32 freq) -{ - /* - * period = 1/freq - * period_in_ns = 10^9/freq - */ - *T_num = 1000000000; - *T_den = freq; - cancel_out(T_num, T_den, 200); - -} - -/* - * Convert time in nano seconds to number of cycles of DDR clock - */ -static inline u32 ns_2_cycles(u32 ns) -{ - return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num); -} - -/* - * ns_2_cycles with the difference that the time passed is 2 times the actual - * value(to avoid fractions). The cycles returned is for the original value of - * the timing parameter - */ -static inline u32 ns_x2_2_cycles(u32 ns) -{ - return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2); -} - -/* - * Find addressing table index based on the device's type(S2 or S4) and - * density - */ -s8 addressing_table_index(u8 type, u8 density, u8 width) -{ - u8 index; - if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8)) - return -1; - - /* - * Look at the way ADDR_TABLE_INDEX* values have been defined - * in emif.h compared to LPDDR2_DENSITY_* values - * The table is layed out in the increasing order of density - * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed - * at the end - */ - if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb)) - index = ADDR_TABLE_INDEX1GS2; - else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb)) - index = ADDR_TABLE_INDEX2GS2; - else - index = density; - - debug("emif: addressing table index %d\n", index); - - return index; -} - -/* - * Find the the right timing table from the array of timing - * tables of the device using DDR clock frequency - */ -static const struct lpddr2_ac_timings *get_timings_table(const struct - lpddr2_ac_timings const *const *device_timings, - u32 freq) -{ - u32 i, temp, freq_nearest; - const struct lpddr2_ac_timings *timings = 0; - - emif_assert(freq <= MAX_LPDDR2_FREQ); - emif_assert(device_timings); - - /* - * Start with the maximum allowed frequency - that is always safe - */ - freq_nearest = MAX_LPDDR2_FREQ; - /* - * Find the timings table that has the max frequency value: - * i. Above or equal to the DDR frequency - safe - * ii. The lowest that satisfies condition (i) - optimal - */ - for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) { - temp = device_timings[i]->max_freq; - if ((temp >= freq) && (temp <= freq_nearest)) { - freq_nearest = temp; - timings = device_timings[i]; - } - } - debug("emif: timings table: %d\n", freq_nearest); - return timings; -} - -/* - * Finds the value of emif_sdram_config_reg - * All parameters are programmed based on the device on CS0. - * If there is a device on CS1, it will be same as that on CS0 or - * it will be NVM. We don't support NVM yet. - * If cs1_device pointer is NULL it is assumed that there is no device - * on CS1 - */ -static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device, - const struct lpddr2_device_details *cs1_device, - const struct lpddr2_addressing *addressing, - u8 RL) -{ - u32 config_reg = 0; - - config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT; - config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING << - EMIF_REG_IBANK_POS_SHIFT; - - config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT; - - config_reg |= RL << EMIF_REG_CL_SHIFT; - - config_reg |= addressing->row_sz[cs0_device->io_width] << - EMIF_REG_ROWSIZE_SHIFT; - - config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT; - - config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) << - EMIF_REG_EBANK_SHIFT; - - config_reg |= addressing->col_sz[cs0_device->io_width] << - EMIF_REG_PAGESIZE_SHIFT; - - return config_reg; -} - -static u32 get_sdram_ref_ctrl(u32 freq, - const struct lpddr2_addressing *addressing) -{ - u32 ref_ctrl = 0, val = 0, freq_khz; - freq_khz = freq / 1000; - /* - * refresh rate to be set is 'tREFI * freq in MHz - * division by 10000 to account for khz and x10 in t_REFI_us_x10 - */ - val = addressing->t_REFI_us_x10 * freq_khz / 10000; - ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT; - - return ref_ctrl; -} - -static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings, - const struct lpddr2_min_tck *min_tck, - const struct lpddr2_addressing *addressing) -{ - u32 tim1 = 0, val = 0; - val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1; - tim1 |= val << EMIF_REG_T_WTR_SHIFT; - - if (addressing->num_banks == BANKS8) - val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) / - (4 * (*T_num)) - 1; - else - val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1; - - tim1 |= val << EMIF_REG_T_RRD_SHIFT; - - val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1; - tim1 |= val << EMIF_REG_T_RC_SHIFT; - - val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1; - tim1 |= val << EMIF_REG_T_RAS_SHIFT; - - val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1; - tim1 |= val << EMIF_REG_T_WR_SHIFT; - - val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1; - tim1 |= val << EMIF_REG_T_RCD_SHIFT; - - val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1; - tim1 |= val << EMIF_REG_T_RP_SHIFT; - - return tim1; -} - -static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings, - const struct lpddr2_min_tck *min_tck) -{ - u32 tim2 = 0, val = 0; - val = max(min_tck->tCKE, timings->tCKE) - 1; - tim2 |= val << EMIF_REG_T_CKE_SHIFT; - - val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1; - tim2 |= val << EMIF_REG_T_RTP_SHIFT; - - /* - * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the - * same value - */ - val = ns_2_cycles(timings->tXSR) - 1; - tim2 |= val << EMIF_REG_T_XSRD_SHIFT; - tim2 |= val << EMIF_REG_T_XSNR_SHIFT; - - val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1; - tim2 |= val << EMIF_REG_T_XP_SHIFT; - - return tim2; -} - -static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings, - const struct lpddr2_min_tck *min_tck, - const struct lpddr2_addressing *addressing) -{ - u32 tim3 = 0, val = 0; - val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF); - tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT; - - val = ns_2_cycles(timings->tRFCab) - 1; - tim3 |= val << EMIF_REG_T_RFC_SHIFT; - - val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1; - tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT; - - val = ns_2_cycles(timings->tZQCS) - 1; - tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT; - - val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1; - tim3 |= val << EMIF_REG_T_CKESR_SHIFT; - - return tim3; -} - -static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device, - const struct lpddr2_addressing *addressing, - u8 volt_ramp) -{ - u32 zq = 0, val = 0; - if (volt_ramp) - val = - EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 / - addressing->t_REFI_us_x10; - else - val = - EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 / - addressing->t_REFI_us_x10; - zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT; - - zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT; - - zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT; - - zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT; - - /* - * Assuming that two chipselects have a single calibration resistor - * If there are indeed two calibration resistors, then this flag should - * be enabled to take advantage of dual calibration feature. - * This data should ideally come from board files. But considering - * that none of the boards today have calibration resistors per CS, - * it would be an unnecessary overhead. - */ - zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT; - - zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT; - - zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT; - - return zq; -} - -static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device, - const struct lpddr2_addressing *addressing, - u8 is_derated) -{ - u32 alert = 0, interval; - interval = - TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10; - if (is_derated) - interval *= 4; - alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT; - - alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT; - - alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT; - - alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT; - - alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT; - - alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT; - - return alert; -} - -static u32 get_read_idle_ctrl_reg(u8 volt_ramp) -{ - u32 idle = 0, val = 0; - if (volt_ramp) - val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1; - else - /*Maximum value in normal conditions - suggested by hw team */ - val = 0x1FF; - idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT; - - idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT; - - return idle; -} - -static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL) -{ - u32 phy = 0, val = 0; - - phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT; - - if (freq <= 100000000) - val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS; - else if (freq <= 200000000) - val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ; - else - val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ; - phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT; - - /* Other fields are constant magic values. Hardcode them together */ - phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL << - EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT; - - return phy; -} - -static u32 get_emif_mem_size(u32 base) -{ - u32 size_mbytes = 0, temp; - struct emif_device_details dev_details; - struct lpddr2_device_details cs0_dev_details, cs1_dev_details; - u32 emif_nr = emif_num(base); - - emif_reset_phy(base); - dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, - &cs0_dev_details); - dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, - &cs1_dev_details); - emif_reset_phy(base); - - if (dev_details.cs0_device_details) { - temp = dev_details.cs0_device_details->density; - size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; - } - - if (dev_details.cs1_device_details) { - temp = dev_details.cs1_device_details->density; - size_mbytes += lpddr2_density_2_size_in_mbytes[temp]; - } - /* convert to bytes */ - return size_mbytes << 20; -} - -/* Gets the encoding corresponding to a given DMM section size */ -u32 get_dmm_section_size_map(u32 section_size) -{ - /* - * Section size mapping: - * 0x0: 16-MiB section - * 0x1: 32-MiB section - * 0x2: 64-MiB section - * 0x3: 128-MiB section - * 0x4: 256-MiB section - * 0x5: 512-MiB section - * 0x6: 1-GiB section - * 0x7: 2-GiB section - */ - section_size >>= 24; /* divide by 16 MB */ - return log_2_n_round_down(section_size); -} - -static void emif_calculate_regs( - const struct emif_device_details *emif_dev_details, - u32 freq, struct emif_regs *regs) -{ - u32 temp, sys_freq; - const struct lpddr2_addressing *addressing; - const struct lpddr2_ac_timings *timings; - const struct lpddr2_min_tck *min_tck; - const struct lpddr2_device_details *cs0_dev_details = - emif_dev_details->cs0_device_details; - const struct lpddr2_device_details *cs1_dev_details = - emif_dev_details->cs1_device_details; - const struct lpddr2_device_timings *cs0_dev_timings = - emif_dev_details->cs0_device_timings; - - emif_assert(emif_dev_details); - emif_assert(regs); - /* - * You can not have a device on CS1 without one on CS0 - * So configuring EMIF without a device on CS0 doesn't - * make sense - */ - emif_assert(cs0_dev_details); - emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM); - /* - * If there is a device on CS1 it should be same type as CS0 - * (or NVM. But NVM is not supported in this driver yet) - */ - emif_assert((cs1_dev_details == NULL) || - (cs1_dev_details->type == LPDDR2_TYPE_NVM) || - (cs0_dev_details->type == cs1_dev_details->type)); - emif_assert(freq <= MAX_LPDDR2_FREQ); - - set_ddr_clk_period(freq); - - /* - * The device on CS0 is used for all timing calculations - * There is only one set of registers for timings per EMIF. So, if the - * second CS(CS1) has a device, it should have the same timings as the - * device on CS0 - */ - timings = get_timings_table(cs0_dev_timings->ac_timings, freq); - emif_assert(timings); - min_tck = cs0_dev_timings->min_tck; - - temp = addressing_table_index(cs0_dev_details->type, - cs0_dev_details->density, - cs0_dev_details->io_width); - - emif_assert((temp >= 0)); - addressing = &(addressing_table[temp]); - emif_assert(addressing); - - sys_freq = get_sys_clk_freq(); - - regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details, - cs1_dev_details, - addressing, RL_BOOT); - - regs->sdram_config = get_sdram_config_reg(cs0_dev_details, - cs1_dev_details, - addressing, RL_FINAL); - - regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing); - - regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing); - - regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck); - - regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing); - - regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE); - - regs->temp_alert_config = - get_temp_alert_config(cs1_dev_details, addressing, 0); - - regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing, - LPDDR2_VOLTAGE_STABLE); - - regs->emif_ddr_phy_ctlr_1_init = - get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT); - - regs->emif_ddr_phy_ctlr_1 = - get_ddr_phy_ctrl_1(freq, RL_FINAL); - - regs->freq = freq; - - print_timing_reg(regs->sdram_config_init); - print_timing_reg(regs->sdram_config); - print_timing_reg(regs->ref_ctrl); - print_timing_reg(regs->sdram_tim1); - print_timing_reg(regs->sdram_tim2); - print_timing_reg(regs->sdram_tim3); - print_timing_reg(regs->read_idle_ctrl); - print_timing_reg(regs->temp_alert_config); - print_timing_reg(regs->zq_config); - print_timing_reg(regs->emif_ddr_phy_ctlr_1); - print_timing_reg(regs->emif_ddr_phy_ctlr_1_init); -} -#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ - -#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -const char *get_lpddr2_type(u8 type_id) -{ - switch (type_id) { - case LPDDR2_TYPE_S4: - return "LPDDR2-S4"; - case LPDDR2_TYPE_S2: - return "LPDDR2-S2"; - default: - return NULL; - } -} - -const char *get_lpddr2_io_width(u8 width_id) -{ - switch (width_id) { - case LPDDR2_IO_WIDTH_8: - return "x8"; - case LPDDR2_IO_WIDTH_16: - return "x16"; - case LPDDR2_IO_WIDTH_32: - return "x32"; - default: - return NULL; - } -} - -const char *get_lpddr2_manufacturer(u32 manufacturer) -{ - switch (manufacturer) { - case LPDDR2_MANUFACTURER_SAMSUNG: - return "Samsung"; - case LPDDR2_MANUFACTURER_QIMONDA: - return "Qimonda"; - case LPDDR2_MANUFACTURER_ELPIDA: - return "Elpida"; - case LPDDR2_MANUFACTURER_ETRON: - return "Etron"; - case LPDDR2_MANUFACTURER_NANYA: - return "Nanya"; - case LPDDR2_MANUFACTURER_HYNIX: - return "Hynix"; - case LPDDR2_MANUFACTURER_MOSEL: - return "Mosel"; - case LPDDR2_MANUFACTURER_WINBOND: - return "Winbond"; - case LPDDR2_MANUFACTURER_ESMT: - return "ESMT"; - case LPDDR2_MANUFACTURER_SPANSION: - return "Spansion"; - case LPDDR2_MANUFACTURER_SST: - return "SST"; - case LPDDR2_MANUFACTURER_ZMOS: - return "ZMOS"; - case LPDDR2_MANUFACTURER_INTEL: - return "Intel"; - case LPDDR2_MANUFACTURER_NUMONYX: - return "Numonyx"; - case LPDDR2_MANUFACTURER_MICRON: - return "Micron"; - default: - return NULL; - } -} - -static void display_sdram_details(u32 emif_nr, u32 cs, - struct lpddr2_device_details *device) -{ - const char *mfg_str; - const char *type_str; - char density_str[10]; - u32 density; - - debug("EMIF%d CS%d\t", emif_nr, cs); - - if (!device) { - debug("None\n"); - return; - } - - mfg_str = get_lpddr2_manufacturer(device->manufacturer); - type_str = get_lpddr2_type(device->type); - - density = lpddr2_density_2_size_in_mbytes[device->density]; - if ((density / 1024 * 1024) == density) { - density /= 1024; - sprintf(density_str, "%d GB", density); - } else - sprintf(density_str, "%d MB", density); - if (mfg_str && type_str) - debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str); -} - -static u8 is_lpddr2_sdram_present(u32 base, u32 cs, - struct lpddr2_device_details *lpddr2_device) -{ - u32 mr = 0, temp; - - mr = get_mr(base, cs, LPDDR2_MR0); - if (mr > 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT; - if (temp) { - /* Not SDRAM */ - return 0; - } - temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT; - - if (temp) { - /* DNV supported - But DNV is only supported for NVM */ - return 0; - } - - mr = get_mr(base, cs, LPDDR2_MR4); - if (mr > 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - mr = get_mr(base, cs, LPDDR2_MR5); - if (mr > 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - if (!get_lpddr2_manufacturer(mr)) { - /* Manufacturer not identified */ - return 0; - } - lpddr2_device->manufacturer = mr; - - mr = get_mr(base, cs, LPDDR2_MR6); - if (mr >= 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - mr = get_mr(base, cs, LPDDR2_MR7); - if (mr >= 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - mr = get_mr(base, cs, LPDDR2_MR8); - if (mr >= 0xFF) { - /* Mode register value bigger than 8 bit */ - return 0; - } - - temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT; - if (!get_lpddr2_type(temp)) { - /* Not SDRAM */ - return 0; - } - lpddr2_device->type = temp; - - temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT; - if (temp > LPDDR2_DENSITY_32Gb) { - /* Density not supported */ - return 0; - } - lpddr2_device->density = temp; - - temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT; - if (!get_lpddr2_io_width(temp)) { - /* IO width unsupported value */ - return 0; - } - lpddr2_device->io_width = temp; - - /* - * If all the above tests pass we should - * have a device on this chip-select - */ - return 1; -} - -struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs, - struct lpddr2_device_details *lpddr2_dev_details) -{ - u32 phy; - u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE; - - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - - if (!lpddr2_dev_details) - return NULL; - - /* Do the minimum init for mode register accesses */ - if (!(running_from_sdram() || warm_reset())) { - phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT); - writel(phy, &emif->emif_ddr_phy_ctrl_1); - } - - if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details))) - return NULL; - - display_sdram_details(emif_num(base), cs, lpddr2_dev_details); - - return lpddr2_dev_details; -} -#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */ - -static void do_sdram_init(u32 base) -{ - const struct emif_regs *regs; - u32 in_sdram, emif_nr; - - debug(">>do_sdram_init() %x\n", base); - - in_sdram = running_from_sdram(); - emif_nr = (base == EMIF1_BASE) ? 1 : 2; - -#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - emif_get_reg_dump(emif_nr, ®s); - if (!regs) { - debug("EMIF: reg dump not provided\n"); - return; - } -#else - /* - * The user has not provided the register values. We need to - * calculate it based on the timings and the DDR frequency - */ - struct emif_device_details dev_details; - struct emif_regs calculated_regs; - - /* - * Get device details: - * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set - * - Obtained from user otherwise - */ - struct lpddr2_device_details cs0_dev_details, cs1_dev_details; - emif_reset_phy(base); - dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0, - &cs0_dev_details); - dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1, - &cs1_dev_details); - emif_reset_phy(base); - - /* Return if no devices on this EMIF */ - if (!dev_details.cs0_device_details && - !dev_details.cs1_device_details) { - return; - } - - /* - * Get device timings: - * - Default timings specified by JESD209-2 if - * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set - * - Obtained from user otherwise - */ - emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings, - &dev_details.cs1_device_timings); - - /* Calculate the register values */ - emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs); - regs = &calculated_regs; -#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */ - - /* - * Initializing the DDR device can not happen from SDRAM. - * Changing the timing registers in EMIF can happen(going from one - * OPP to another) - */ - if (!in_sdram && (!warm_reset() || is_dra7xx())) { - if (emif_sdram_type(regs->sdram_config) == - EMIF_SDRAM_TYPE_LPDDR2) - lpddr2_init(base, regs); -#ifndef CONFIG_OMAP44XX - else - ddr3_init(base, regs); -#endif - } -#ifdef CONFIG_OMAP54X - if (warm_reset() && (emif_sdram_type(regs->sdram_config) == - EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) { - set_lpmode_selfrefresh(base); - emif_reset_phy(base); - omap5_ddr3_leveling(base, regs); - } -#endif - - /* Write to the shadow registers */ - emif_update_timings(base, regs); - - debug("<<do_sdram_init() %x\n", base); -} - -void emif_post_init_config(u32 base) -{ - struct emif_reg_struct *emif = (struct emif_reg_struct *)base; - u32 omap_rev = omap_revision(); - - /* reset phy on ES2.0 */ - if (omap_rev == OMAP4430_ES2_0) - emif_reset_phy(base); - - /* Put EMIF back in smart idle on ES1.0 */ - if (omap_rev == OMAP4430_ES1_0) - writel(0x80000000, &emif->emif_pwr_mgmt_ctrl); -} - -void dmm_init(u32 base) -{ - const struct dmm_lisa_map_regs *lisa_map_regs; - u32 i, section, valid; - -#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - emif_get_dmm_regs(&lisa_map_regs); -#else - u32 emif1_size, emif2_size, mapped_size, section_map = 0; - u32 section_cnt, sys_addr; - struct dmm_lisa_map_regs lis_map_regs_calculated = {0}; - - mapped_size = 0; - section_cnt = 3; - sys_addr = CONFIG_SYS_SDRAM_BASE; - emif1_size = get_emif_mem_size(EMIF1_BASE); - emif2_size = get_emif_mem_size(EMIF2_BASE); - debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); - - if (!emif1_size && !emif2_size) - return; - - /* symmetric interleaved section */ - if (emif1_size && emif2_size) { - mapped_size = min(emif1_size, emif2_size); - section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL; - section_map |= 0 << EMIF_SDRC_ADDR_SHIFT; - /* only MSB */ - section_map |= (sys_addr >> 24) << - EMIF_SYS_ADDR_SHIFT; - section_map |= get_dmm_section_size_map(mapped_size * 2) - << EMIF_SYS_SIZE_SHIFT; - lis_map_regs_calculated.dmm_lisa_map_3 = section_map; - emif1_size -= mapped_size; - emif2_size -= mapped_size; - sys_addr += (mapped_size * 2); - section_cnt--; - } - - /* - * Single EMIF section(we can have a maximum of 1 single EMIF - * section- either EMIF1 or EMIF2 or none, but not both) - */ - if (emif1_size) { - section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL; - section_map |= get_dmm_section_size_map(emif1_size) - << EMIF_SYS_SIZE_SHIFT; - /* only MSB */ - section_map |= (mapped_size >> 24) << - EMIF_SDRC_ADDR_SHIFT; - /* only MSB */ - section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT; - section_cnt--; - } - if (emif2_size) { - section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL; - section_map |= get_dmm_section_size_map(emif2_size) << - EMIF_SYS_SIZE_SHIFT; - /* only MSB */ - section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT; - /* only MSB */ - section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT; - section_cnt--; - } - - if (section_cnt == 2) { - /* Only 1 section - either symmetric or single EMIF */ - lis_map_regs_calculated.dmm_lisa_map_3 = section_map; - lis_map_regs_calculated.dmm_lisa_map_2 = 0; - lis_map_regs_calculated.dmm_lisa_map_1 = 0; - } else { - /* 2 sections - 1 symmetric, 1 single EMIF */ - lis_map_regs_calculated.dmm_lisa_map_2 = section_map; - lis_map_regs_calculated.dmm_lisa_map_1 = 0; - } - - /* TRAP for invalid TILER mappings in section 0 */ - lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP; - - if (omap_revision() >= OMAP4460_ES1_0) - lis_map_regs_calculated.is_ma_present = 1; - - lisa_map_regs = &lis_map_regs_calculated; -#endif - struct dmm_lisa_map_regs *hw_lisa_map_regs = - (struct dmm_lisa_map_regs *)base; - - writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); - - writel(lisa_map_regs->dmm_lisa_map_3, - &hw_lisa_map_regs->dmm_lisa_map_3); - writel(lisa_map_regs->dmm_lisa_map_2, - &hw_lisa_map_regs->dmm_lisa_map_2); - writel(lisa_map_regs->dmm_lisa_map_1, - &hw_lisa_map_regs->dmm_lisa_map_1); - writel(lisa_map_regs->dmm_lisa_map_0, - &hw_lisa_map_regs->dmm_lisa_map_0); - - if (lisa_map_regs->is_ma_present) { - hw_lisa_map_regs = - (struct dmm_lisa_map_regs *)MA_BASE; - - writel(lisa_map_regs->dmm_lisa_map_3, - &hw_lisa_map_regs->dmm_lisa_map_3); - writel(lisa_map_regs->dmm_lisa_map_2, - &hw_lisa_map_regs->dmm_lisa_map_2); - writel(lisa_map_regs->dmm_lisa_map_1, - &hw_lisa_map_regs->dmm_lisa_map_1); - writel(lisa_map_regs->dmm_lisa_map_0, - &hw_lisa_map_regs->dmm_lisa_map_0); - - setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK); - } - - /* - * EMIF should be configured only when - * memory is mapped on it. Using emif1_enabled - * and emif2_enabled variables for this. - */ - emif1_enabled = 0; - emif2_enabled = 0; - for (i = 0; i < 4; i++) { - section = __raw_readl(DMM_BASE + i*4); - valid = (section & EMIF_SDRC_MAP_MASK) >> - (EMIF_SDRC_MAP_SHIFT); - if (valid == 3) { - emif1_enabled = 1; - emif2_enabled = 1; - break; - } - - if (valid == 1) - emif1_enabled = 1; - - if (valid == 2) - emif2_enabled = 1; - } -} - -static void do_bug0039_workaround(u32 base) -{ - u32 val, i, clkctrl; - struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base; - const struct read_write_regs *bug_00339_regs; - u32 iterations; - u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0]; - u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1; - - if (is_dra7xx()) - phy_status_base++; - - bug_00339_regs = get_bug_regs(&iterations); - - /* Put EMIF in to idle */ - clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl); - __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl); - - /* Copy the phy status registers in to phy ctrl shadow registers */ - for (i = 0; i < iterations; i++) { - val = __raw_readl(phy_status_base + - bug_00339_regs[i].read_reg - 1); - - __raw_writel(val, phy_ctrl_base + - ((bug_00339_regs[i].write_reg - 1) << 1)); - - __raw_writel(val, phy_ctrl_base + - (bug_00339_regs[i].write_reg << 1) - 1); - } - - /* Disable leveling */ - writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl); - - __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl); -} - -/* - * SDRAM initialization: - * SDRAM initialization has two parts: - * 1. Configuring the SDRAM device - * 2. Update the AC timings related parameters in the EMIF module - * (1) should be done only once and should not be done while we are - * running from SDRAM. - * (2) can and should be done more than once if OPP changes. - * Particularly, this may be needed when we boot without SPL and - * and using Configuration Header(CH). ROM code supports only at 50% OPP - * at boot (low power boot). So u-boot has to switch to OPP100 and update - * the frequency. So, - * Doing (1) and (2) makes sense - first time initialization - * Doing (2) and not (1) makes sense - OPP change (when using CH) - * Doing (1) and not (2) doen't make sense - * See do_sdram_init() for the details - */ -void sdram_init(void) -{ - u32 in_sdram, size_prog, size_detect; - struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE; - u32 sdram_type = emif_sdram_type(emif->emif_sdram_config); - - debug(">>sdram_init()\n"); - - if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL) - return; - - in_sdram = running_from_sdram(); - debug("in_sdram = %d\n", in_sdram); - - if (!in_sdram) { - if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset()) - bypass_dpll((*prcm)->cm_clkmode_dpll_core); - else if (sdram_type == EMIF_SDRAM_TYPE_DDR3) - writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl); - } - - if (!in_sdram) - dmm_init(DMM_BASE); - - if (emif1_enabled) - do_sdram_init(EMIF1_BASE); - - if (emif2_enabled) - do_sdram_init(EMIF2_BASE); - - if (!(in_sdram || warm_reset())) { - if (emif1_enabled) - emif_post_init_config(EMIF1_BASE); - if (emif2_enabled) - emif_post_init_config(EMIF2_BASE); - } - - /* for the shadow registers to take effect */ - if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2) - freq_update_core(); - - /* Do some testing after the init */ - if (!in_sdram) { - size_prog = omap_sdram_size(); - size_prog = log_2_n_round_down(size_prog); - size_prog = (1 << size_prog); - - size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - size_prog); - /* Compare with the size programmed */ - if (size_detect != size_prog) { - printf("SDRAM: identified size not same as expected" - " size identified: %x expected: %x\n", - size_detect, - size_prog); - } else - debug("get_ram_size() successful"); - } - -#if defined(CONFIG_TI_SECURE_DEVICE) - /* - * On HS devices, do static EMIF firewall configuration - * but only do it if not already running in SDRAM - */ - if (!in_sdram) - if (0 != secure_emif_reserve()) - hang(); - - /* On HS devices, ensure static EMIF firewall APIs are locked */ - if (0 != secure_emif_firewall_lock()) - hang(); -#endif - - if (sdram_type == EMIF_SDRAM_TYPE_DDR3 && - (!in_sdram && !warm_reset()) && (!is_dra7xx())) { - if (emif1_enabled) - do_bug0039_workaround(EMIF1_BASE); - if (emif2_enabled) - do_bug0039_workaround(EMIF2_BASE); - } - - debug("<<sdram_init()\n"); -} diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c deleted file mode 100644 index f317293..0000000 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * - * Common functions for OMAP4/5 based boards - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Author : - * Aneesh V <aneesh@ti.com> - * Steve Sakoman <steve@sakoman.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <spl.h> -#include <asm/arch/sys_proto.h> -#include <linux/sizes.h> -#include <asm/emif.h> -#include <asm/omap_common.h> -#include <linux/compiler.h> -#include <asm/system.h> - -DECLARE_GLOBAL_DATA_PTR; - -void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) -{ - int i; - struct pad_conf_entry *pad = (struct pad_conf_entry *) array; - - for (i = 0; i < size; i++, pad++) - writew(pad->val, base + pad->offset); -} - -static void set_mux_conf_regs(void) -{ - switch (omap_hw_init_context()) { - case OMAP_INIT_CONTEXT_SPL: - set_muxconf_regs(); - break; - case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: - break; - case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: - case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: - set_muxconf_regs(); - break; - } -} - -u32 cortex_rev(void) -{ - - unsigned int rev; - - /* Read Main ID Register (MIDR) */ - asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); - - return rev; -} - -static void omap_rev_string(void) -{ - u32 omap_rev = omap_revision(); - u32 soc_variant = (omap_rev & 0xF0000000) >> 28; - u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16; - u32 major_rev = (omap_rev & 0x00000F00) >> 8; - u32 minor_rev = (omap_rev & 0x000000F0) >> 4; - - const char *sec_s; - - switch (get_device_type()) { - case TST_DEVICE: - sec_s = "TST"; - break; - case EMU_DEVICE: - sec_s = "EMU"; - break; - case HS_DEVICE: - sec_s = "HS"; - break; - case GP_DEVICE: - sec_s = "GP"; - break; - default: - sec_s = "?"; - } - - if (soc_variant) - printf("OMAP"); - else - printf("DRA"); - printf("%x-%s ES%x.%x\n", omap_variant, sec_s, major_rev, minor_rev); -} - -#ifdef CONFIG_SPL_BUILD -void spl_display_print(void) -{ - omap_rev_string(); -} -#endif - -void __weak srcomp_enable(void) -{ -} - -/** - * do_board_detect() - Detect board description - * - * Function to detect board description. This is expected to be - * overridden in the SoC family board file where desired. - */ -void __weak do_board_detect(void) -{ -} - -/** - * vcores_init() - Assign omap_vcores based on board - * - * Function to pick the vcores based on board. This is expected to be - * overridden in the SoC family board file where desired. - */ -void __weak vcores_init(void) -{ -} - -void s_init(void) -{ -} - -/** - * early_system_init - Does Early system initialization. - * - * Does early system init of watchdog, muxing, andclocks - * Watchdog disable is done always. For the rest what gets done - * depends on the boot mode in which this function is executed when - * 1. SPL running from SRAM - * 2. U-Boot running from FLASH - * 3. U-Boot loaded to SDRAM by SPL - * 4. U-Boot loaded to SDRAM by ROM code using the - * Configuration Header feature - * Please have a look at the respective functions to see what gets - * done in each of these cases - * This function is called with SRAM stack. - */ -void early_system_init(void) -{ - init_omap_revision(); - hw_data_init(); - -#ifdef CONFIG_SPL_BUILD - if (warm_reset()) - force_emif_self_refresh(); -#endif - watchdog_init(); - set_mux_conf_regs(); -#ifdef CONFIG_SPL_BUILD - srcomp_enable(); - do_io_settings(); -#endif - setup_early_clocks(); - do_board_detect(); - vcores_init(); - prcm_init(); -} - -#ifdef CONFIG_SPL_BUILD -void board_init_f(ulong dummy) -{ - early_system_init(); -#ifdef CONFIG_BOARD_EARLY_INIT_F - board_early_init_f(); -#endif - /* For regular u-boot sdram_init() is called from dram_init() */ - sdram_init(); -} -#endif - -int arch_cpu_init_dm(void) -{ - early_system_init(); - return 0; -} - -/* - * Routine: wait_for_command_complete - * Description: Wait for posting to finish on watchdog - */ -void wait_for_command_complete(struct watchdog *wd_base) -{ - int pending = 1; - do { - pending = readl(&wd_base->wwps); - } while (pending); -} - -/* - * Routine: watchdog_init - * Description: Shut down watch dogs - */ -void watchdog_init(void) -{ - struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE; - - writel(WD_UNLOCK1, &wd2_base->wspr); - wait_for_command_complete(wd2_base); - writel(WD_UNLOCK2, &wd2_base->wspr); -} - - -/* - * This function finds the SDRAM size available in the system - * based on DMM section configurations - * This is needed because the size of memory installed may be - * different on different versions of the board - */ -u32 omap_sdram_size(void) -{ - u32 section, i, valid; - u64 sdram_start = 0, sdram_end = 0, addr, - size, total_size = 0, trap_size = 0, trap_start = 0; - - for (i = 0; i < 4; i++) { - section = __raw_readl(DMM_BASE + i*4); - valid = (section & EMIF_SDRC_ADDRSPC_MASK) >> - (EMIF_SDRC_ADDRSPC_SHIFT); - addr = section & EMIF_SYS_ADDR_MASK; - - /* See if the address is valid */ - if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) && - (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) { - size = ((section & EMIF_SYS_SIZE_MASK) >> - EMIF_SYS_SIZE_SHIFT); - size = 1 << size; - size *= SZ_16M; - - if (valid != DMM_SDRC_ADDR_SPC_INVALID) { - if (!sdram_start || (addr < sdram_start)) - sdram_start = addr; - if (!sdram_end || ((addr + size) > sdram_end)) - sdram_end = addr + size; - } else { - trap_size = size; - trap_start = addr; - } - } - } - - if ((trap_start >= sdram_start) && (trap_start < sdram_end)) - total_size = (sdram_end - sdram_start) - (trap_size); - else - total_size = sdram_end - sdram_start; - - return total_size; -} - - -/* - * Routine: dram_init - * Description: sets uboots idea of sdram size - */ -int dram_init(void) -{ - sdram_init(); - gd->ram_size = omap_sdram_size(); - return 0; -} - -/* - * Print board information - */ -int checkboard(void) -{ - puts(sysinfo.board_string); - return 0; -} - -/* - * get_device_type(): tell if GP/HS/EMU/TST - */ -u32 get_device_type(void) -{ - return (readl((*ctrl)->control_status) & - (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT; -} - -#if defined(CONFIG_DISPLAY_CPUINFO) -/* - * Print CPU information - */ -int print_cpuinfo(void) -{ - puts("CPU : "); - omap_rev_string(); - - return 0; -} -#endif diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S deleted file mode 100644 index 8ce12c8..0000000 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Author : - * Aneesh V <aneesh@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <config.h> -#include <asm/arch/omap.h> -#include <asm/omap_common.h> -#include <asm/arch/spl.h> -#include <linux/linkage.h> - -.arch_extension sec - -#ifdef CONFIG_SPL -ENTRY(save_boot_params) - ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS - str r0, [r1] - b save_boot_params_ret -ENDPROC(save_boot_params) - -#if !defined(CONFIG_TI_SECURE_DEVICE) && defined(CONFIG_ARMV7_LPAE) -ENTRY(switch_to_hypervisor) - -/* - * Switch to hypervisor mode - */ - adr r0, save_sp - str sp, [r0] - adr r1, restore_from_hyp - ldr r0, =0x102 - b omap_smc1 -restore_from_hyp: - adr r0, save_sp - ldr sp, [r0] - MRC p15, 4, R0, c1, c0, 0 - ldr r1, =0X1004 @Set cache enable bits for hypervisor mode - orr r0, r0, r1 - MCR p15, 4, R0, c1, c0, 0 - b switch_to_hypervisor_ret -save_sp: - .word 0x0 -ENDPROC(switch_to_hypervisor) -#endif -#endif - -ENTRY(omap_smc1) - push {r4-r12, lr} @ save registers - ROM code may pollute - @ our registers - mov r12, r0 @ Service - mov r0, r1 @ Argument - - dsb - dmb - smc 0 @ SMC #0 to enter monitor mode - @ call ROM Code API for the service requested - pop {r4-r12, pc} -ENDPROC(omap_smc1) - -ENTRY(omap_smc_sec) - push {r4-r12, lr} @ save registers - ROM code may pollute - @ our registers - mov r6, #0xFF @ Indicate new Task call - mov r12, #0x00 @ Secure Service ID in R12 - - dsb - dmb - smc 0 @ SMC #0 to enter monitor mode - - b omap_smc_sec_end @ exit at end of the service execution - nop - - @ In case of IRQ happening in Secure, then ARM will branch here. - @ At that moment, IRQ will be pending and ARM will jump to Non Secure - @ IRQ handler - mov r12, #0xFE - - dsb - dmb - smc 0 @ SMC #0 to enter monitor mode - -omap_smc_sec_end: - pop {r4-r12, pc} -ENDPROC(omap_smc_sec) diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c deleted file mode 100644 index d72e82e..0000000 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Author : - * Mansoor Ahamed <mansoor.ahamed@ti.com> - * - * Initial Code from: - * Manikandan Pillai <mani.pillai@ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mem.h> -#include <asm/arch/sys_proto.h> -#include <command.h> -#include <linux/mtd/omap_gpmc.h> -#include <jffs2/load_kernel.h> - -const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE; - -#if defined(CONFIG_NOR) -char gpmc_cs0_flash = MTD_DEV_TYPE_NOR; -#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) -char gpmc_cs0_flash = MTD_DEV_TYPE_NAND; -#elif defined(CONFIG_CMD_ONENAND) -char gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; -#else -char gpmc_cs0_flash = -1; -#endif - -#if defined(CONFIG_OMAP34XX) -/******************************************************** - * mem_ok() - test used to see if timings are correct - * for a part. Helps in guessing which part - * we are currently using. - *******************************************************/ -u32 mem_ok(u32 cs) -{ - u32 val1, val2, addr; - u32 pattern = 0x12345678; - - addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); - - writel(0x0, addr + 0x400); /* clear pos A */ - writel(pattern, addr); /* pattern to pos B */ - writel(0x0, addr + 4); /* remove pattern off the bus */ - val1 = readl(addr + 0x400); /* get pos A value */ - val2 = readl(addr); /* get val2 */ - writel(0x0, addr + 0x400); /* clear pos A */ - - if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */ - return 0; - else - return 1; -} -#endif - -void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, - u32 base, u32 size) -{ - writel(0, &cs->config7); - sdelay(1000); - /* Delay for settling */ - writel(gpmc_config[0], &cs->config1); - writel(gpmc_config[1], &cs->config2); - writel(gpmc_config[2], &cs->config3); - writel(gpmc_config[3], &cs->config4); - writel(gpmc_config[4], &cs->config5); - writel(gpmc_config[5], &cs->config6); - /* Enable the config */ - writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | - (1 << 6)), &cs->config7); - sdelay(2000); -} - -void set_gpmc_cs0(int flash_type) -{ - const u32 *gpmc_regs; - u32 base, size; -#if defined(CONFIG_NOR) - const u32 gpmc_regs_nor[GPMC_MAX_REG] = { - STNOR_GPMC_CONFIG1, - STNOR_GPMC_CONFIG2, - STNOR_GPMC_CONFIG3, - STNOR_GPMC_CONFIG4, - STNOR_GPMC_CONFIG5, - STNOR_GPMC_CONFIG6, - STNOR_GPMC_CONFIG7 - }; -#endif -#if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) - const u32 gpmc_regs_nand[GPMC_MAX_REG] = { - M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, - 0 - }; -#endif -#if defined(CONFIG_CMD_ONENAND) - const u32 gpmc_regs_onenand[GPMC_MAX_REG] = { - ONENAND_GPMC_CONFIG1, - ONENAND_GPMC_CONFIG2, - ONENAND_GPMC_CONFIG3, - ONENAND_GPMC_CONFIG4, - ONENAND_GPMC_CONFIG5, - ONENAND_GPMC_CONFIG6, - 0 - }; -#endif - - switch (flash_type) { -#if defined(CONFIG_NOR) - case MTD_DEV_TYPE_NOR: - gpmc_regs = gpmc_regs_nor; - base = CONFIG_SYS_FLASH_BASE; - size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : - ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : - ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : - ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : - GPMC_SIZE_16M))); - break; -#endif -#if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) - case MTD_DEV_TYPE_NAND: - gpmc_regs = gpmc_regs_nand; - base = CONFIG_SYS_NAND_BASE; - size = GPMC_SIZE_16M; - break; -#endif -#if defined(CONFIG_CMD_ONENAND) - case MTD_DEV_TYPE_ONENAND: - gpmc_regs = gpmc_regs_onenand; - base = CONFIG_SYS_ONENAND_BASE; - size = GPMC_SIZE_128M; - break; -#endif - default: - /* disable the GPMC0 config set by ROM code */ - writel(0, &gpmc_cfg->cs[0].config7); - sdelay(1000); - return; - } - - /* enable chip-select specific configurations */ - enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); -} - -/***************************************************** - * gpmc_init(): init gpmc bus - * Init GPMC for x16, MuxMode (SDRAM in x32). - * This code can only be executed from SRAM or SDRAM. - *****************************************************/ -void gpmc_init(void) -{ - /* global settings */ - writel(0x00000008, &gpmc_cfg->sysconfig); - writel(0x00000000, &gpmc_cfg->irqstatus); - writel(0x00000000, &gpmc_cfg->irqenable); - /* disable timeout, set a safe reset value */ - writel(0x00001ff0, &gpmc_cfg->timeout_control); - writel(gpmc_cs0_flash == MTD_DEV_TYPE_NOR ? - 0x00000200 : 0x00000012, &gpmc_cfg->config); - - set_gpmc_cs0(gpmc_cs0_flash); -} diff --git a/arch/arm/cpu/armv7/omap-common/omap-cache.c b/arch/arm/cpu/armv7/omap-common/omap-cache.c deleted file mode 100644 index b37163a..0000000 --- a/arch/arm/cpu/armv7/omap-common/omap-cache.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * - * Common functions for OMAP4/5 based boards - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Author : - * Aneesh V <aneesh@ti.com> - * Steve Sakoman <steve@sakoman.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/cache.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Without LPAE short descriptors are used - * Set C - Cache Bit3 - * Set B - Buffer Bit2 - * The last 2 bits set to 0b10 - * Do Not set XN bit4 - * So value is 0xe - * - * With LPAE cache configuration happens via MAIR0 register - * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF. - * 0xFF maps to Cache writeback with Read and Write Allocate set - * The bits[1:0] should have the value 0b01 for the first level - * descriptor. - * So the value is 0xd - */ - -#ifdef CONFIG_ARMV7_LPAE -#define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC -#else -#define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK -#endif - -#define ARMV7_DOMAIN_CLIENT 1 -#define ARMV7_DOMAIN_MASK (0x3 << 0) - -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} - -void dram_bank_mmu_setup(int bank) -{ - bd_t *bd = gd->bd; - int i; - - u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; - u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; - u32 end = start + size; - - debug("%s: bank: %d\n", __func__, bank); - for (i = start; i < end; i++) - set_section_dcache(i, ARMV7_DCACHE_POLICY); -} - -void arm_init_domains(void) -{ - u32 reg; - - reg = get_dacr(); - /* - * Set DOMAIN to client access so that all permissions - * set in pagetables are validated by the mmu. - */ - reg &= ~ARMV7_DOMAIN_MASK; - reg |= ARMV7_DOMAIN_CLIENT; - set_dacr(reg); -} diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c deleted file mode 100644 index e02e3ec..0000000 --- a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * TI PIPE3 PHY - * - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <sata.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <asm/io.h> -#include <linux/errno.h> -#include "pipe3-phy.h" - -/* PLLCTRL Registers */ -#define PLL_STATUS 0x00000004 -#define PLL_GO 0x00000008 -#define PLL_CONFIGURATION1 0x0000000C -#define PLL_CONFIGURATION2 0x00000010 -#define PLL_CONFIGURATION3 0x00000014 -#define PLL_CONFIGURATION4 0x00000020 - -#define PLL_REGM_MASK 0x001FFE00 -#define PLL_REGM_SHIFT 9 -#define PLL_REGM_F_MASK 0x0003FFFF -#define PLL_REGM_F_SHIFT 0 -#define PLL_REGN_MASK 0x000001FE -#define PLL_REGN_SHIFT 1 -#define PLL_SELFREQDCO_MASK 0x0000000E -#define PLL_SELFREQDCO_SHIFT 1 -#define PLL_SD_MASK 0x0003FC00 -#define PLL_SD_SHIFT 10 -#define SET_PLL_GO 0x1 -#define PLL_TICOPWDN BIT(16) -#define PLL_LDOPWDN BIT(15) -#define PLL_LOCK 0x2 -#define PLL_IDLE 0x1 - -/* PHY POWER CONTROL Register */ -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE - -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000 -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16 - -#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3 -#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0 - - -#define PLL_IDLE_TIME 100 /* in milliseconds */ -#define PLL_LOCK_TIME 100 /* in milliseconds */ - -static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset) -{ - return __raw_readl(addr + offset); -} - -static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset, - u32 data) -{ - __raw_writel(data, addr + offset); -} - -static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3 - *pipe3) -{ - u32 rate; - struct pipe3_dpll_map *dpll_map = pipe3->dpll_map; - - rate = get_sys_clk_freq(); - - for (; dpll_map->rate; dpll_map++) { - if (rate == dpll_map->rate) - return &dpll_map->params; - } - - printf("%s: No DPLL configuration for %u Hz SYS CLK\n", - __func__, rate); - return NULL; -} - - -static int omap_pipe3_wait_lock(struct omap_pipe3 *phy) -{ - u32 val; - int timeout = PLL_LOCK_TIME; - - do { - mdelay(1); - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if (val & PLL_LOCK) - break; - } while (--timeout); - - if (!(val & PLL_LOCK)) { - printf("%s: DPLL failed to lock\n", __func__); - return -EBUSY; - } - - return 0; -} - -static int omap_pipe3_dpll_program(struct omap_pipe3 *phy) -{ - u32 val; - struct pipe3_dpll_params *dpll_params; - - dpll_params = omap_pipe3_get_dpll_params(phy); - if (!dpll_params) { - printf("%s: Invalid DPLL parameters\n", __func__); - return -EINVAL; - } - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); - val &= ~PLL_REGN_MASK; - val |= dpll_params->n << PLL_REGN_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - val &= ~PLL_SELFREQDCO_MASK; - val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); - val &= ~PLL_REGM_MASK; - val |= dpll_params->m << PLL_REGM_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); - val &= ~PLL_REGM_F_MASK; - val |= dpll_params->mf << PLL_REGM_F_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); - val &= ~PLL_SD_MASK; - val |= dpll_params->sd << PLL_SD_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); - - omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); - - return omap_pipe3_wait_lock(phy); -} - -static void omap_control_phy_power(struct omap_pipe3 *phy, int on) -{ - u32 val, rate; - - val = readl(phy->power_reg); - - rate = get_sys_clk_freq(); - rate = rate/1000000; - - if (on) { - val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK); - val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; - val |= rate << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; - } else { - val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; - val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; - } - - writel(val, phy->power_reg); -} - -int phy_pipe3_power_on(struct omap_pipe3 *phy) -{ - int ret; - u32 val; - - /* Program the DPLL only if not locked */ - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if (!(val & PLL_LOCK)) { - ret = omap_pipe3_dpll_program(phy); - if (ret) - return ret; - } else { - /* else just bring it out of IDLE mode */ - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - if (val & PLL_IDLE) { - val &= ~PLL_IDLE; - omap_pipe3_writel(phy->pll_ctrl_base, - PLL_CONFIGURATION2, val); - ret = omap_pipe3_wait_lock(phy); - if (ret) - return ret; - } - } - - /* Power up the PHY */ - omap_control_phy_power(phy, 1); - - return 0; -} - -int phy_pipe3_power_off(struct omap_pipe3 *phy) -{ - u32 val; - int timeout = PLL_IDLE_TIME; - - /* Power down the PHY */ - omap_control_phy_power(phy, 0); - - /* Put DPLL in IDLE mode */ - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - val |= PLL_IDLE; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); - - /* wait for LDO and Oscillator to power down */ - do { - mdelay(1); - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) - break; - } while (--timeout); - - if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { - printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n", - __func__, val); - return -EBUSY; - } - - return 0; -} - diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.h b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h deleted file mode 100644 index 441f49a..0000000 --- a/arch/arm/cpu/armv7/omap-common/pipe3-phy.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * TI PIPE3 PHY - * - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __OMAP_PIPE3_PHY_H -#define __OMAP_PIPE3_PHY_H - -struct pipe3_dpll_params { - u16 m; - u8 n; - u8 freq:3; - u8 sd; - u32 mf; -}; - -struct pipe3_dpll_map { - unsigned long rate; - struct pipe3_dpll_params params; -}; - -struct omap_pipe3 { - void __iomem *pll_ctrl_base; - void __iomem *power_reg; - struct pipe3_dpll_map *dpll_map; -}; - - -int phy_pipe3_power_on(struct omap_pipe3 *phy); -int phy_pipe3_power_off(struct omap_pipe3 *pipe3); - -#endif /* __OMAP_PIPE3_PHY_H */ diff --git a/arch/arm/cpu/armv7/omap-common/reset.c b/arch/arm/cpu/armv7/omap-common/reset.c deleted file mode 100644 index 91ad031..0000000 --- a/arch/arm/cpu/armv7/omap-common/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * - * Common layer for reset related functionality of OMAP based socs. - * - * (C) Copyright 2012 - * Texas Instruments, <www.ti.com> - * - * Sricharan R <r.sricharan@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <config.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <linux/compiler.h> - -void __weak reset_cpu(unsigned long ignored) -{ - writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); -} - -u32 __weak warm_reset(void) -{ - return (readl(PRM_RSTST) & PRM_RSTST_WARM_RESET_MASK); -} - -void __weak setup_warmreset_time(void) -{ -} diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c deleted file mode 100644 index 2c2d1bc..0000000 --- a/arch/arm/cpu/armv7/omap-common/sata.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * TI SATA platform driver - * - * (C) Copyright 2013 - * Texas Instruments, <www.ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <ahci.h> -#include <scsi.h> -#include <asm/arch/clock.h> -#include <asm/arch/sata.h> -#include <sata.h> -#include <asm/io.h> -#include "pipe3-phy.h" - -static struct pipe3_dpll_map dpll_map_sata[] = { - {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */ - {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */ - {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ - {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */ - {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */ - {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */ - { }, /* Terminator */ -}; - -struct omap_pipe3 sata_phy = { - .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE, - /* .power_reg is updated at runtime */ - .dpll_map = dpll_map_sata, -}; - -int init_sata(int dev) -{ - int ret; - u32 val; - - u32 const clk_domains_sata[] = { - 0 - }; - - u32 const clk_modules_hw_auto_sata[] = { - (*prcm)->cm_l3init_ocp2scp3_clkctrl, - 0 - }; - - u32 const clk_modules_explicit_en_sata[] = { - (*prcm)->cm_l3init_sata_clkctrl, - 0 - }; - - do_enable_clocks(clk_domains_sata, - clk_modules_hw_auto_sata, - clk_modules_explicit_en_sata, - 0); - - /* Enable optional functional clock for SATA */ - setbits_le32((*prcm)->cm_l3init_sata_clkctrl, - SATA_CLKCTRL_OPTFCLKEN_MASK); - - sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata; - - /* Power up the PHY */ - phy_pipe3_power_on(&sata_phy); - - /* Enable SATA module, No Idle, No Standby */ - val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO; - writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG); - - ret = ahci_init((void __iomem *)DWC_AHSATA_BASE); - - return ret; -} - -int reset_sata(int dev) -{ - return 0; -} - -/* On OMAP platforms SATA provides the SCSI subsystem */ -void scsi_init(void) -{ - init_sata(0); - scsi_scan(1); -} - -void scsi_bus_reset(void) -{ - ahci_reset((void __iomem *)DWC_AHSATA_BASE); - ahci_init((void __iomem *)DWC_AHSATA_BASE); -} diff --git a/arch/arm/cpu/armv7/omap-common/sec-common.c b/arch/arm/cpu/armv7/omap-common/sec-common.c deleted file mode 100644 index 246a239..0000000 --- a/arch/arm/cpu/armv7/omap-common/sec-common.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * - * Common security related functions for OMAP devices - * - * (C) Copyright 2016 - * Texas Instruments, <www.ti.com> - * - * Daniel Allred <d-allred@ti.com> - * Andreas Dannenberg <dannenberg@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <stdarg.h> - -#include <asm/arch/sys_proto.h> -#include <asm/omap_common.h> -#include <asm/omap_sec_common.h> -#include <asm/spl.h> -#include <spl.h> - -/* Index for signature verify ROM API */ -#define API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX (0x0000000E) - -static uint32_t secure_rom_call_args[5] __aligned(ARCH_DMA_MINALIGN); - -u32 secure_rom_call(u32 service, u32 proc_id, u32 flag, ...) -{ - int i; - u32 num_args; - va_list ap; - - va_start(ap, flag); - - num_args = va_arg(ap, u32); - - if (num_args > 4) - return 1; - - /* Copy args to aligned args structure */ - for (i = 0; i < num_args; i++) - secure_rom_call_args[i + 1] = va_arg(ap, u32); - - secure_rom_call_args[0] = num_args; - - va_end(ap); - - /* if data cache is enabled, flush the aligned args structure */ - flush_dcache_range( - (unsigned int)&secure_rom_call_args[0], - (unsigned int)&secure_rom_call_args[0] + - roundup(sizeof(secure_rom_call_args), ARCH_DMA_MINALIGN)); - - return omap_smc_sec(service, proc_id, flag, secure_rom_call_args); -} - -static u32 find_sig_start(char *image, size_t size) -{ - char *image_end = image + size; - char *sig_start_magic = "CERT_"; - int magic_str_len = strlen(sig_start_magic); - char *ch; - - while (--image_end > image) { - if (*image_end == '_') { - ch = image_end - magic_str_len + 1; - if (!strncmp(ch, sig_start_magic, magic_str_len)) - return (u32)ch; - } - } - return 0; -} - -int secure_boot_verify_image(void **image, size_t *size) -{ - int result = 1; - u32 cert_addr, sig_addr; - size_t cert_size; - - /* Perform cache writeback on input buffer */ - flush_dcache_range( - (u32)*image, - (u32)*image + roundup(*size, ARCH_DMA_MINALIGN)); - - cert_addr = (uint32_t)*image; - sig_addr = find_sig_start((char *)*image, *size); - - if (sig_addr == 0) { - printf("No signature found in image!\n"); - result = 1; - goto auth_exit; - } - - *size = sig_addr - cert_addr; /* Subtract out the signature size */ - cert_size = *size; - - /* Check if image load address is 32-bit aligned */ - if (!IS_ALIGNED(cert_addr, 4)) { - printf("Image is not 4-byte aligned!\n"); - result = 1; - goto auth_exit; - } - - /* Image size also should be multiple of 4 */ - if (!IS_ALIGNED(cert_size, 4)) { - printf("Image size is not 4-byte aligned!\n"); - result = 1; - goto auth_exit; - } - - /* Call ROM HAL API to verify certificate signature */ - debug("%s: load_addr = %x, size = %x, sig_addr = %x\n", __func__, - cert_addr, cert_size, sig_addr); - - result = secure_rom_call( - API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX, 0, 0, - 4, cert_addr, cert_size, sig_addr, 0xFFFFFFFF); -auth_exit: - if (result != 0) { - printf("Authentication failed!\n"); - printf("Return Value = %08X\n", result); - hang(); - } - - /* - * Output notification of successful authentication as well the name of - * the signing certificate used to re-assure the user that the secure - * code is being processed as expected. However suppress any such log - * output in case of building for SPL and booting via YMODEM. This is - * done to avoid disturbing the YMODEM serial protocol transactions. - */ - if (!(IS_ENABLED(CONFIG_SPL_BUILD) && - IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) && - spl_boot_device() == BOOT_DEVICE_UART)) - printf("Authentication passed: %s\n", (char *)sig_addr); - - return result; -} diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c deleted file mode 100644 index 49e3a97..0000000 --- a/arch/arm/cpu/armv7/omap-common/timer.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2008 - * Texas Instruments - * - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Moahmmed Khasim <khasim@ti.com> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * Alex Zuepke <azu@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/clock.h> - -DECLARE_GLOBAL_DATA_PTR; - -static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; - -/* - * Nothing really to do with interrupts, just starts up a counter. - */ - -#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV)) -#define TIMER_OVERFLOW_VAL 0xffffffff -#define TIMER_LOAD_VAL 0 - -int timer_init(void) -{ - /* start the counter ticking up, reload value on overflow */ - writel(TIMER_LOAD_VAL, &timer_base->tldr); - /* enable timer */ - writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, - &timer_base->tclr); - - return 0; -} - -/* - * timer without interrupts - */ -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* delay x useconds */ -void __udelay(unsigned long usec) -{ - long tmo = usec * (TIMER_CLOCK / 1000) / 1000; - unsigned long now, last = readl(&timer_base->tcrr); - - while (tmo > 0) { - now = readl(&timer_base->tcrr); - if (last > now) /* count up timer overflow */ - tmo -= TIMER_OVERFLOW_VAL - last + now + 1; - else - tmo -= now - last; - last = now; - } -} - -ulong get_timer_masked(void) -{ - /* current tick value */ - ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); - - if (now >= gd->arch.lastinc) { /* normal mode (non roll) */ - /* move stamp fordward with absoulte diff ticks */ - gd->arch.tbl += (now - gd->arch.lastinc); - } else { /* we have rollover of incrementer */ - gd->arch.tbl += ((TIMER_OVERFLOW_VAL / (TIMER_CLOCK / - CONFIG_SYS_HZ)) - gd->arch.lastinc) + now; - } - gd->arch.lastinc = now; - return gd->arch.tbl; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds b/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds deleted file mode 100644 index 8fec715..0000000 --- a/arch/arm/cpu/armv7/omap-common/u-boot-spl.lds +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * Aneesh V <aneesh@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ - LENGTH = CONFIG_SPL_MAX_SIZE } -MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ - LENGTH = CONFIG_SPL_BSS_MAX_SIZE } - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - .text : - { - __start = .; - *(.vectors) - arch/arm/cpu/armv7/start.o (.text*) - *(.text*) - } >.sram - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram - - . = ALIGN(4); - .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } >.sram - - . = ALIGN(4); - __image_copy_end = .; - - .end : - { - *(.__end) - } - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } >.sdram -} diff --git a/arch/arm/cpu/armv7/omap-common/utils.c b/arch/arm/cpu/armv7/omap-common/utils.c deleted file mode 100644 index 2d03ebf..0000000 --- a/arch/arm/cpu/armv7/omap-common/utils.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright 2011 Linaro Limited - * Aneesh V <aneesh@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <asm/arch/sys_proto.h> -static void do_cancel_out(u32 *num, u32 *den, u32 factor) -{ - while (1) { - if (((*num)/factor*factor == (*num)) && - ((*den)/factor*factor == (*den))) { - (*num) /= factor; - (*den) /= factor; - } else - break; - } -} - -/* - * Cancel out the denominator and numerator of a fraction - * to get smaller numerator and denominator. - */ -void cancel_out(u32 *num, u32 *den, u32 den_limit) -{ - do_cancel_out(num, den, 2); - do_cancel_out(num, den, 3); - do_cancel_out(num, den, 5); - do_cancel_out(num, den, 7); - do_cancel_out(num, den, 11); - do_cancel_out(num, den, 13); - do_cancel_out(num, den, 17); - while ((*den) > den_limit) { - *num /= 2; - /* - * Round up the denominator so that the final fraction - * (num/den) is always <= the desired value - */ - *den = (*den + 1) / 2; - } -} - -__weak void omap_die_id(unsigned int *die_id) -{ - die_id[0] = die_id[1] = die_id[2] = die_id[3] = 0; -} - -void omap_die_id_serial(void) -{ - unsigned int die_id[4] = { 0 }; - char serial_string[17] = { 0 }; - - omap_die_id((unsigned int *)&die_id); - - if (!getenv("serial#")) { - snprintf(serial_string, sizeof(serial_string), - "%08x%08x", die_id[0], die_id[3]); - - setenv("serial#", serial_string); - } -} - -void omap_die_id_get_board_serial(struct tag_serialnr *serialnr) -{ - char *serial_string; - unsigned long long serial; - - serial_string = getenv("serial#"); - - if (serial_string) { - serial = simple_strtoull(serial_string, NULL, 16); - - serialnr->high = (unsigned int) (serial >> 32); - serialnr->low = (unsigned int) (serial & 0xffffffff); - } else { - serialnr->high = 0; - serialnr->low = 0; - } -} - -void omap_die_id_usbethaddr(void) -{ - unsigned int die_id[4] = { 0 }; - unsigned char mac[6] = { 0 }; - - omap_die_id((unsigned int *)&die_id); - - if (!getenv("usbethaddr")) { - /* - * Create a fake MAC address from the processor ID code. - * First byte is 0x02 to signify locally administered. - */ - mac[0] = 0x02; - mac[1] = die_id[3] & 0xff; - mac[2] = die_id[2] & 0xff; - mac[3] = die_id[1] & 0xff; - mac[4] = die_id[0] & 0xff; - mac[5] = (die_id[0] >> 8) & 0xff; - - eth_setenv_enetaddr("usbethaddr", mac); - } -} - -void omap_die_id_display(void) -{ - unsigned int die_id[4] = { 0 }; - - omap_die_id(die_id); - - printf("OMAP die ID: %08x%08x%08x%08x\n", die_id[3], die_id[2], - die_id[1], die_id[0]); -} diff --git a/arch/arm/cpu/armv7/omap-common/vc.c b/arch/arm/cpu/armv7/omap-common/vc.c deleted file mode 100644 index a68f1d1..0000000 --- a/arch/arm/cpu/armv7/omap-common/vc.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Voltage Controller implementation for OMAP - * - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ - * Nishanth Menon - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <common.h> -#include <asm/omap_common.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/clock.h> - -/* - * Define Master code if there are multiple masters on the I2C_SR bus. - * Normally not required - */ -#ifndef CONFIG_OMAP_VC_I2C_HS_MCODE -#define CONFIG_OMAP_VC_I2C_HS_MCODE 0x0 -#endif - -/* Register defines and masks for VC IP Block */ -/* PRM_VC_CFG_I2C_MODE */ -#define PRM_VC_CFG_I2C_MODE_DFILTEREN_BIT (0x1 << 6) -#define PRM_VC_CFG_I2C_MODE_SRMODEEN_BIT (0x1 << 4) -#define PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT (0x1 << 3) -#define PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT 0x0 -#define PRM_VC_CFG_I2C_MODE_HSMCODE_MASK 0x3 - -/* PRM_VC_CFG_I2C_CLK */ -#define PRM_VC_CFG_I2C_CLK_HSCLL_SHIFT 24 -#define PRM_VC_CFG_I2C_CLK_HSCLL_MASK 0xFF -#define PRM_VC_CFG_I2C_CLK_HSCLH_SHIFT 16 -#define PRM_VC_CFG_I2C_CLK_HSCLH_MASK 0xFF -#define PRM_VC_CFG_I2C_CLK_SCLH_SHIFT 0 -#define PRM_VC_CFG_I2C_CLK_SCLH_MASK 0xFF -#define PRM_VC_CFG_I2C_CLK_SCLL_SHIFT 8 -#define PRM_VC_CFG_I2C_CLK_SCLL_MASK (0xFF << 8) - -/* PRM_VC_VAL_BYPASS */ -#define PRM_VC_VAL_BYPASS_VALID_BIT (0x1 << 24) -#define PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT 0 -#define PRM_VC_VAL_BYPASS_SLAVEADDR_MASK 0x7F -#define PRM_VC_VAL_BYPASS_REGADDR_SHIFT 8 -#define PRM_VC_VAL_BYPASS_REGADDR_MASK 0xFF -#define PRM_VC_VAL_BYPASS_DATA_SHIFT 16 -#define PRM_VC_VAL_BYPASS_DATA_MASK 0xFF - -/** - * omap_vc_init() - Initialization for Voltage controller - * @speed_khz: I2C buspeed in KHz - */ -static void omap_vc_init(u16 speed_khz) -{ - u32 val; - u32 sys_clk_khz, cycles_hi, cycles_low; - - sys_clk_khz = get_sys_clk_freq() / 1000; - - if (speed_khz > 400) { - puts("higher speed requested - throttle to 400Khz\n"); - speed_khz = 400; - } - - /* - * Setup the dedicated I2C controller for Voltage Control - * I2C clk - high period 40% low period 60% - */ - speed_khz /= 10; - cycles_hi = sys_clk_khz * 4 / speed_khz; - cycles_low = sys_clk_khz * 6 / speed_khz; - /* values to be set in register - less by 5 & 7 respectively */ - cycles_hi -= 5; - cycles_low -= 7; - val = (cycles_hi << PRM_VC_CFG_I2C_CLK_SCLH_SHIFT) | - (cycles_low << PRM_VC_CFG_I2C_CLK_SCLL_SHIFT); - writel(val, (*prcm)->prm_vc_cfg_i2c_clk); - - val = CONFIG_OMAP_VC_I2C_HS_MCODE << - PRM_VC_CFG_I2C_MODE_HSMCODE_SHIFT; - /* No HS mode for now */ - val &= ~PRM_VC_CFG_I2C_MODE_HSMODEEN_BIT; - writel(val, (*prcm)->prm_vc_cfg_i2c_mode); -} - -/** - * omap_vc_bypass_send_value() - Send a data using VC Bypass command - * @sa: 7 bit I2C slave address of the PMIC - * @reg_addr: I2C register address(8 bit) address in PMIC - * @reg_data: what 8 bit data to write - */ -int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data) -{ - /* - * Unfortunately we need to loop here instead of a defined time - * use arbitary large value - */ - u32 timeout = 0xFFFF; - u32 reg_val; - - sa &= PRM_VC_VAL_BYPASS_SLAVEADDR_MASK; - reg_addr &= PRM_VC_VAL_BYPASS_REGADDR_MASK; - reg_data &= PRM_VC_VAL_BYPASS_DATA_MASK; - - /* program VC to send data */ - reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT | - reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT | - reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT; - writel(reg_val, (*prcm)->prm_vc_val_bypass); - - /* Signal VC to send data */ - writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, - (*prcm)->prm_vc_val_bypass); - - /* Wait on VC to complete transmission */ - do { - reg_val = readl((*prcm)->prm_vc_val_bypass) & - PRM_VC_VAL_BYPASS_VALID_BIT; - if (!reg_val) - break; - - sdelay(100); - } while (--timeout); - - /* Optional: cleanup PRM_IRQSTATUS_Ax */ - /* In case we can do something about it in future.. */ - if (!timeout) - return -1; - - /* All good.. */ - return 0; -} - -void sri2c_init(void) -{ - static int sri2c = 1; - - if (sri2c) { - omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ); - sri2c = 0; - } - return; -} |