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| author | Tom Rini <trini@konsulko.com> | 2016-08-01 22:54:53 (GMT) |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-08-05 11:23:57 (GMT) |
| commit | a78cd8613204188991c192b8dae2de0aae3b1722 (patch) | |
| tree | 1f181c9cffd17bccde12060eb6465544890c5f51 /arch/arm/cpu/armv7/sunxi | |
| parent | 65fcba1251dcb1fc2c48966406145a69fee3a817 (diff) | |
| download | u-boot-fsl-qoriq-a78cd8613204188991c192b8dae2de0aae3b1722.tar.xz | |
ARM: Rework and correct barrier definitions
As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases incomplete isb definitions. This was causing a failure to
boot of the Linux kernel.
In order to solve this problem as well as cover any corner cases that we
may also have had a number of changes are made in order to consolidate
things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb
definitions. This however introduces another complexity. Due to
needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
a comment about it. Now that we can always know what the target CPU is
capable off we can get always do the correct thing for the barrier. The
final part of this is that need to be consistent everywhere and call
isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
function names in others.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Sandy Patterson <apatterson@sightlogix.com>
Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Reported-by: Sandy Patterson <apatterson@sightlogix.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/cpu/armv7/sunxi')
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/psci.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index 7ac8406..766b8c7 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -53,16 +53,16 @@ static void __secure __mdelay(u32 ms) u32 reg = ONE_MS * ms; cp15_write_cntp_tval(reg); - ISB; + isb(); cp15_write_cntp_ctl(3); do { - ISB; + isb(); reg = cp15_read_cntp_ctl(); } while (!(reg & BIT(2))); cp15_write_cntp_ctl(0); - ISB; + isb(); } static void __secure clamp_release(u32 __maybe_unused *clamp) @@ -164,7 +164,7 @@ static u32 __secure cp15_read_scr(void) static void __secure cp15_write_scr(u32 scr) { asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr)); - ISB; + isb(); } /* @@ -190,7 +190,7 @@ void __secure __irq psci_fiq_enter(void) /* End of interrupt */ writel(reg, GICC_BASE + GICC_EOIR); - DSB; + dsb(); /* Get CPU number */ cpu = (reg >> 10) & 0x7; @@ -242,7 +242,7 @@ void __secure psci_cpu_off(void) /* Ask CPU0 via SGI15 to pull the rug... */ writel(BIT(16) | 15, GICD_BASE + GICD_SGIR); - DSB; + dsb(); /* Wait to be turned off */ while (1) |